JP2001092675A - Microcomputer and device for rewriting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute an instruction to use data written in a vector table region in a loader region in which on-board rewriting is unavailable by realizing the rewriting in the loader region at the time of changing data in the vector table region after a user program is changed in a microcomputer incorporating a flash EEPROM. SOLUTION: At the time of on-board rewriting, the data of a vector table region after program change are written in a rewritable firm region. When an instruction to read the vector table region is executed after the on-board rewriting, an address converter 12 converts an address outputted from a CPU 11 into the address of the film region, and reads the data after change to execut the instruction after change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having an electrically erasable and rewritable flash EEPROM.

[0002]

2. Description of the Related Art In a microcomputer in which a memory for storing a program and a CPU are integrated on one chip,
An increasingly erasable and rewritable flash EEPROM is mounted as a memory for storing programs. This flash EEPROM is an EPRO
As in the case of the microcomputer with the built-in M, there are two methods: a method of rewriting with a PROM writer using a dedicated socket adapter, and an on-board rewriting method of rewriting while mounted on a board.

In on-board rewriting, rewriting can be performed by using a rewriting control circuit built in a microcomputer according to a rewriting control program previously written in a ROM. The flash EEPROM is divided into two types of areas: a loader area for writing a rewrite control program, and a firmware area for writing a unique user program according to the use of the microcomputer.

In rewriting by a PROM writer, both the loader area and the firmware area can be rewritten.
In on-board rewriting, only the firmware area is rewritten.

FIG. 2 is a view showing a memory address area of a flash EEPROM, and FIG. 3 is a detailed view of an area A in FIG. The area A in FIG. 2 is divided into n areas of vector 1 to vector n as shown in FIG. 3, and is a vector table area for specifying a branch destination address.

FIGS. 4 and 5 show examples of program instructions of a microcomputer having a built-in flash EEPROM.
It is assumed that the data has been written in the firmware area. Instruction 1 in FIG. 4 is an instruction for calling a function called ABC.
When the instruction 1 is read by the CPU, the program counter of the CPU becomes the value of the start address of the function ABC and branches to the function ABC. The instruction 2 in FIG. 5 is an instruction for causing the CPU to perform the same operation as the instruction 1. Here, it is assumed that the value of the start address of the function ABC is written in the vector 1 area shown in FIG. When the instruction 2 is read by the CPU, the program counter of the CPU first becomes the address of the vector 1 area in FIG. 3, reads the value of the vector 1 area, and then the program counter becomes the value written in the vector 1. , Branches to the address written in the vector 1 area, that is, the function ABC.

As described above, both the instruction 1 and the instruction 2 are operations for calling the function ABC, but the instruction 1 directly specifies an address, whereas the instruction 2 only specifies a vector number. This is a vector indirect branch instruction. If a 32-bit memory is required to specify an address and an 8-bit memory is required to specify a vector number, the instruction code size for the same instruction may be reduced by 24 bits for instruction 2 than for instruction 1. it can. Therefore, in a program that calls the same function many times, using the instruction 2 can reduce the code size of the entire program much more than using the instruction 1, and the capacity of the flash EEPROM built in the microcomputer can be reduced.

[0008]

Here, the vector 1 area necessary for executing the instruction 2 is located in the area A in the loader area shown in FIG. When the user program written in the firmware area is changed and the program in the firmware area is rewritten by on-board rewriting, the contents of the area A may be changed. However, since the CPU rewrites the program data in the firmware area by executing the program instruction in the loader area, the loader area cannot be rewritten. Therefore, when developing the user program, it is necessary to consider that the data in the area A, for example, the value of the vector 1 used in the instruction 2 does not change, and the program efficiency cannot be increased due to the restriction. Increase in size. If it is impossible to change the user program without changing the data in the area A, an instruction using the data in the area A, such as the instruction 2, cannot be used, and the program code size increases.

The present invention solves the above-mentioned conventional problem. Even if data in the vector table area (area A) is changed during on-board rewriting, the vector indirect branch instruction such as the instruction 2 described above can be normally executed. It is an object of the present invention to provide a microcomputer and a rewriting device capable of reducing the program code size by eliminating the restrictions on the user program development while executing the program.

[0010]

In order to achieve this object, a microcomputer according to the present invention has a flash EEPROM having a loader area including a vector table area and a firmware area, and is pre-written in a vector table area. And a CPU having a function capable of indirect branching according to a value.
A memory state determination circuit for determining whether the EPROM has been rewritten by a PROM writer or a state after onboard rewriting, and an address area determination unit for determining whether an address output from the CPU is an address of a vector table area And flash EEPROM by the memory state determination circuit.
Only when M is determined to be in the state after on-board rewriting and the address area determination unit determines that the address output from the CPU is the address of the vector table area, the address output from the CPU is updated. An address conversion / non-conversion circuit is provided, which converts the address into an area address and supplies the address to the flash EEPROM, and otherwise supplies the address output from the CPU to the flash EEPROM as it is.

According to this configuration, at the time of on-board rewriting, the data of the branch destination address that should be originally written in the vector table area in the loader area is written in the firmware area. When the operation of reading the data in the vector table area is performed, the address output from the CPU is converted into the address of the firmware area, and the data in the firmware area is read. However, the vector indirect branch instruction can be executed normally. This eliminates restrictions on user program development and reduces the program code size.

Further, the microcomputer rewriting device of the present invention inputs a program file to perform on-board rewriting of a flash EEPROM built in the microcomputer according to the first aspect of the present invention, and stores the program file in a vector table area in the program file. It has a function of automatically converting data to be written so that the data is written to the firmware area. By performing on-board rewriting with this rewriting device, the user is originally written to the vector table area in the loader area. A program can be developed without being aware that the data at the desired branch destination address is written to the firmware area.

[0013]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a microcomputer with a built-in flash EEPROM according to an embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a CPU which includes a program counter, an instruction decoding unit, an arithmetic unit, and operates based on data read from a memory;
Is an address converter for converting an address output from the CPU 11, 13 is an address area determining unit, 14 is a memory state determining circuit for determining a rewriting state of the flash EEPROM 16, 15 is a selection circuit, and 16 is a flash EEPROM.
ROM. The address conversion / non-conversion circuit includes an address converter 12 and a selection circuit 15.

The address area judging section 13 outputs 1 when the address output from the CPU 11 corresponds to the address of the area A shown in FIG. 2, and outputs 0 otherwise.
When the microcomputer starts executing the program instruction, the memory state determination circuit 14 executes the flash EEPROM
The OM 16 has a register that reads the value of the area C shown in FIG. 2 in the OM 16 and stores the value, and outputs the value (0 or 1) written in the area C. In the area C, PR
1 is written when rewriting is performed by the OM writer, and 0 is written when on-board rewriting is performed. When the output of the address area determination unit 13 is 1 and the output of the memory state determination circuit 14 is 0, the selection circuit 15
Output the address input from C, otherwise C
The address input from the PU 11 is output. The address converter 12 converts the address of the area A shown in FIG.

First, the operation of the microcomputer before on-board rewriting will be described. It is assumed that a program has been written to both the loader area and the firmware area shown in FIG. 2 by the PROM writer. Figure 5 shows the farm area.
5 is written in the vector 1 area of FIG. 3 in the area A of FIG. 2, and the start address value of the function ABC in the program of FIG. 5 is written. PR
Flash EEPROM when writing with OM writer
When 1 is written in the area C in the memory 16, the memory state determination circuit 14 outputs 1. Instruction 2 shown in FIG.
When read to 1, the program counter becomes a value indicating the address of the vector 1 area in the area A shown in FIG.
At this time, the address area determination unit 13 outputs 1 and outputs the area A
Is determined, the memory state determination circuit 1
4 is 1, the selection circuit 15 supplies the address output from the CPU 11 to the flash EEPROM 16, reads the data of the vector 1 in the area A from the flash EEPROM 16, and sets the value of the program counter of the CPU 11 to the vector. 1 and the function A of FIG.
Branch to BC.

Next, it is assumed that a change occurs in the user program shown in FIG. 5 and on-board rewriting of the flash EEPROM 16 is performed. When performing on-board rewriting, the head address of the function ABC in the program after the change is written to the area B shown in FIG.

Next, after the on-board rewriting, since 0 is written in the area C at the time of the on-board rewriting, the output of the memory state determination circuit 14 becomes 0. When the instruction 2 shown in FIG. 5 is read by the CPU 11, the program counter becomes a value indicating the address of the vector 1 area in the area A shown in FIG. At this time, the address area judging section 13 judges that the address is in the area A, outputs 1 and outputs
Indicates the output of the address converter 12 (the address of the area B obtained by converting the address of the area A) into the flash EEPROM 1
6, the data of the vector 1 in the area B (the head address of the function ABC after the program is changed) is read out, and
The value of the program counter of the PU 11 becomes the start address of the function ABC, and branches to the function ABC.

As described above, according to the present embodiment, when performing on-board rewriting, the data of the branch destination address (here, the start address of the function ABC) to be written to the area A in the loader area is stored in the firmware area. Is written in the area B of the CPU 11 so that the CPU 11
Performs the operation of reading the data in the area A,
By reading the data in the area B by converting the address output from the address 11 into the address in the area B, even if the data in the area A is changed at the time of on-board rewriting, the instruction 2
Can be normally executed. This eliminates restrictions on user program development, reduces the program code size, and reduces the capacity of the flash EEPROM 16, thereby providing advantages such as a reduction in microcomputer cost.

Next, an on-board rewriting method for a microcomputer having the configuration shown in FIG. 1 will be described. FIG.
1 is a block diagram of a rewriting device of a microcomputer with a built-in flash EEPROM. 17 is a program data converter for processing an input program file, 18
Is a communication control circuit for supplying a rewriting program to the microcomputer, and 19 is a microcomputer having the configuration shown in FIG.

The program data converter 17 copies a portion corresponding to the area A in FIG. The data of the firmware area in the converted program file is controlled by the communication control circuit 18 and supplied to the microcomputer 19. The microcomputer 19 executes the rewrite control program written in the loader area, receives the data to be rewritten from the communication control circuit 18, and rewrites the data in the firmware area.

Here, the operation of the program data converter 17 will be described in detail. As shown in the input data of FIG. 7A, the user creates a program together with the portion of the loader area where on-board rewriting is not performed. However, the part of the rewrite control program is a fixed program. The user rewrites the area A as necessary. When the area A is rewritten, the data in the area C is set to 0.
Keep it. That is, when a change occurs in the content of the area A, the user writes 0 in the area C when creating the program. The area B is left empty when a program is created. The user can freely use only the part after the area C as the program data. Program data converter 17
Then, as shown in FIG. 7B, the data (program A) in the area A is copied to an empty area B. In the actual on-board rewriting process, only the program data in the firmware area is written. That is, the program A in the area B, 0 in the area C, and the user program are used as write data.

As described above, the program data converter 17
2 automatically converts the program data, so that the user of the microcomputer can develop the program without being aware that the area A in FIG.

In the above embodiment, an example in which an instruction for indirectly calling a function by reading data written in the area A has been described. However, a vector indirect branch instruction such as an interrupt processing at the time of occurrence of an interrupt is described. Can also be used.

[0024]

According to the present invention, when performing on-board rewriting, the data of the branch destination address that should be originally written in the vector table area in the loader area is written in the firmware area. When the CPU performs the operation of reading the data in the vector table area, the address output from the CPU is converted to the address in the firmware area, and the data in the firmware area is read. , The vector indirect branch instruction can be executed normally. This eliminates restrictions on user program development, reduces the program code size, and allows the flash EE built in the microcomputer to be used.
Since the capacity of the PROM can be reduced, advantages such as the cost of the microcomputer can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a view showing a memory address area of the flash EEPROM in FIG. 1;

FIG. 3 is an enlarged detailed view of a region A in FIG. 2;

FIG. 4 is a diagram showing an example of a program instruction.

FIG. 5 is a diagram showing an example of a program instruction.

FIG. 6 is a block diagram of a microcomputer rewriting device according to an embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the program data converter of the microcomputer rewriting device according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 CPU 12 Address converter 13 Address area judgment part 14 Memory state judgment circuit 15 Selection circuit 16 Flash EEPROM 17 Program data converter 18 Communication control circuit 19 Microcomputer with built-in EEPROM

Claims (2)

[Claims] 1. A microcomputer comprising: a flash EEPROM having a loader area including a vector table area and a firmware area; and a CPU having a function capable of indirect branching based on a value previously written in the vector table area. A memory state determination circuit for determining whether the flash EEPROM has been rewritten by a PROM writer or a state after on-board rewriting; and whether or not an address output from the CPU is an address of the vector table area. An address area determining unit that determines whether the flash EEPROM is
Only when OM is determined to be in a state after on-board rewriting and the address output from the CPU is determined by the address area determination unit to be an address of the vector table area, the output from the CPU is performed. And an address conversion / non-conversion circuit for supplying an address output from the CPU to the flash EEPROM as it is after converting the address to the address of the firmware area and supplying the address to the flash EEPROM otherwise. A microcomputer characterized by the above-mentioned. 2. A program file is inputted to perform on-board rewriting of a flash EEPROM built in the microcomputer according to claim 1, and data to be written to a vector table area in the program file is written to a firmware area. A microcomputer rewriting device with the function of automatically converting to a file.