JP2001092656A5 - - Google Patents

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Publication number
JP2001092656A5
JP2001092656A5 JP2000269771A JP2000269771A JP2001092656A5 JP 2001092656 A5 JP2001092656 A5 JP 2001092656A5 JP 2000269771 A JP2000269771 A JP 2000269771A JP 2000269771 A JP2000269771 A JP 2000269771A JP 2001092656 A5 JP2001092656 A5 JP 2001092656A5
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JP
Japan
Prior art keywords
instructions
instruction
issue
issue group
group
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JP2000269771A
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English (en)
Japanese (ja)
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JP2001092656A (ja
JP3773769B2 (ja
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Priority claimed from US09/390,199 external-priority patent/US6618802B1/en
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Publication of JP2001092656A publication Critical patent/JP2001092656A/ja
Publication of JP2001092656A5 publication Critical patent/JP2001092656A5/ja
Application granted granted Critical
Publication of JP3773769B2 publication Critical patent/JP3773769B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000269771A 1999-09-07 2000-09-06 命令のインオーダ処理を効率的に実行するスーパースケーラ処理システム及び方法 Expired - Fee Related JP3773769B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/390199 1999-09-07
US09/390,199 US6618802B1 (en) 1999-09-07 1999-09-07 Superscalar processing system and method for selectively stalling instructions within an issue group

Publications (3)

Publication Number Publication Date
JP2001092656A JP2001092656A (ja) 2001-04-06
JP2001092656A5 true JP2001092656A5 (https=) 2005-07-07
JP3773769B2 JP3773769B2 (ja) 2006-05-10

Family

ID=23541515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000269771A Expired - Fee Related JP3773769B2 (ja) 1999-09-07 2000-09-06 命令のインオーダ処理を効率的に実行するスーパースケーラ処理システム及び方法

Country Status (2)

Country Link
US (1) US6618802B1 (https=)
JP (1) JP3773769B2 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885375B2 (en) * 2002-03-11 2005-04-26 Sun Microsystems, Inc. Stalling pipelines in large designs
US20040142620A1 (en) * 2002-09-10 2004-07-22 Fibermark, Inc. Nonwoven fiber webs with poly(phenylene sulfide) binder
WO2006134693A1 (ja) * 2005-06-15 2006-12-21 Matsushita Electric Industrial Co., Ltd. プロセッサ
US7627735B2 (en) * 2005-10-21 2009-12-01 Intel Corporation Implementing vector memory operations
US20090210664A1 (en) * 2008-02-15 2009-08-20 Luick David A System and Method for Issue Schema for a Cascaded Pipeline
US20090210677A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline
US20090210669A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Prioritizing Floating-Point Instructions
US8108654B2 (en) * 2008-02-19 2012-01-31 International Business Machines Corporation System and method for a group priority issue schema for a cascaded pipeline
US7877579B2 (en) * 2008-02-19 2011-01-25 International Business Machines Corporation System and method for prioritizing compare instructions
US7865700B2 (en) * 2008-02-19 2011-01-04 International Business Machines Corporation System and method for prioritizing store instructions
US8095779B2 (en) * 2008-02-19 2012-01-10 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US7882335B2 (en) * 2008-02-19 2011-02-01 International Business Machines Corporation System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline
US7984270B2 (en) * 2008-02-19 2011-07-19 International Business Machines Corporation System and method for prioritizing arithmetic instructions
US20090210666A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
US7996654B2 (en) * 2008-02-19 2011-08-09 International Business Machines Corporation System and method for optimization within a group priority issue schema for a cascaded pipeline
US7870368B2 (en) * 2008-02-19 2011-01-11 International Business Machines Corporation System and method for prioritizing branch instructions
US20090210672A1 (en) * 2008-02-19 2009-08-20 Luick David A System and Method for Resolving Issue Conflicts of Load Instructions
JP5436033B2 (ja) * 2009-05-08 2014-03-05 パナソニック株式会社 プロセッサ
CN119003002B (zh) * 2024-07-19 2025-07-11 摩尔线程智能科技(北京)股份有限公司 处理器、显卡、计算机设备以及依赖解除方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2911278B2 (ja) * 1990-11-30 1999-06-23 松下電器産業株式会社 プロセッサ
US6138230A (en) * 1993-10-18 2000-10-24 Via-Cyrix, Inc. Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline
US5592679A (en) * 1994-11-14 1997-01-07 Sun Microsystems, Inc. Apparatus and method for distributed control in a processor architecture
US5958042A (en) * 1996-06-11 1999-09-28 Sun Microsystems, Inc. Grouping logic circuit in a pipelined superscalar processor
US6047368A (en) * 1997-03-31 2000-04-04 Sun Microsystems, Inc. Processor architecture including grouping circuit

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