JP2001092441A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the situation in which unnecessary accesses are conducted to a video memory and a display buffer because image data, that are overwritten by an attribute having a higher display priority and are not displayed, are read from the video memory and being written into the display buffer. SOLUTION: The device is provided with an attribute converting circuit and a source address computing circuit. When display regions of attribute data on a prescribed horizontal one line of a display screen are overlapped, the pixels of an attribute having a lower display priority are disappeared and the display regions on the screen are changed by the disappeared pixels, the changed display regions are made into new display regions by the attribute conversion circuit. If divided, the attribute data are converted into attributes having the number of divisions in which divided display regions are made into new display regions by the attribute converting. The source address computing circuit computes addresses of a video memory, in which corresponding source image data exist, from new display regions converted by the attribute converting circuit. Note that the operation, in which data in the video memory are written into a display buffer for every horizontal display line, is repeatedly conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a video display device.

2. Description of the Related Art A conventional video display apparatus repeatedly writes all source image data indicated by one attribute to a display area of a display buffer in order from an attribute having a lower display priority. Thus, the entire image to be displayed was constituted.
Less than,

The details will be described with reference to FIG. 6a is an attribute memory for storing attributes, 6b is a display buffer for temporarily storing images to be displayed, 6c is a video memory for storing source image data, and 6d is a drawing circuit. The attribute memory stores four attributes from att1 to att4, and indicates addresses indicating areas of the video memory and the display buffer, respectively. The drawing circuit first reads the attribute of att1, and writes image data from the area of att1 of the video memory to the area of att1 of the display buffer. Next, the attribute of att2 is read and the same processing is performed. At this time, the data of att2 is overwritten on the hatched portion of the display buffer, and the image data of att1 is lost. The drawing circuit further performs the processing from att3 to att4 to compose the entire image. Similarly, the image data in the shaded area is overwritten. As described above, since the drawing circuit reads and processes the attribute memory in the order of att1 to att4, the display priority is att1 to att
It becomes higher in the order of t4.

However, according to the above prior art,

FIG. 5 also shows image data that is overwritten by an attribute with a high display priority and that is not displayed, as indicated by the shaded area in FIG. 5, which is read from the video memory and written to the display buffer. Access was to be made. Accordingly, it is an object of the present invention to provide a video display device that does not uselessly access a video memory and a display buffer for image data that is overwritten by an attribute having a high display priority and is not displayed.

In order to solve the above problems, a video memory for storing source image data,
A video memory controller capable of reading data from an arbitrary address of the video memory, a display buffer for temporarily storing data read by the video memory controller, a display buffer controller for managing the display buffer, An attribute memory for storing attribute data such as an address of the source image data stored in the video memory and a display area on the screen, an attribute controller for reading attribute data from the attribute memory, and a predetermined horizontal line on the display screen If the display area of the attribute data overlaps and the pixel of the attribute with the lower display priority disappears, and if the display area on the screen changes due to the lost pixel, the changed display area is newly added. An attribute conversion circuit for converting the attribute data into a display area, and when the attribute data is divided, the attribute display circuit converts the divided display area into a new number of attributes as a new display area; A source address calculating circuit for calculating an address of a video memory in which the corresponding source image data is present from a proper display area, wherein the attribute controller reads the attribute data from the attribute memory, An address of the video memory calculated by the source address calculation circuit from the attribute data corresponding to the line is sent to the video memory controller, and the display converted by the attribute conversion circuit is displayed. Sends the address corresponding to the display area of Ffa to the display buffer controller, the video memory controller reads the source image data required from the address of the video memory received from the attribute controller,
The display buffer controller sends the data to the display buffer controller, and the display buffer controller repeatedly stores the data received from the video memory controller at the address of the display buffer received from the attribute controller for each horizontal display line.

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention

FIG. 1 shows.

FIG. 1 is an operation explanatory block diagram 1. less than

The operation will be described in detail with reference to FIG. The attribute is composed of four, and the display area of the attribute memory is

The settings are as shown in the display buffer of FIG. The vertical counter counts a vertical pointer on the display screen, and one sequence from v0 to the value of ve constitutes one image. Writing of image data to the display buffer is performed for each horizontal line of the pointer indicated by the vertical counter, and when there is a corresponding attribute, an operation of reading necessary data from the video memory and writing it to the display buffer is performed. The attribute controller determines whether each attribute corresponds to the current horizontal pointer by comparing the value of the vertical counter with the start and end of the vertical display area of each attribute and judging whether or not it is contained therein. The vertical counter value from v0
No corresponding attribute if less than v1, v1 to v2
If it is less than v2, it is possible to read the corresponding attribute for each line, such as att2 and att3 if v2 to less than v3, and perform the write operation to the display buffer as needed. Vertical counter value is between v1 and v2
If the value is v12, the attribute controller reads the attribute of att2 and adds the value obtained by subtracting v1 from v12 to the vertical start address y2 of the source image and the vertical address and horizontal start address x1 of the video memory obtained. , The end address x3 to the video memory controller, and the display screen vertical pointer v12, horizontal start address h2, end address h4
To the display buffer controller. The display buffer controller transfers the data received from the video memory controller to the horizontal addresses h2 to h4 of the vertical address v12.
Are sequentially written to complete the drawing of one horizontal line. If the value of the vertical counter is v23, which is between v2 and v3, the corresponding attributes are att2 and att3
Therefore, the same operation as described above is performed for att2 and att3. V34 where the value of the vertical counter is between v3 and v4
, The corresponding attribute is
Att1, att2, and att3 are overlapped with the diagonal lines. The attribute controller divides att1 into att1: 1 and att1: 2 by the attribute conversion circuit.The start h1, end h2-1, and att1: 2 for att1: 1 are used as the horizontal start address and end address of the new display screen. The start h4 + 1 and the end h5-1 are given, and the horizontal x start address and the end address of the new source image are set to att1: 1 at the start x by the source address calculation circuit.
1, end x1 + (h2-1) -h1, start x1 + (h4 + 1) for att1: 2
Give -h1, end x1 + (h5-1) -h1. Further, the attributes att1: 1, att1: 2, att2, and att3 converted by the above operation are sequentially sent to the video memory controller and the display buffer controller, and the rendering of one horizontal line is completed. V67 with vertical counter value between v6 and v7
, The corresponding attribute is
Att1 and att4, but the shaded area overlaps. The attribute controller gives the horizontal start address h1 and the end address h3-1 of the new display screen to att1 by the attribute conversion circuit, and the horizontal start address x1 and the end address x1 + (h3- 1) Give -h1.
Further, the attributes att1 and att4 converted by the above operation are sequentially sent to the video memory controller and the display buffer controller, and the drawing of one horizontal line is completed. The above operation is repeated from the vertical counter value of v0 to ve, and drawing of all display lines is completed.
One image is composed,

1 does not access the video memory or the display buffer of the attribute with the lower priority in the overlap region indicated by the diagonal lines in the display buffer.
In the above description, for the sake of explanation, the size of the source image and the size of the displayed image are the same, but the description is made.
Even if horizontal and vertical enlargement / reduction is performed and the above two image sizes are different, the required video memory address is calculated from the attribute data display area and video memory address based on the ratio of each size. It is clear that it is possible to do
The present invention is also effective in a video display device having a reduction function. "Effect of Embodiment" According to this embodiment, when an attribute is overlapped, it is actually displayed on a display buffer or a video memory. Since only access to image data is performed, the substantial rendering capability can be greatly improved. Also, compared to conventional video display devices,
Since it is possible to use low-speed memory and lower the bus bandwidth for memory,
System size and cost can be reduced. Furthermore, if you are sharing video memory with other devices,
The occupation time of the bus of the video memory controller is reduced, so that the processing time of other devices can be improved, and the processing capability of the system can be improved. Below "other embodiments"

FIG. 2 ~

Another embodiment will be described with reference to FIG.

FIG. 2 is an operation explanation block diagram 2,

FIG. 3 is an attribute display area

FIG. 4 shows an attribute conversion circuit. Attributes are

FIG. 3 shows

FIG. 1 shows the same settings as those shown in the display buffer.

In the embodiment of FIG. 1, the display buffer has a capacity for one screen. However, in the present embodiment, two display buffers having a capacity for one line are provided. -It is composed of a display buffer A and a display buffer B which serve odd lines. Further, a display transmission controller is connected to the two display buffers, and transmits the data of the line for which the drawing has been completed from the display buffer to the display in accordance with the video synchronization signal. Further, a horizontal counter and a TMP memory are connected to the attribute conversion circuit.

FIG. 4 shows the contents of the attribute conversion circuit. att1
From the start hs and end he of the display of att4, the output hcnt of the horizontal counter, the attribute controller compares the value of the vertical counter with the start and end of the vertical display area of each attribute, and determines whether or not it is inside The resulting vvlds are connected to each other, and there are four horizontal display determination circuits, which are connected to the priority encoder. As for the horizontal display judgment circuit, vvld is valid and hcnt is hs
1 is output when the value is between "1" and "he", and 0 is output otherwise. Since the priority encoder outputs the code of the largest input among the inputs from 0 to 4, the attribute having the highest display priority can be determined at the position of hcnt. If no attribute is at the position of hcnt, the output is 0. Since hcnt counts up for each clock and FF1 and FF2 also hold data for each clock, the output of FF1 and FF2 indicates the attribute number and the value of hcnt one clock before. Therefore, the output wr of exor becomes 1 when the displayed attribute of the horizontal display line changes, and the outputs of FF1 and FF2 at that time were converted by the attribute number before the change and the overlap of the display of the attribute. Indicates the end address. Therefore, if hcnt is counted up from 0 to the horizontal display size, and writing is performed to the TMP memory when wr is 1, the attribute numbers and the end of the display area for all attributes displayed on the line are listed. . The address of the TMP memory required in this configuration is 8 (2 × 4 attributes). The listed data is sequentially passed to the attribute controller, and according to the display area calculated from the attribute number and the end of the display area,

The same operation as in the embodiment of FIG. 1 is performed, and drawing of one horizontal line is completed. In the present embodiment, two display buffers for one line are prepared, and the display buffer controller and the display transmission controller are alternately switched between the odd and even vertical counts for access. Therefore, it is necessary to complete the drawing one line before the vertical line sent to the display.
Passed through a line delay. Also, drawing of one line must be completed within one line of display transmission, but the clock used for the drawing circuit such as the attribute controller must be faster than the dot clock for display transmission. Is easy to implement. Table 1
To

FIG. 1 shows that the value of the vertical counter is v12, v2 as in the embodiment of FIG.
3, the contents of the TMP memory in the case of v34 and v67 are shown, and the operation will be described taking the case of v34 as an example.

[Table 1] Since the horizontal counter is between h0 and h1-1, no attribute is at the display position, so the output of the priority encoder is 0. When the horizontal counter next reaches h1, att1 is the attribute with the highest display priority. Therefore, the output of the priority encoder becomes 1.
At this time, the value held in FF1 is 0 one clock before, so e
The output of xor becomes 1 and the values 0 and h1- held in FF1 and FF2
1 is written to TMP memory. Similarly, the horizontal counter
h2 is 1 and h2-1, h4 + 1 is 2 and h4, h5 is 1 and h5-1 is h7 + 1
Then, 3 and h7 are written to the TMP memory. When the writing to the TMP memory is completed, the attribute controller first reads the attribute number 0 and the end address h1-1, but since the attribute number is 0, the drawing operation is not performed and the end address h1-1 is held. Next, when attribute number 1 and end address h2-1 are read, at
Read the attribute of t1 from the attribute memory, change the display start to h1 which added 1 to h1-1 which was held earlier, and change the end to h2-1

1 performs the same operation as in the embodiment of FIG. This is repeated until the last attribute number 3 and end address h7 written in the TMP memory are read, and the drawing of one horizontal line is completed. The above operation is performed when the value of the vertical counter is v0
Repeat from to ve to complete the drawing of all display lines to form one image,

In the overlapping area shown by the diagonal lines in FIG. 3, no access is made to the video memory or the display buffer of the low priority attribute. In the above description, the number of attributes is four for the sake of explanation, but it is obvious that the number can be increased by preparing the same number of circuits. Attribute conversion and drawing are completed at the same time within the time of one line.However, a TMP memory with the same capacity as the delay of one line is prepared, and attribute conversion is performed two lines before display. Alternatively, the drawing may be completed one line before the display.

As described above, according to the present invention, when the attributes are overlapped, only the access to the display buffer or the video memory relating to the image data actually displayed is performed, so that the substantial effect is obtained. The drawing ability can be greatly improved. Further, compared to the conventional video display device, it is possible to use a memory having a lower operation speed and to reduce the bandwidth of a bus for the memory, so that the system can be reduced in size and cost. Further, when the video memory is shared with other devices, the bus occupation time of the video memory controller can be reduced, so that the processing time of other devices can be improved and the processing capability of the system can be improved. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the operation of an embodiment of the present invention;
It is.

FIG. 2 is a block diagram illustrating the operation of the embodiment of the present invention;
It is.

FIG. 3 is a diagram showing an example of an attribute display area according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of an attribute conversion circuit according to an embodiment of the present invention.

FIG. 5 is an operation explanatory block diagram of an example of a conventional video display device.

[Explanation of symbols]

 1a Video memory 1b Video memory controller 1c Display buffer 1d Display buffer controller 1e Attribute memory 1f Attribute controller 1g Attribute conversion circuit 1h Source address calculation circuit 1i Vertical counter 2a Video memory 2b Video memory controller 2c Display transmission controller 2d Display 2e Display buffer A 2f Display buffer B 2g 1 line delay 2h Vertical counter 2i Attribute memory 2j Display buffer controller 2k Attribute controller 2l Source address calculation circuit 2m Attribute conversion circuit 2n Horizontal counter 2o TMP memory 4a Attribute 1 data 4b Attribute 2 data 4c Attribute 3 data 4d Attribute 4 Data 4e Horizontal display judgment circuit for attribute 1 4f Water for attribute 2 Display judgment circuit 4g Attribute 3 horizontal display judgment circuit 4h Attribute 4 horizontal display judgment circuit 4i End address holding FF 4j Attribute number holding FF 4k Attribute number change judgment exor 4l Priority encoder 6a Attribute memory 6b Display buffer 6c Video memory 6d drawing circuit

Claims (5)

[Claims] 1. A video memory for storing source image data, a video memory controller capable of reading data from an arbitrary address of the video memory,
A display buffer for temporarily storing data read by the video memory controller; a display buffer controller for managing the display buffer; and attributes such as an address of a source image data stored in the video memory and a display area on a screen. The attribute memory for storing data, the attribute controller for reading the attribute data from the attribute memory, and the display area of the attribute data on one predetermined horizontal line of the display screen overlap, and the pixels of the attribute with low display priority disappear. If the display area on the screen changes due to the disappeared pixels,
An attribute conversion circuit for converting the changed display area into a new display area and, when divided, converting the attribute data into the number of attributes divided by the divided display area as a new display area; A source address calculation circuit for calculating an address of a video memory in which the corresponding source image data exists from the new display area converted by the conversion circuit, wherein the attribute controller reads the attribute data from the attribute memory. Read, and sends the address of the video memory calculated by the source address calculation circuit from the attribute data corresponding to one predetermined horizontal line to the video memory controller, and sends the address to the attribute conversion circuit. Sends the converted address corresponding to the display area of the display buffer to the display buffer controller, the video memory controller reads necessary source image data from the video memory address received from the attribute controller, The display buffer controller sends the data to the display buffer controller and stores the data received from the video memory controller at the address of the display buffer received from the attribute controller for each horizontal display line. . 2. The video display device according to claim 1, wherein:
2. A display sending controller for sending the contents of a display buffer to a display in accordance with a display synchronization signal, wherein the operation of repeating each horizontal display line according to claim 1 is shorter than the horizontal synchronization time of display and the display sending controller. Is completed before the timing of transmission of the corresponding line. 3. The video display device according to claim 1, wherein the attribute data divided by the attribute conversion circuit is only a display area. 4. A video display according to claim 1, wherein:
Horizontal counter for counting the horizontal display position and TM for temporarily storing data output by the attribute conversion circuit
A priority circuit for calculating the attribute number of the highest display priority at the display position from the horizontal display area of the attribute corresponding to one predetermined horizontal line and the value of the horizontal counter; Each time the horizontal counter increments by one from 0 to the horizontal size of the display, the attribute circuit calculates a position at which the attribute number changes from the attribute number calculated by the priority circuit and a change point output circuit that outputs the position. The attribute conversion circuit realizes attribute conversion by storing the output of the change point output circuit in the TMP memory and referring to the contents of the TMP memory. 5. The video display according to claim 4, wherein the TMP
The memory has a capacity capable of storing data corresponding to an attribute number or data indicating that an attribute does not exist and an end address of the area by twice the number of attributes.