JP3499780B2 - Video display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device.

[0002]

2. Description of the Related Art A conventional video display device repeatedly writes all the source image data indicated by one attribute in the display area of a display buffer, in order from the attribute with the lowest display priority, to all the attributes. Then, the entire image to be displayed was constructed.
Hereinafter, the details will be described with reference to FIG. 6a is an attribute memory for storing attributes, 6b is a display buffer for temporarily storing images to be displayed, 6c is a video memory for storing source image data, and 6d is a drawing circuit.

[0003] The attribute memory from att1 att4
Up to four attributes are stored, and addresses indicating the areas of the video memory and the display buffer are shown. The drawing circuit first reads the attributes of att1 and reads the att1 area of the video memory from the att of the display buffer.
The image data is written in the area of t1. Next, the attribute of att2 is read and the same processing is performed, but at this time, the data of att2 is overwritten in the shaded area of the display buffer, and att1
Image data of will be lost. The drawing circuit is att3
The processing up to att4 is performed to form the entire image, but similarly, the image data in the shaded area is overwritten. As described above, the drawing circuit sets the attribute memory to att1 ~
Since the reading is performed in the order of att4, the display priority is at
Higher in the order of t1 to att4.

[0004]

However, according to the above-mentioned conventional technique, the image data which is overwritten by the attribute having the high display priority and which is not displayed is read from the video memory to the display buffer as shown by the hatched portion in FIG. Since it was writing, it was supposed to make unnecessary access to the video memory and display buffer. Therefore, it is an object of the present invention to provide a video display device that does not wastefully access a video memory or a display buffer for image data that is overwritten by an attribute having a high display priority and is not displayed.

[0005]

In order to solve the above problems, a video memory for storing source image data,
A video memory controller capable of reading data from an arbitrary address of the video memory, a display buffer for temporarily storing the data read by the video memory controller, a display buffer controller managing the display buffer, Attribute memory that stores the attribute data such as the address of the source image data stored in the video memory and the display area on the screen, an attribute controller that reads the attribute data from the attribute memory, and a predetermined horizontal line on the display screen If the display areas of the attribute data of are overlapped and the pixels of the attribute with a low display priority disappear, and the display area on the screen changes due to the lost pixels, the changed display area is newly updated. And a display region, if that will be split, and attribute conversion circuit for converting the display region divided its attribute data to the divided number of attributes to a new display area, newly converted by the attribute conversion circuit In a video display device including a source address calculation circuit that calculates an address of a video memory in which the corresponding source image data exists from a different display area, the attribute controller reads the attribute data from the attribute memory and sets a predetermined horizontal 1 The address of the video memory calculated by the source address calculation circuit from the attribute data corresponding to the line is sent to the video memory controller, and the display converted by the attribute conversion circuit Sends the address corresponding to the display area of Ffa to the display buffer controller, the video memory controller reads the source image data required from the address of the video memory received from the attribute controller,
The display buffer controller sends the data to the display buffer controller, and the display buffer controller stores the data received from the video memory controller in the address of the display buffer received from the attribute controller repeatedly for each horizontal display line.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION One embodiment of the present invention is shown in FIG . FIG. 1 is an operation explanation block diagram 1. Figure 1 below
The details of the operation will be described using. The attribute is composed of four, and the display area of the attribute memory is shown in Fig. 1.
The settings are as shown in the display buffer of. The vertical counter counts the vertical pointer on the display screen. It is a sequence from v0 to ve.
An image of one side is constructed. The image data is written to the display buffer for each horizontal line of the pointer indicated by the vertical counter, and when the corresponding attribute exists, the necessary data is read from the video memory and written to the display buffer.

The attribute controller compares the value of the vertical counter with the start / end of the vertical display area of each attribute to determine whether or not it is contained therein, thereby determining whether each attribute corresponds to the current horizontal pointer. Since it is possible to know whether or not the value of the vertical counter is v0 to less than v1, there is no corresponding attribute, if v1 to less than v2, only att2, if v2 to less than v3, att2 and att3 Can be read and a write operation to the display buffer can be performed as necessary.

[0008] The value of the vertical counter exists between v1 and v2
If the value is v12, the attribute controller reads the attribute of att2 and adds the vertical start address y2 of the source image plus the value of v12 minus v1 to obtain the vertical and horizontal start address x1 of the video memory. , End address x3 is sent to the video memory controller and the vertical pointer v12 and horizontal start address h2 and end address h4 of the display screen are sent.
To the display buffer controller. The display buffer controller receives the data received from the video memory controller from the horizontal address h2 to h4 of the vertical address v12.
The lights are sequentially written to and the drawing of one horizontal line is completed.

[0009] The value of the vertical counter exists between v2 and v3
When the value is v23, the corresponding attributes are att2 and att3, so the same operation as above is performed.
done about att3. If the value of the vertical counter is v34, which exists between v3 and v4, the corresponding attributes are att1, att2, and att3, but the shaded areas overlap. The attribute controller uses the attribute conversion circuit to convert att1 to att1: 1 and att1
Divide into 1: 2 and start h1 and end in att1: 1 as horizontal start address and end address of new display screen.
Start h4 + 1 and end h5-1 are given to h2-1 and att1: 2, and at the same time, the horizontal start address and end address of the new source image are specified by the source address calculation circuit.
Start x1 and end x1 + (h2-1) -h1 are given to 1: 1 and start x1 + (h4 + 1) -h1 and end x1 + (h5-1) -h1 are given to att1: 2.
In addition, att1: 1 and att1: 2 converted by the above operation
Horizontally sends att2 and att3 attributes to the video memory controller and display buffer controller in sequence.
Finish drawing the line.

[0010] The value of the vertical counter exists between v6 and v7
When the value is v67, the corresponding attributes are att1 and att4, but the shaded areas overlap. The attribute controller gives the new horizontal start address h1 and end address h3-1 of the display screen to att1 by the attribute conversion circuit, and the horizontal start address x1 and end address x1 + (h3- 1) -give h1. Further, the attributes of att1 and att4 converted by the above operation are sequentially sent to the video memory controller and the display buffer controller to complete the drawing of one horizontal line.

The above operation is performed by changing the value of the vertical counter from v0 to ve.
Repeat the above until all the display lines have been drawn to form a one-sided image, but with regard to the overlapping area indicated by the diagonal lines in the display buffer in Fig. 1 , access to the video memory or display buffer of the attribute with lower priority Is not done. In the above description, the size of the source image and the size of the displayed image are the same for the sake of description. However, when horizontal / vertical enlargement / reduction is performed and the two image sizes are different. But
It is clear that it is possible to calculate the required video memory address from the attribute data display area and video memory address based on the ratio of each size. The present invention is also effective for a video display device that has

According to the "Effects of the Embodiment" This embodiment, if the attribute is overlapped, since only done accessing an image data that is actually displayed to the display buffer, video memory, substantial drawing The ability can be greatly improved. Further, as compared with the conventional video display device, it is possible to use a memory having a low operation speed and to reduce the bandwidth of the bus to the memory, so that the system can be downsized and the cost can be reduced. Furthermore, when the video memory is shared with other devices, the time occupied by the bus of the video memory controller is reduced, and it is possible to improve the processing time of other devices and improve the processing capacity of the system. Becomes

[0013] another embodiment will be described with reference to FIGS below "another embodiment". 2 is a block diagram for explaining the operation, FIG. 3 is an attribute display area, and FIG. 4 is an attribute conversion circuit. Attribute has the same settings as those shown in the display buffer as Figure 1 shown in FIG. In the embodiment shown in FIG. 1 , the display buffer has a capacity for one screen, but in the present embodiment, there are two display buffers having a capacity for one line. It is composed of a display buffer A and a display buffer B which are in charge of lines. A display transmission controller is connected to the two display buffers, and the data of the line for which drawing has been completed is transmitted from the display buffer to the display according to the video synchronization signal. Further, a horizontal counter and TMP memory are connected to the attribute conversion circuit.

FIG . 4 shows the contents of the attribute conversion circuit. The display start hs and end he of att1 to att4, the output hcnt of the horizontal counter, the attribute controller compares the value of the vertical counter with the vertical display area start and end of each attribute to determine whether they are inside As a result, vvld and 4 are connected respectively.
There are two horizontal display decision circuits connected to the priority encoder. Vvld is effective for the horizontal display judgment circuit
If hcnt is between hs and he, 1 is output, otherwise 0 is output. Since the priority encoder outputs the code of the largest input among the inputs of 0 to 4, the attribute having the highest display priority can be discriminated at the position of hcnt.

[0015] It should be noted that, if any attribute is also not in the position of hcnt, output is zero. Since hcnt counts up for each clock and FF1 and FF2 also hold data for each clock, the outputs of FF1 and FF2 show the attribute number one clock before and the value of hcnt. Therefore, the output wr of exor becomes 1 when the displayed attribute of the horizontal display line changes, and the outputs of FF1 and FF2 at that time are converted by the attribute number before the change and the display of that attribute. It indicates the end address. Therefore, if you count up hcnt from 0 to the horizontal display size and write to TMP memory when wr is 1, the attribute numbers for all attributes displayed on that line and the end of the display area are listed. . The TMP memory address required in this configuration is 8 (2 × 4 attributes).

The listed data is sequentially passed to the attribute controller, and the same operation as that of the embodiment of FIG. 1 is performed according to the display area calculated from the attribute number and the end of the display area, and the drawing of one horizontal line is completed. In this embodiment, there are two display buffers for one line.
One is prepared, and the display buffer controller and the display transmission controller are alternately switched by the odd / even of the vertical count to access. Therefore, since it is necessary to complete drawing one line before the vertical line sent to the display, the value of the vertical counter is passed to the display sending controller via the one-line delay. Also, it is necessary to complete the drawing of one line within the time for one line of display transmission, but the clock used for the drawing circuit such as the attribute controller should be faster than the dot clock for display transmission. Since it is possible, it is easy to realize.

[0017] Table 1 is the value of the embodiment as well as vertical counter of Figure 1 shows the v12, v23, v34, TMP content of the memory in the case of V67, describing the operation as an example a case where v34.

[Table 1] The output of the priority encoder is 0 because no attribute is in the display position between the horizontal counter h0 and h1-1. At the next horizontal counter h1, att1 is the attribute with the highest display priority. Therefore, the output of the priority encoder becomes 1.
At this time, the value held in FF1 is 0 one clock before, so e
The output of xor becomes 1, and the value 0 and h1- held in FF1 and FF2
1 is written to TMP memory. Similarly, the horizontal counter
h2 is 1 and h2-1, h4 + 1 is 2 and h4, h5 is 1 and h5-1 is h7 + 1
Then 3 and h7 are written to TMP memory.

When the writing to the TMP memory is completed, the attribute controller first reads the attribute number 0 and the end address h1-1, but since the attribute number is 0, the drawing operation is not performed and the end address h1-1 is held. Next, when the attribute number 1 and the end address h2-1 are read, the attribute of att1 is read from the attribute memory, and the start of the display is added to h1-1 obtained by adding 1 to h1-1 and the end is set to h2-1. Instead of this, the same operation as in the embodiment of FIG. 1 is performed. This is repeated until the last attribute number 3 written in the TMP memory and the end address h7 are read, and the drawing of one horizontal line is completed.

The above operation is performed by changing the value of the vertical counter from v0 to ve.
By repeating the above until all the display lines are drawn, the image on one side is constructed. However, regarding the overlapping area indicated by the diagonal lines in Fig . 3 , the video memory and the display buffer of the attribute with low priority are not accessed. . In the above description, the number of attributes is four for the sake of explanation, but it is clear that the number can be increased by preparing the same number of circuits. In addition, the attribute conversion and drawing are completed at the same time within the time for one line, but a TMP memory of the same capacity as the delay for one line is prepared, and the attribute conversion is performed two lines before the display. , Drawing may be completed one line before display.

[0020]

As described above, according to the present invention, when the attributes are overlapped with each other, only the image data to be actually displayed is accessed to the display buffer and the video memory. The drawing ability can be greatly improved. Further, as compared with the conventional video display device, it is possible to use a memory having a low operation speed and to reduce the bandwidth of the bus to the memory, so that the system can be downsized and the cost can be reduced. Furthermore, if the video memory is shared with other devices, the bus occupied time of the video memory controller can be kept low, so the processing time of other devices should be improved and the processing capacity of the system should be improved. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the operation of an embodiment of the present invention.
Is.

FIG. 2 is a block diagram for explaining the operation of the embodiment of the present invention.
Is.

FIG. 3 is a diagram showing an example of an attribute display area according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of an attribute conversion circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating the operation of an example of a conventional video display device.

[Explanation of symbols]

1a video memory 1b video memory controller 1c display buffer 1d display buffer controller 1e attribute memory 1f attribute controller 1g attribute conversion circuit 1h Source address calculation circuit 1i vertical counter 2a video memory 2b video memory controller 2c Display sending controller 2d display 2e Display buffer A 2f Display buffer B 2g 1 line delay 2h vertical counter 2i attribute memory 2j display buffer controller 2k attribute controller 2l Source address calculation circuit 2m attribute conversion circuit 2n horizontal counter 2o TMP memory 4a Attribute 1 data 4b Attribute 2 data 4c attribute 3 data 4d attribute 4 data 4e Horizontal display judgment circuit for attribute 1 Horizontal display judgment circuit for 4f attribute 2 Horizontal display judgment circuit for 4g attribute 3 4h Horizontal display judgment circuit for attribute 4 4i End address holding FF FF for holding 4j attribute number 4k exor for judging attribute number change 4l priority encoder 6a Attribute memory 6b display buffer 6c video memory 6d drawing circuit

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 5/377 G09G 5/14

Claims (3)

(57) [Claims] 1. A video memory for storing source image data, and a video memory controller capable of reading data from an arbitrary address of the video memory.
A display buffer for temporarily storing the data read by the video memory controller, a display buffer controller for managing the display buffer, and an attribute such as an address of the source image data stored in the video memory or a display area on the screen. Attribute memory that stores data, attribute controller that reads the attribute data from the attribute memory, and the display area of the attribute data on a predetermined horizontal 1 line of the display screen overlap, and the source image data with a low display priority of the overlap area When the display area of changes
If the change to the display area as a new display area, if it is split, the attributes conversion for converting the divided number of attributes data and the divided display area of the source image data as a new display area A video display device including a circuit and a source address calculation circuit that calculates an address of a video memory in which the corresponding source image data is present from the new display area converted by the attribute conversion circuit, wherein the attribute controller includes the attribute The attribute data is read from the memory, the address of the video memory calculated by the source address calculation circuit from the attribute data corresponding to a predetermined horizontal 1 line is sent to the video memory controller, and the attribute conversion is performed. An address corresponding to the display area of the display buffer converted by a circuit is sent to the display buffer controller, the video memory controller reads necessary source image data from the address of the video memory received from the attribute controller, the display sent to the buffer controller, the display buffer controller is configured to repeat that stores data received from the video memory controller to the address of the display buffer received from the attribute controller for each horizontal display lines, horizontal Horizontal counter and attribi that count the display position of
TM for temporarily accumulating the data output by the automatic conversion circuit
Equipped with P memory, the attribute conversion circuit
Horizontal display area of attributes corresponding to one horizontal line
From the value of the above horizontal counter,
Also calculates the attribute number with the highest display priority.
The priority circuit and the horizontal counter display from 0
Each time you increment the horizontal size by 1
From the attribute number calculated by the priority circuit,
Output the position where the tribute number changed and its number
Change point output circuit and the above attribute conversion
The circuit outputs the output of the change point output circuit to the TMP memory.
After storing , refer to the contents of the TMP memory above .
A feature that realizes attribute conversion.
Deo display device . 2. A display transmission controller for transmitting the contents of a display buffer to a display device according to a display synchronization signal,
The operation of repeating each horizontal display line according to claim 1 is completed in a time shorter than the horizontal synchronization time of display and before the timing at which the display transmission controller transmits the corresponding line. Item 1
Deo display device . That wherein TMP memory having a capacity capable of storing data in pairs and data indicating that the attribute number or attribute is not present and the end address of the area by twice attributes number
The video display device according to claim 2, wherein the video display device is a video display device .