JP2001092416A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly erase the after-image of the final display picture which is generated after the power source of a display device is turned off by adding simple circuits to the device. SOLUTION: This device is provided with active switching elements 11 arranged in a matrix shape, gate lines 15 to which these active switching elements 11 are connected and which supply an ON voltage for turning these elements ON and after-image erasing circuits 16 connected to these gate lines 15. Then, this after-image erasing circuit 16 is provided with a storage capacitance 16c and a pair of transistors which are connected to the storage capacitance 16c and whose ON/OFF states are invertedly controlled to directions reverse with each other in accordance with the presenece or absence of the ON voltage to be supplied to the gate line 15 and whose polarities are different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device capable of quickly erasing an afterimage on a final display screen after power is turned off, and is particularly suitable for use in a liquid crystal display device.

[0002]

2. Description of the Related Art Conventional active matrix type TFT
In the case of stopping the use of the device displayed on the display screen in the liquid crystal display device, usually, the operation of clearing the final display screen is not actively performed, and only the power switch of the display device body is turned off. Met. In this case, the afterimage of the last screen immediately before the power is turned off remains for a relatively long time after the power is turned off. During this period, the DC voltage is still applied to the liquid crystal itself, so that the deterioration of the liquid crystal is accelerated and the life is shortened. There is a problem that the reliability is impaired. As a prior art for solving this problem, Japanese Patent Laid-Open No. 10-3336 is disclosed.
No. 42 is disclosed. In this method, afterimages generated when the power is turned off are erased with a low-cost circuit configuration without providing a special power supply.

The prior art will be described below with reference to FIG. In FIG. 5, reference numeral 51 denotes an active switch element;
1a is an FET, 51b is a pixel electrode, 52 is a gate line, 5
3 is a gate line drive circuit, 54 is a voltage generation circuit, 55 is an afterimage removal circuit, 56 is a charge storage circuit, 57 is a P-channel transistor, 58 is a voltage supply circuit, 59 is a voltage drop circuit, and 60 is a P-channel transistor. . When the power supply voltage Vdd is supplied to the liquid crystal display device, the node A is supplied with the gate low voltage Vgl, and the gate line driving circuit 53 outputs the power supply voltage Vdd, the gate high voltage Vgh, and the potential of the node A. It operates under a power supply voltage of a certain gate low voltage Vgl. The afterimage removal circuit 55 includes a charge storage circuit 56, a P-channel transistor 57, and a voltage supply circuit 5.
8 and a voltage drop circuit 59.

The capacitance C1 of the charge storage circuit 56 is charged by the diode D1 to near the power supply voltage Vdd. The P-channel transistor 57 is kept OFF because the P-channel transistor 60 is ON.

[0005] In this configuration, an operation when power is not supplied to the liquid crystal display device will be described. In this case, the power supply voltage Vdd instantaneously changes to zero. Therefore, not only the power supply voltage Vdd but also Vgh and Vgl instantaneously change to zero. As a result, although the potential of the power supply voltage terminal Vdd in the charge storage circuit 56 becomes zero, the charge stored in the capacitance C1 is on the power supply voltage terminal Vdd side (the potential has changed to zero because of the diode D1). ) No discharge or leakage. Voltage supply means 58
Although the middle power supply voltage terminal Vdd also becomes zero, the potential of the node C in a floating state is higher, so that the potential of the node C is not reduced by the P-channel transistor 60. Further, since the potential of the gate high voltage terminal Vgh in the voltage dropping circuit 59 instantaneously becomes zero, the potential of the node C drops at a stretch due to the capacitive coupling of the capacitances C2 and C3, turning on the P-channel transistor 57.

As a result, the electric charge stored in the capacitance C 1 causes the potential of the node A to rise, and the voltage is supplied to the gate line driving circuit 53. as a result,
The potential of the plurality of gate lines 52 that are not selected by the gate line driving circuit 53 increases (for example, about +2 V),
The FET 51a in the active switch element 51 turns on. Thereby, the electric charge accumulated in the element 51 becomes
For example, afterimages after power-off can be erased earlier than in the case where the source lines are forcibly discharged and spontaneous discharge occurs.

[0007]

However, in the above-described configuration, the P-channel transistors 57 for driving the gate lines after the power is turned off are all non-selected FETs 51a.
It is necessary to drive the gate and the load of the gate line 52,
The transistor width and transistor length also need to be set large. The capacitance C2 of the voltage drop means for driving the gate of the P-channel transistor 57,
C3 has a large capacity, and a P-channel transistor 60
Also, both the transistor width and the transistor length need to be set large. As a result, there is a problem that the area of the afterimage removing circuit portion increases, which leads to an increase in cost.

As another problem, in the method according to the prior art, in order to supply a potential higher than Vgl to the unselected gate lines after the power is turned off, the operating power supply of the gate line driving circuit is turned off for a certain period after the power is turned off. It has to be held, and a holding circuit for that purpose needs to be provided in the voltage generation circuit 54 or the gate line drive circuit 53, which increases the circuit scale and complexity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. By adding a very simple circuit to a gate line, the potential of the gate line after power-off is increased, and the power of the display device is turned off. It is an object of the present invention to quickly eliminate the afterimage by discharging electric charges accumulated in each pixel.

[0010]

According to the present invention, there is provided an image display apparatus, comprising: an active switch element arranged in a matrix; and a gate to which the active switch element is connected and which supplies an on-voltage for turning on the element. Line, and an afterimage removal circuit connected to the gate line,
The after-image elimination circuit is connected to the storage capacitor and connected to the storage capacitor, and the on / off states are controlled to be reversed in opposite directions depending on the presence or absence of the on-voltage supplied to the gate line. And a pair of transistors.

Further, the pair of transistors is constituted by an N-channel transistor and a P-channel transistor.

Further, the source or the drain of the P-channel transistor is connected to the gate line.

Further, the storage capacitor and the pair of transistors are formed on an insulating substrate on which the active switch elements are formed in a matrix.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a conceptual diagram of the display device according to the first embodiment of the present invention, and FIG. 2 is a time chart of a control signal and a power supply voltage when the power supply is turned off.

FIG. 1 is a diagram for explaining details of a driving circuit for a gate line in a liquid crystal display device, in particular, 11 is an active switch element, 15 is a gate line, 16 is an afterimage removing circuit, 17 is a source line, and 18 is a gate. Line drive circuit,
19 is a voltage generation circuit. The gate line high voltage Vgh and the gate line low voltage Vgl supplied to the gate line 15 are generated by the voltage generation circuit 19 to which the power supply voltage Vdd is input, and are input to the gate line drive circuit 18. Gate line drive circuit 1
8, the configuration is such that Vgh is supplied to the select gate line and Vgl is supplied to the non-select gate line. An afterimage removing circuit 16 is a P-channel transistor 16a
And an N-channel transistor 16b and a storage capacitor 16c. Each gate line 1 of the gate line driving circuit 18
The P-channel transistor 16a having a source and a bulk (back gate) connected to one end of the storage capacitor 16c, a gate connected to the high voltage Vgh, and a drain connected to each gate line 15 is connected to the output stage No. 5. I have. Here, the source and the drain are usually symmetrical,
The source and the drain may be exchanged.

The other end of the storage capacitor 16c is connected to the ground potential. Further, one end of the storage capacitor 16c is connected to the source of the N-channel transistor 16b, and the gate and the drain of the N-channel transistor 16b are connected to the high voltage V.
gh, and the bulk (back gate) is connected to the ground potential. Each gate line 15 is connected to a gate of each active switch element 11 formed in a matrix on an insulating substrate via an afterimage removing circuit 16. The source of the active matrix element is connected to each source line 17, and a liquid crystal capacitor 1 is connected between the drain and the common electrode 11d.
1b and the storage capacitor 11c are connected in parallel.

FIG. 2 is a time chart of the control signals and the power supply voltage of the liquid crystal display device when the power supply is turned off. As shown in FIG. , The gate line high voltage Vgh generated from the power supply voltage also becomes substantially the ground (zero) level.

At this time, during the normal operation (power-on) in the configuration of FIG. 1, the N-channel transistor 16b is turned on by the high voltage Vgh connected to the gate and drain of the N-channel transistor 16b, so that the storage capacitance is set. An electric charge is accumulated in 16c. At this time, the P-channel transistor 16a is cut off because the high voltage Vgh is connected to the gate, and the charge stored in the storage capacitor 16c does not flow out to the gate line 15.

When the power is turned off, as shown in FIG. 2, the gate line high voltage Vgh also goes to the ground level at the same time as the power is turned off. Therefore, the gate of the P-channel transistor 16a goes to the ground level and turns on. The charge stored in the storage capacitor 16c is supplied to the gate line 15 via the P-channel transistor 16a. At this time, N
Since the gate of the channel transistor 16b is at the ground level, the channel transistor 16b is cut off with the disappearance of Vgh, and the charge of the storage capacitor 16c is transferred to the gate line high voltage Vgh (ground level after the power is turned off) via the N-channel transistor 16b. Do not spill.

With the above-described configuration, the electric charge stored in the storage capacitor 16c is supplied to each gate line 15 after the power is turned off, the potential of each gate line is raised, and each active switch element 11 has a low resistance. In this state, the charge remaining in the drain of each active switch element 11 is discharged to the source line 17 and the like, and the afterimage of the display image after the power is turned off can be quickly erased.

Embodiment 2 A second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a conceptual diagram of a display device according to the second embodiment of the present invention, and FIG. 4 is a layout diagram of the second embodiment of the present invention. FIG. 3 shows only the afterimage removing circuit of FIG. 1 according to the first embodiment, and the other configuration is the same as that of the first embodiment, so that the description is omitted.

The present embodiment is characterized in that the afterimage removing circuit is formed on an insulating substrate on which active switch elements are formed in a matrix. Bulk (back gate) when forming an afterimage removing circuit 31 on an insulating substrate
Is unnecessary, the P-channel transistor 31a and the N-channel transistor 31b as shown in FIG.
Is a three-terminal (gate, source, drain) representation.

FIG. 4 shows an example of a layout diagram of the afterimage removing circuit 31 in FIG. 3 on an insulating substrate. FIG.
As shown in (2), the output (gate line) 41 from the gate line drive circuit is partially transferred to the source / drain metal 42 by the contact hole 43, and crosses over the gate line high voltage Vgh (gate metal) 47. An input is made to the gate of an active switch element formed in a matrix with a gate metal. The P-type semiconductor layer 44 and the N-type semiconductor layer 4 are formed on the gate line high voltage Vgh (gate metal) 47.
5, a P-channel transistor 31a having a drain connected to the gate line, a source connected to one end of the storage capacitor 31c, and a gate connected to the gate line high voltage Vgh.
An N-channel transistor 31b whose drain and gate are connected to the gate line high voltage Vgh and whose source is connected to one end of the storage capacitor 31c is formed.

Further, the ground potential 49 formed of the source / drain metal is transferred to the gate metal through the contact hole 43, passes under the gate line high voltage Vgh (source / drain metal) 48, and passes through one end of the storage capacitor 31c ( (Storage / source / drain metal). The operation at the time of turning on and off the power is the same as that of the first embodiment. With the above configuration, the same effect as that of the first embodiment can be obtained. As a further effect, the afterimage removing circuit 31 is insulated. By forming the gate line voltage on the conductive substrate, it is possible to increase the gate line voltage after the power is turned off closer to the display area, and the drive load capacity is reduced, so that the gate line potential can be reliably increased. Become.

According to this circuit configuration, the storage capacitance 3
Since 1c is provided for each gate line, it can be dispersed in a small capacity, which is advantageous for patterning. P-channel transistor 31a, N-channel transistor 3
In the case of 1b as well, it is only necessary to drive the distributed small loads, so that the transistor size can be reduced, which is advantageous for patterning.

Although the present invention has been described based on the first and second embodiments, the present invention is not limited to the first and second embodiments, and does not depart from the gist of the present invention. It goes without saying that various changes can be made in the range.

For example, in the first and second embodiments, the image elimination circuit after the power of the liquid crystal display device is turned off is described. However, the present invention is not limited to a display device using liquid crystal, but may be an electronic device. The present invention is applicable to any active matrix type display device using a luminescence element or the like.

In the first and second embodiments,
Although an example in which an afterimage removing circuit is connected to each gate line is shown, it is not always necessary to connect an afterimage removing circuit to each of all the gate lines. 1 may not be provided with one gate line and the afterimage removal circuit.

Further, a display in which an insulating film, a metal pattern, a semiconductor layer, and the like are formed on an insulating substrate without being limited to the layer configuration on the insulating substrate shown in FIG. 4 of the second embodiment. The present invention is applicable to all cases where the afterimage removal circuit is configured.

[0030]

The image display apparatus according to the first aspect of the present invention comprises an image elimination circuit connected to a gate line, a storage capacitor, and presence or absence of an ON voltage connected to the storage capacitor and supplied to the gate line. And a pair of transistors having different polarities whose on / off states are controlled to be reversed in opposite directions according to the above, and the gate line potential after the power is turned off is increased. By setting the resistance to a low resistance state, the electric charge accumulated in the drain of the active switch element is discharged to the source line or the like, and the afterimage of the display image after the power is turned off can be quickly erased.

According to a second aspect of the present invention, the pair of transistors comprises an N-channel transistor and a P-channel transistor, and a source or a drain of the P-channel transistor is connected to a gate line. With this configuration, the charge accumulated in the drain of the active switch element can be discharged to the source line or the like and the afterimage of the display image after the power is turned off can be quickly erased with a very simple configuration.

An image display device according to a fourth aspect of the present invention is configured such that the storage capacitor and the pair of transistors are formed on an insulating substrate on which active switch elements are formed in a matrix. As a result, the gate line voltage after the power is turned off can be increased closer to the display area, the driving load is reduced, and the charge remaining in the drain of the active switch element is reliably discharged to the source line and the like. As a result, the afterimage of the display image after the power is turned off can be quickly erased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a time chart of a control signal and a power supply voltage when the power supply of the liquid crystal display device is turned off in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a pattern layout diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional liquid crystal display device.

[Explanation of symbols]

11, 51 Active switch element 11b, 51b Liquid crystal capacitance 13, 16c, 31c Storage capacitance 11d Common electrode 15, 52 Gate line 16, 31, 55 Afterimage removal circuit 16a, 31a, 57, 60 P-channel transistor 16b, 31b N-channel transistor 17 Source line 18, 53 Gate line drive circuit 19, 54 Voltage generation circuit 41 Gate line (gate metal) 42 Gate line (source / drain metal) 43 Contact hole 44 P-type semiconductor layer 45 N-type semiconductor layer 11c, 46 Storage capacitance Part 47 Gate high voltage line (gate metal) 47, 48 Gate high voltage line (source / drain metal) 49 Ground potential line (source / drain metal) 11a, 51a FET 56 Charge storage circuit 58 Voltage supply circuit 59 Voltage drop circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA80 NC21 NC34 NC35 ND60 5C006 AA01 AA22 AC02 AF33 AF67 AF78 BB16 BC02 BC03 BC06 BF34 BF37 BF50 FA34 FA38 FA43 FA51 5C080 AA10 BB05 DD18 DD22 DD27 DD30 EE32 KK03 JJ03 JJ03 JJ03 JJ03 JJ03 JJ03

Claims (4)

[Claims] 1. An active switch element arranged in a matrix, a gate line connected to the active switch element and supplying an ON voltage for turning on the element, and an afterimage removing circuit connected to the gate line Wherein the afterimage removing circuit is connected to the storage capacitor, and the on / off state is controlled to reverse in the opposite direction depending on the presence or absence of the on-voltage supplied to the gate line. An image display device comprising a pair of transistors having different polarities. 2. The image display device according to claim 1, wherein said pair of transistors comprises an N-channel transistor and a P-channel transistor. 3. The image display device according to claim 2, wherein a source or a drain of said P-channel transistor is connected to said gate line. 4. The image display device according to claim 1, wherein the storage capacitor and the pair of transistors are formed on an insulating substrate on which the active switch elements are formed in a matrix.