JP2001085408A - Method and device for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology that can reduce the manufacturing cost of a semiconductor integrated circuit device. SOLUTION: In a method for manufacturing semiconductor integrated circuit device, a W film formed on a wafer SW is etched by heating the wafer SW to about 100-250 deg.C by using all or part of infrared lamps 20, a temperature- adjusting liquid, a heating gas 18a, and a Peltier element 19. Then, a polycrystalline silicon film formed on the wafer SW is etched continuously by cooling the wafer SW to about -30 to 80 deg.C by using all or part of the temperature-adjusting liquid 15, a cooling gas 18b, and the Peltier element 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a process for processing a laminated film composed of a metal film and a polycrystalline silicon film deposited on a semiconductor wafer by a dry etching technology. The present invention relates to a technique which is effective when applied to a method for manufacturing a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art MISFET (Metal Insulator Semico)
nductor Field Effect Transistor)
In order to reduce the resistance, for example, a polymetal structure including a tungsten film and a polycrystalline silicon film is used.

Using a patterned resist film as a mask, first, a tungsten film is etched at a relatively high temperature of about 100 ° C., and then a polycrystalline silicon film is etched at a relatively low temperature of about 0 ° C. By
A fine gate electrode having a laminated structure composed of a tungsten film and a polycrystalline silicon film is formed.

[0004]

However, the above-mentioned method of etching a laminated film composed of a tungsten film and a polycrystalline silicon film requires two processing chambers for a high temperature and a low temperature. There is a problem that the number of foreign particles increases and the number of foreign particles increases because floating foreign particles adhere to the semiconductor wafer.

An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) In the method of manufacturing a semiconductor integrated circuit device of the present invention, when processing a laminated film composed of a first film and a second film deposited on a semiconductor wafer,
After heating to about 50 ° C. to etch the first film, the semiconductor wafer is continuously processed in the same processing chamber at −30 to −30.
The second film is etched by cooling to about 80 ° C.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a semiconductor integrated circuit device according to the above (1), the semiconductor wafers are each heated by an infrared lamp and a processing chamber. A heating gas introduced into the inside of the processing chamber, inside the member of the processing chamber wall, a temperature control liquid flowing outside the processing chamber wall or on the wafer stage, and inside the member of the processing chamber wall, An air-cooling fan heated by at least one of a heating method outside the wall, inside the processing chamber, or a Peltier element installed on the wafer stage, and a cooling gas introduced into the processing chamber. And inside the member of the wall of the processing chamber,
A temperature control liquid flowing outside the processing chamber wall or on the wafer stage, and a Peltier element installed inside the processing chamber wall, outside the processing chamber wall, inside the processing chamber or on the wafer stage. Is cooled by at least one cooling method.

(3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a semiconductor integrated circuit device described in (2), a fin is provided on a pipe through which the temperature-adjusted liquid flows or the Peltier element. Things.

(4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a semiconductor integrated circuit device described in (1), the first film is made of a tungsten film, a molybdenum film, a tungsten silicide film or a molybdenum film. A silicide film, and the second film is a polycrystalline silicon film.

(5) The semiconductor integrated circuit device manufacturing apparatus of the present invention has a function of heating a semiconductor wafer to about 100 to 250 ° C. and a function of cooling the semiconductor wafer to about −30 to 80 ° C. It has a processing chamber.

(6) The apparatus for manufacturing a semiconductor integrated circuit device according to the present invention is the apparatus for manufacturing a semiconductor integrated circuit device according to (5), wherein:
A heating gas introduced into the inside of the processing chamber, a temperature adjustment liquid flowing inside the member of the wall of the processing chamber, outside the wall of the processing chamber or on the wafer stage, and inside the member of the wall of the processing chamber; An air-cooling fan having at least one heating function out of the wall of the processing chamber, the inside of the processing chamber, or a Peltier element installed on the wafer stage, each being a cooling method, and introduced into the processing chamber. Cooling gas, inside the member of the processing chamber wall, outside the processing chamber wall or the temperature control liquid flowing to the wafer stage, and inside the processing chamber wall member, outside the processing chamber wall, It has at least one cooling function of a Peltier element installed in the processing chamber or on the wafer stage.

(7) The apparatus for manufacturing a semiconductor integrated circuit device according to the present invention is the apparatus for manufacturing a semiconductor integrated circuit device according to the above (6), wherein a fin is provided on the pipe through which the temperature-adjusted liquid flows or on the Peltier element. Things.

(8) The apparatus for manufacturing a semiconductor integrated circuit device according to the present invention is the apparatus for manufacturing a semiconductor integrated circuit device according to the above (6), wherein a fan is provided above the processing chamber.

According to the above-described means, one processing chamber has one unit.
High temperature etching of about 00 to 250 ° C. and -30 to 8
Since low-temperature etching of about 0 ° C. can be continuously performed, two processing chambers for high temperature and low temperature are not required, so that the cost of the dry etching apparatus is reduced, and furthermore, the generation of foreign substances is suppressed, and the production yield is reduced. improves.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A DRAM (Dy) according to an embodiment of the present invention
FIGS. 1 to 1 show a method of fabricating a dynamic random access memory (NRAM).
3 will be described in the order of steps. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

First, as shown in FIG. 1, a semiconductor substrate 1 made of p-type silicon (Si) single crystal having a specific resistance of about 10 Ωcm is prepared, and a shallow groove 2 is formed in a main surface of the semiconductor substrate 1. Form. Thereafter, thermal oxidation is performed on the semiconductor substrate 1 to form a silicon oxide film 3. In addition, a silicon oxide film is deposited and this is chemically mechanically polished (Chemical Mechani
The silicon oxide film is left only in the shallow groove 2 by polishing by a cal polishing (CMP) method to form an isolation region 4.

Next, an n-type impurity, for example, phosphorus (P) is ion-implanted into the semiconductor substrate 1 in a region (A region: memory array) where a memory cell is to be formed, thereby forming an n-type semiconductor region 5. Part (n) of the peripheral circuit (area B)
A p-type impurity, for example, boron (B) is ion-implanted into a region where a channel-type MISFET is formed to form a p-type well 6, and another part of the peripheral circuit (p-channel type MISFET) is formed.
An n-type impurity, for example, P is ion-implanted into an SFET formation region) to form an n-type well 7. Subsequent to this ion implantation, an impurity for adjusting the threshold voltage of the MISFET, for example, boron fluoride (B
F ₂ ) is ion-implanted into the p-type well 6 and the n-type well 7. The n-type semiconductor region 5 is formed to prevent noise from entering the p-type well 6 of the memory array through the semiconductor substrate 1 from an input / output circuit or the like.

Next, as shown in FIG. 2, after the surfaces of the p-type well 6 and the n-type well 7 are cleaned using a hydrofluoric acid (HF) -based solution, the semiconductor substrate 1 is wet at about 850 ° C. Oxidation forms a clean gate oxide film 8 having a thickness of about 7 nm on each surface of the p-type well 6 and the n-type well 7.

Next, a gate electrode 9 is formed on the gate oxide film 8.
A, 9B and 9C are formed. The gate electrode 9A forms a part of the memory cell selection MISFET, and functions as a word line WL in a region other than the active region. The width of the gate electrode 9A (word line WL), that is, the gate length, has a minimum dimension within an allowable range where the short-channel effect of the memory cell selecting MISFET can be suppressed and the threshold voltage can be secured to a certain value or more. Is done. The interval between two adjacent gate electrodes 9A (word lines WL) has a minimum size determined by the resolution limit of photolithography. The gate electrode 9B and the gate electrode 9C constitute a part of each of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

Next, a method of forming the gate electrode 9A (word line WL) and the gate electrodes 9B and 9C will be described with reference to FIGS. FIG. 3 is a cross-sectional view of a main part of the semiconductor substrate showing, for example, a gate electrode 9A (word line WL).
5 is a schematic view of an example of a temperature control device provided in a processing chamber of the dry etching apparatus, FIG. 5 is a process diagram in a dry etching process, and FIG. 6 is a temperature control device provided in a processing chamber of the dry etching apparatus. FIG. 4 is a schematic view of another example of the device.

First, as shown in FIG.
A polycrystalline silicon film 9a having a thickness of about 70 nm doped with an n-type impurity such as is deposited on the semiconductor substrate 1 by a chemical vapor deposition (CVD) method.
Next, a tungsten nitride (WN) film 9b having a thickness of about 50 nm and a tungsten (W) film 9c having a thickness of about 100 nm are sequentially deposited thereon by a sputtering method, and a silicon nitride film having a thickness of about 150 nm is further formed thereon. 10 is deposited by a CVD method.

The WN film 9b functions as a barrier layer for preventing the W film 9c and the polycrystalline silicon film 9a from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface therebetween. As the barrier layer, a titanium nitride (TiN) film or the like can be used in addition to the WN film.

By forming a part of the gate electrode 9A (word line WL) with the low-resistance W film 9c, the sheet resistance can be reduced to about 2 to 2.5 Ω / □, thereby reducing the word line delay. can do. Also, the gate electrode 9A
Since the word line delay can be reduced without backing the (word line WL) with aluminum (Al) wiring or the like, the number of wiring layers formed above the memory cell can be reduced by one.

Next, the silicon nitride film 10 is etched first using the photoresist film 11 formed on the silicon nitride film 10 as a mask by the processing nitrogen DE of the dry etching apparatus shown in FIG. And WN film 9b are sequentially etched at a relatively high temperature (FIG. 3).
(B)) The polycrystalline silicon film 9a is continuously etched at a relatively low temperature in the same processing chamber DE (FIG. 3C).

The dry etching apparatus is, for example, an inductively coupled plasma (ICP).
This is an etching apparatus, and a plasma generating coil 12 is provided on the outer upper surface of the processing chamber DE. A pipe 14 is provided inside the member of the wall 13 of the processing chamber DE,
Using a circulator 16, a temperature control liquid 15 made of, for example, an organic liquid and capable of cooling or heating the inside of the processing chamber DE by flowing the liquid itself is flowed in the pipe 14. The temperature control liquid 15 is also passed through the pipe 14 inside the wafer stage 17 on which the semiconductor wafer SW is installed. In addition, a pipe 14 is installed outside the wall 13 of the processing chamber DE, and
May flow. The wall 13 is made of, for example, ceramic or metal.

Further, an introduction pipe 18 for introducing a heating gas 18a or a cooling gas 18b is provided on the wall 13 of the processing chamber DE, and inside the wafer stage 17, together with a pipe 14 through which the temperature control liquid 15 flows. , Wafer stage 1
The Peltier element 19 capable of adjusting the temperature of the Peltier 7 is attached. The Peltier element 19 is not limited to the inside of the wafer stage 17 and may be installed inside the processing chamber DE, or may be attached to an inner member of the wall 13 of the processing chamber DE or outside the wall 13. Above the processing chamber DE, an infrared lamp 2 capable of heating the processing chamber DE
A plurality of 0s are provided. Further, a fan 21 is provided above the infrared lamp 20, and the processing chamber D
By stirring the atmosphere in the region where E is placed, the temperature can be made constant.

Next, an example of a procedure for etching the W film 9c, the WN film 9b, and the polycrystalline silicon film 9a will be described with reference to FIG.

First, the temperature of the semiconductor wafer SW placed on the wafer stage 17 in the processing chamber DE shown in FIG. 4 is heated to about 100 to 250 ° C. (heating step). In this heating, after the processing chamber DE is heated by the infrared lamp 20 (step 100 in FIG. 5), the temperature control liquid 15 flowing through the pipe 14 installed inside the member of the wall 13 and the inside of the wafer stage 17 and the introduction pipe 18 The temperature of the processing chamber DE is adjusted to, for example, about 180 ° C. by using at least one heating method of the heating gas 18 a introduced into the processing chamber DE from the Peltier element 19 (see FIG. 5). Step 101).

Next, using a chlorine (Cl ₂ ) gas as an etching gas, a source power of 1000 W and a bias power of 200 W
The W film 9c and the WN film 9b are sequentially etched under the condition of W (Step 102 in FIG. 5). After the etching is completed, the heating by the infrared lamp 20 and other heating means are stopped (step 103 in FIG. 5).

Next, with the semiconductor wafer SW placed on the wafer stage 17 in the processing chamber DE, the semiconductor wafer SW
Is cooled to about −30 to 80 ° C. (cooling step).
This cooling is performed inside the member of the wall 13 and the wafer stage 1.
The temperature of the processing chamber DE is adjusted by using at least one of the temperature control liquid 15, the cooling gas 18b introduced from the introduction pipe 18 into the processing chamber DE, and the Peltier element 19 through the pipe 14 installed in the pipe 7, for example. This is performed by adjusting the temperature to about 50 ° C. (Step 104 in FIG. 5).

Next, the polycrystalline silicon film 9a is etched under the conditions of a source power of 500 W and a bias power of 100 W using HBr gas and Cl ₂ gas as an etching gas (step 105 in FIG. 5). By using HBr gas as the etching gas, the polycrystalline silicon film 9a can be processed vertically. After the above etching,
The cooling means is stopped (step 106 in FIG. 5).

The fan 21 may be used in a heating step and a cooling step in order to keep the ambient temperature in a region where the processing chamber DE is placed, or may be used only as a cooling fan. Good.

As shown in FIG. 6, a fin 14a may be provided on a pipe 14 provided inside the member of the wall 13 of the processing chamber DE to increase the efficiency of heat transfer. Further, a Peltier element 19 is provided inside the member of the wall 13 of the processing chamber DE.
May be provided on the Peltier element 19 to improve the efficiency of heat transfer similar to the fin 14a.

Next, the photoresist film 11 is removed, and then a dry etching residue and a photoresist residue remaining on the surface of the semiconductor substrate 1 are removed using an etching solution such as HF. When this wet etching is performed,
Gate electrode 9A (word line WL) and gate electrode 9
Since the gate oxide film 8 in the region other than the lower portions of B and 9C is shaved, the gate oxide film 8 in the lower portion of the gate side wall is also isotropically etched to produce an undercut. descend. Therefore, the quality of the cut gate oxide film 8 is improved by oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, a p-type impurity, for example, B is ion-implanted into the n-type well 7 to form a p ^- type semiconductor region 22 in the n-type well 7 on both sides of the gate electrode 9C. Also, an n ^- type semiconductor region 23 is formed in the p-type well 6 on both sides of the gate electrode 9B by ion-implanting an n-type impurity, for example, P, in the p-type well 6, and the p-type well 6 on both sides of the gate electrode 9A is formed.
Then, an n-type semiconductor region 24 is formed. Thus, a memory cell selecting MISFET is formed in the memory array.

Next, as shown in FIG. 7, after a silicon nitride film 25 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by the CVD method, the silicon nitride film 25 of the memory array is covered with a photoresist film. By anisotropically etching the silicon nitride film 25 of the circuit, the gate electrodes 9B, 9
A sidewall spacer 26 is formed on the side wall of C. This etching uses an etching gas that increases the etching rate of the silicon nitride film 25 with respect to the silicon oxide film in order to minimize the amount of shaving of the silicon oxide film embedded in the gate oxide film 8 and the isolation region 4. Do it. Also, the silicon nitride film 1 on the gate electrodes 9B and 9C
In order to minimize the abrasion amount of 0, the amount of over-etching is kept to a necessary minimum.

Next, after removing the photoresist film, a p-type impurity, for example, B is ion-implanted into the n-type well 7 of the peripheral circuit, and the p ⁺ -type semiconductor region 27 (source, drain) of the p-channel MISFET is implanted. Is formed, and an n-type impurity, for example, arsenic (As) is ion-implanted into the p-type well 6 of the peripheral circuit to form an n ⁺ -type semiconductor region 28 (source, drain) of the n-channel MISFET. Thereby, the p-channel type MISFET and the n-channel
A channel MISFET is formed.

Next, as shown in FIG. 8, an SOG (spin-on-glass) film 29 having a film thickness of about 300 nm is spin-coated on the semiconductor substrate 1, and then the semiconductor substrate 1 is heated at 800.degree.
SOG film 29 is sintered (baked) by heat treatment for about a minute.

Next, a film thickness of 600 n is formed on the SOG film 29.
After the silicon oxide film 30 having a thickness of about m is deposited, the silicon oxide film 30 is polished by a CMP method to planarize the surface. The silicon oxide film 30 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, a film having a thickness of 1
A silicon oxide film 31 of about 00 nm is deposited. The silicon oxide film 31 is deposited in order to repair fine scratches on the surface of the silicon oxide film 30 generated when the silicon oxide film 31 is polished by the CMP method. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas. A PSG (Phospho Silicate Glass) film may be deposited on the silicon oxide film 30 instead of the silicon oxide film 31.

Next, the silicon oxide films 31, 30 and the SOG film 29 on the n-type semiconductor region 24 (source, drain) of the memory cell selecting MISFET are removed by dry etching using the patterned photoresist film as a mask. I do.

The above-mentioned etching is performed under such a condition that the etching rates of the silicon oxide films 31 and 30 and the SOG film 29 with respect to the silicon nitride film 25 are increased, and the n-type semiconductor region 24 and the upper portion of the isolation region 4 are covered. The remaining silicon nitride film 25 is not completely removed.

Subsequently, the memory cell selecting MISFET is formed by dry etching using the photoresist film as a mask.
The contact hole 32 is formed on one of the n-type semiconductor regions 24 (source and drain) by removing the silicon nitride film 25 and the gate oxide film 8 above the n-type semiconductor region 24 (source and drain). Then, a contact hole 33 is formed on the other. This etching is performed under such a condition that the etching rate of the silicon nitride film 25 with respect to the silicon oxide film (the gate oxide film 8 and the silicon oxide film in the isolation region 4) is increased, and the n-type semiconductor region 24 and the isolation region 4 are deep. Avoid scraping. This etching is performed under such a condition that the silicon nitride film 25 is anisotropically etched so that the silicon nitride film 25 remains on the side wall of the gate electrode 9A (word line WL). As a result, contact holes 32 and 33 having a fine diameter equal to or smaller than the resolution limit of photolithography are formed in self-alignment with the gate electrode 9A (word line WL). In order to form the contact holes 32 and 33 in a self-aligned manner with respect to the gate electrode 9A (word line WL), the silicon nitride film 25 is anisotropically etched in advance to form a side wall on the side wall of the gate electrode 9A (word line WL). A spacer may be formed.

Next, after removing the photoresist film, a plug 34 is formed inside the contact holes 32 and 33 as shown in FIG. The plug 34 is formed by depositing a polycrystalline silicon film doped with an n-type impurity, for example, P on the silicon oxide film 31 by a CVD method, and then polishing the polycrystalline silicon film by a CMP method to form a contact hole 3.
It is formed by leaving it inside 2, 33.

Next, as shown in FIG. 10, a silicon oxide film 3 having a thickness of about 200 nm
After depositing 5, the semiconductor substrate 1 is heat-treated at about 800.degree. The silicon oxide film 35 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas. Further, by this heat treatment, n-type impurities in the polycrystalline silicon film forming plug 34 are removed from contact holes 32 and 3.
3 diffuses into the n-type semiconductor region 24 (source, drain) of the MISFET for memory cell selection, and the resistance of the n-type semiconductor region 24 is reduced.

Next, the silicon oxide film 35 on the contact hole 32 is removed by dry etching using a photoresist film as a mask to expose the surface of the plug 34. Next, after removing the photoresist film, the silicon oxide films 35, 31, 30, the SOG film 29 and the gate oxide film 8 of the peripheral circuit are removed by dry etching using the photoresist film as a mask. A contact hole 36 is formed on the p ⁺ type semiconductor region 27 (source and drain) of the n-type MISFET, and a contact hole 37 is formed on the n ⁺ type semiconductor region 28 (source and drain) of the n-channel MISFET.

Next, after removing the photoresist film, a bit line BL and a first layer wiring 38 of a peripheral circuit are formed on the silicon oxide film 35 as shown in FIG. The bit line BL and the first layer wiring 38 are formed, for example, on a silicon oxide film 35 by titanium (T
i) A film and a TiN film having a thickness of about 50 nm are deposited by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 39a having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are formed by patterning these films using a resist film as a mask.

After a Ti film is deposited on the silicon oxide film 35, the semiconductor substrate 1 is subjected to a heat treatment at about 800 ° C. so that the Ti film reacts with the Si substrate to form a p-channel type M substrate.
The surface of the p ⁺ -type semiconductor region 27 (source and drain) of the ISFET, the surface of the n ⁺ -type semiconductor region 28 (source and drain) of the n-channel MISFET, and the surface of the plug 34 embedded in the contact hole 32 have low resistance. A titanium silicide (TiSi ₂ ) layer 40 is formed.
Thereby, wiring (bit line B) connected to p ⁺ type semiconductor region 27, n ⁺ type semiconductor region 28 and plug 34 is formed.
L, the contact resistance of the first layer wiring 38) can be reduced. Further, the bit line BL is connected to the W film / TiN film / Ti
By using a film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the bit line BL and the first layer wiring 38 of the peripheral circuit can be formed simultaneously in the same step.

Next, after removing the photoresist film, a sidewall spacer 39b is formed on the side wall of the bit line BL and the first layer wiring 38. The sidewall spacer 39b is formed by depositing a silicon nitride film on the bit line BL and the first layer wiring 38 by a CVD method and then anisotropically etching the silicon nitride film.

Next, as shown in FIG.
And an S layer having a thickness of about 300 nm
After spin coating the OG film 41, the semiconductor substrate 1
The SOG film 41 is sintered (baked) by heat treatment at about 1 ° C. for about 1 minute.

Next, a thickness of 600 n is formed on the SOG film 41.
After a silicon oxide film 42 having a thickness of about m is deposited, the silicon oxide film 42 is polished by a CMP method to flatten its surface. The silicon oxide film 42 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas.

Next, a film thickness of 1
A silicon oxide film 43 of about 00 nm is deposited. The silicon oxide film 43 is deposited in order to repair fine scratches on the surface of the silicon oxide film 42 generated when the silicon oxide film 43 is polished by the CMP method. The silicon oxide film 43 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas.

Next, the silicon oxide films 43 and 42 in the upper layer of the plug 34 embedded in the contact hole 33 by dry etching using a photoresist film as a mask,
The film 41 and the silicon oxide film 35 are removed and the plug 34 is removed.
Is formed to reach the surface of the substrate. This etching is performed on the silicon oxide films 43, 42, 35 and SO
The etching is performed under such a condition that the etching rate of the silicon nitride film with respect to the G film 41 is increased.
The upper silicon nitride film 39a and the side wall spacers 39b are not deeply shaved. As a result, the through hole 44 is formed in self alignment with the bit line BL.

Next, after removing the photoresist film, a plug 45 is formed inside the through hole 44.
The plug 45 is to deposit a polycrystalline silicon film doped with an n-type impurity, for example, P, on the silicon oxide film 43 by a CVD method, and then etch back the polycrystalline silicon film to leave it inside the through hole 44. Is formed.

Next, as shown in FIG. 13, a silicon nitride film 4 having a thickness of about 100 nm
6 is deposited by the CVD method, and the silicon nitride film 4 of the peripheral circuit is dry-etched using the photoresist film as a mask.
6 is removed. Silicon nitride film 4 remaining in memory array
Reference numeral 6 is used as an etching stopper for etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor C described later.

Next, after removing the photoresist film, a silicon oxide film 47 having a thickness of about 1.3 μm is deposited on the silicon nitride film 46, and the silicon oxide film is dry-etched using the photoresist film as a mask. A groove 48 is formed above the through-hole 44 by removing the 47 and the silicon nitride film 46. At the same time, a frame-like groove 48 surrounding the memory array is formed around the memory array.
a is formed. The silicon oxide film 47 is made of, for example, O ₃ and T
EOS is deposited by a plasma CVD method using a source gas.

Next, after removing the photoresist film, an n-type impurity such as P
Doped polycrystalline silicon film 49 having a thickness of about 60 nm
Is deposited by a CVD method. This polycrystalline silicon film 49
It is used as a lower electrode material of the information storage capacitor C.

Next, the trench 4 is formed on the polycrystalline silicon film 49.
A film thickness larger than the depth of 8, 48a (for example, about 2 μm)
The SOG film 50 is spin-coated, the SOG film 50 is etched back, and the polycrystalline silicon film 49 on the silicon oxide film 47 is etched back, thereby forming the trench 4.
The polycrystalline silicon film 49 is left inside (the inner wall and the bottom) of 8, 48a.

Next, the SOG film 40 inside the groove 48 and the silicon oxide film 47 in the gap between the groove 48 are wet-etched by using a photoresist film covering the silicon oxide film 47 of the peripheral circuit as a mask, so that the information storage capacitor C is formed. Is formed. At this time, the silicon nitride film 4
Since the silicon oxide film 6 remains, the silicon oxide film 43 thereunder is not etched. One end of the photoresist film covering the silicon oxide film 47 of the peripheral circuit is disposed at the boundary between the lower electrode 51 formed on the outermost side of the memory array and the peripheral circuit region, that is, above the groove 48a. In this way, even when misalignment occurs at the end of the photoresist film, the SOG film 50 is formed inside the groove 48 of the lower electrode 51 formed on the outermost side of the memory array.
Does not remain, and the silicon oxide film 47 of the peripheral circuit is not etched.

Next, in order to prevent the oxidation of the polycrystalline silicon film 49 constituting the lower electrode 51, the semiconductor substrate 1 is heat-treated at about 800 ° C. in an ammonia atmosphere to remove the photoresist film. After nitriding the surface of the crystalline silicon film 49, a film thickness of 20 nm
A tantalum oxide (Ta ₂ O ₅ ) film 52 is deposited by a CVD method, and the semiconductor substrate 1 is heat-treated at about 800 ° C. to activate the Ta ₂ O ₅ film 52. This Ta ₂ O ₅ film 5
Reference numeral 2 is used as a material for a capacitive insulating film of the information storage capacitive element C.

Next, after a TiN film 53 having a thickness of about 150 nm is deposited on the Ta ₂ O ₅ film 52 by CVD and sputtering, the TiN film 53 and the Ta are etched by dry etching using a photoresist film as a mask. ₂ O ₅ film 52
Is patterned to form an upper electrode made of a TiN film 53, a capacitance insulating film made of a Ta ₂ O ₅ film 52,
An information storage capacitor C composed of the lower electrode 51 made of the polycrystalline silicon film 49 is formed. Thus, a DRAM memory cell composed of the memory cell selection MISFET and the information storage capacitor C connected in series thereto is completed.

Thereafter, a passivation film is deposited on the multi-layer wiring and the uppermost wiring, but illustration thereof is omitted.

As described above, according to the present embodiment, high-temperature etching of W film 9c at 100 to 250 ° C. and low-temperature etching of polycrystalline silicon film 9a at −30 to 80 ° C. are successively performed in one processing chamber DE. Can be done. Therefore,
Since two processing chambers for high temperature and low temperature are not required, the cost of the dry etching apparatus is reduced, and the number of foreign substances on the semiconductor wafer can be reduced, thereby improving the production yield.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

[0067]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the cost of the dry etching apparatus can be reduced, the number of foreign substances on the semiconductor wafer can be reduced, and the manufacturing yield can be improved, so that the manufacturing cost of the semiconductor integrated circuit device can be reduced. .

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the gate electrode of the MISFET according to one embodiment of the present invention;

FIG. 4 is a schematic view of an example of a processing chamber of a dry etching apparatus according to an embodiment of the present invention.

FIG. 5 is a process diagram illustrating a dry etching technique according to an embodiment of the present invention.

FIG. 6 is a schematic view of another example of the processing chamber of the dry etching apparatus according to the embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 shallow groove 3 silicon oxide film 4 isolation region 5 n-type semiconductor region 6 p-type well 7 n-type well 8 gate oxide film 9A gate electrode 9B gate electrode 9C gate electrode 9a polycrystalline silicon film 9b tungsten nitride film 9c Tungsten film 10 Silicon nitride film 11 Photoresist film 12 Plasma generating coil 13 Wall 14 Pipe 14a Fin 15 Temperature control liquid 16 Circulator 17 Wafer stage 18 Inlet tube 18a Heating gas 18b Cooling gas 19 Peltier element 19a Fin 20 Infrared lamp 21 Fan 22 p ^- type semiconductor region 23 n ^- -type semiconductor region 24 n-type semiconductor region 25 the silicon nitride film 26 sidewall spacers 27 p ⁺ -type semiconductor region 28 n ⁺ -type semiconductor region 29 SOG film 30 a silicon oxide film 31 oxide Recon film 32 Contact hole 33 Contact hole 34 Plug 35 Silicon oxide film 36 Contact hole 37 Contact hole 38 First layer wiring 39a Silicon nitride film 39b Sidewall spacer 40 Titanium silicide layer 41 SOG film 42 Silicon oxide film 43 Silicon oxide film 44 Through Hole 45 Plug 46 Silicon nitride film 47 Silicon oxide film 48 Groove 48a Groove 49 Polycrystalline silicon film 50 SOG film 51 Lower electrode 52 Silicon oxide film 53 Silicon nitride film A Memory cell B Peripheral circuit BL Bit line WL Word line C Information storage Capacitive element SW Semiconductor wafer DE Processing chamber

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Keiji Kuroki 3F, 6-16 Shinmachi, Ome-shi, Tokyo 3F004 BA01 BB25 BB26 BB27 BC04 BC08 CA01 CA04 DA04 DB02 DB03 DB04 DB07 DB08 DB10 DB12 DB13 DB17 DB18 EB01 EB02 5F083 AD24 AD48 AD49 JA06 JA35 JA39 JA40 JA56 KA05 MA03 MA04 MA06 MA17 MA19 MA20 PR03 PR06 PR21 PR23 PR33 PR40 PR43 PR44 PR45 PR53 PR54 PR55 ZA04 ZA06

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device for processing a laminated film composed of a first film and a second film deposited on a semiconductor wafer, wherein the semiconductor wafer is 100 to
After heating to about 250 ° C. to etch the first film, the semiconductor wafer is continuously cooled to −30 in the same processing chamber.
A method for manufacturing a semiconductor integrated circuit device, comprising cooling to about 80 ° C. and etching the second film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor wafers are each heated by an infrared lamp, a heating gas introduced into the processing chamber, Inside the member of the wall, outside the wall of the processing chamber or a temperature control liquid flowing to the wafer stage,
An air cooling fan that is heated by at least one heating method among a member inside the wall of the processing chamber, outside the wall of the processing chamber, inside the processing chamber, or a Peltier element installed on the wafer stage, and is a cooling method. A cooling gas introduced into the inside of the processing chamber, a temperature control liquid flowing inside the member of the processing chamber wall, outside the wall of the processing chamber or on the wafer stage, and inside the member of the wall of the processing chamber. A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor device is cooled by at least one of a cooling method outside a wall of the processing chamber, inside the processing chamber or on a wafer stage. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the pipe or the Peltier element through which the temperature control liquid flows has fins. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first film is a tungsten film, a molybdenum film, a tungsten silicide film or a molybdenum silicide film, and said second film is a multi-layer film. A method for manufacturing a semiconductor integrated circuit device, wherein the method is a crystalline silicon film. 5. A semiconductor integrated circuit device having a processing chamber provided with a function of heating a semiconductor wafer to about 100 to 250 ° C. and a function of cooling the semiconductor wafer to about −30 to 80 ° C. Manufacturing equipment. 6. The apparatus for manufacturing a semiconductor integrated circuit device according to claim 5, wherein an infrared lamp, which is a heating method, a heating gas introduced into the inside of the processing chamber, a member inside a wall of the processing chamber, A temperature control liquid flowing outside the processing chamber wall or on the wafer stage, and a Peltier element installed inside the processing chamber wall, outside the processing chamber wall, inside the processing chamber or on the wafer stage. An air cooling fan having at least one heating function among them, a cooling method, and a cooling gas introduced into the inside of the processing chamber, a member inside a wall of the processing chamber, an outside of a wall of the processing chamber or At least one of a temperature control liquid flowing through the wafer stage and a Peltier element installed inside a member of the processing chamber wall, outside the processing chamber wall, inside the processing chamber or on the wafer stage. An apparatus for manufacturing a semiconductor integrated circuit device having two cooling functions. 7. The apparatus for manufacturing a semiconductor integrated circuit device according to claim 6, wherein a fin is provided on a pipe or the Peltier element through which the temperature-adjusted liquid flows. 8. An apparatus for manufacturing a semiconductor integrated circuit device according to claim 6, wherein a fan is provided above said processing chamber.