JP2001083938A - El display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove a polarized charge remaining in EL elements without a feeling of incongruity. SOLUTION: An EL display panel 1 comprises plural EL elements. A luminescence driving voltage is applied by driving circuits 2-4 on a scanning electrode and a data electrode of the EL display panel 1 to start a luminescence operation. A reference voltage is supplied corresponding to positive and negative fields from a power source circuit 5 to scanning electrode circuits 2, 3 through a scanning voltage supply circuit 6. A control circuit 8 supplies a voltage by executing switching control of an FET 51 of the power source circuit 5 by switching an ACC switch 9 to the ON state. When the switch 9 is switched to the OFF state, the power source circuit 5 is switched to the OFF state after one second. During that time, an erasing pulse voltage is applied on the EL display panel 1 to remove a polarized charge. Hereby, mis-luminescence is prevented at the starting time of the next luminescence operation, and simultaneously luminescence caused by application of the erasing pulse voltage can be controlled in the degree of no feeling of incongruity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EL display device having a display section provided with a plurality of EL elements, and more particularly to a method for solving the problem caused by internal charges remaining after the light emitting operation of the EL elements is completed. EL display device.

[0002]

2. Description of the Related Art An EL panel, which is an EL display device, has a large number of EL elements arranged thereon. The EL elements are formed by sandwiching a light emitting layer between an insulating layer and a pair of electrodes. Some have been formed. Such an EL element performs a light emitting operation by applying a driving voltage between a pair of electrodes, and it is known that after the light emitting operation, polarized charges remain inside.

FIG. 15 illustrates this phenomenon, in which the horizontal axis represents the drive voltage V and the vertical axis represents the charge amount Q.
When no voltage is applied to the EL element and no internal polarization charge exists, the EL element is in a position Po in the drawing. Next, when a pulse-like drive voltage Vr (a voltage higher than the light emission start voltage) is applied to cause the EL element to emit light, the charge amount Q changes to the state of Pb through the state of Pa in the figure as the applied voltage V increases. Thereafter, even if the applied voltage V becomes zero, the position returns to the position Pc instead of the initial position Po. That is, even when no voltage is applied, the internal polarization charge remains. In this case, the EL element emits light during the period from the position Pa to the position Pb.

After that, when the polarity of the voltage applied between the electrodes is inverted and the same pulse-like drive voltage -Vr is applied, the position Pc is shifted from the state of Pc along the slope of the negative voltage application.
The state transits from the state of d to the states of Pe and Pf and emits light during the period from the state of the position Pd to the state of the position Pf. Thereafter, when the applied voltage becomes zero, the state transits to the state of the position Pg. In the state of the position Pg, a state in which negative internal polarization charges remain.

When the EL element that has emitted light is set to a non-emission state, a light emission start voltage Vr-Vm is applied between the electrodes to reduce the internal polarization charge to zero. When a non-light-emission state is performed after the light-emission operation is performed by applying the positive drive voltage Vr, a negative light-emission start voltage − (Vr−Vm) is applied during a subsequent negative voltage application period. Thus, the state of the position Pc returns to the state of Po via the positions Pd and Pe, that is, the state in which the internal polarization charge is zero. Similarly, when the light emission operation is performed by applying the negative drive voltage -Vr and then the light emission is stopped, the positive emission start voltage Vr-
Vm is applied. Accordingly, the state of the position Pg returns to the state of Po via the positions Ph and Pa, that is, the state in which the internal polarization charge is zero.

As described above, even in the non-light emitting operation, the light emitting start voltage Vr-Vm or-(Vr
In the period of transition from the position Pd to the state of Pe when applying −Vm), or the period of transition from the position Ph to the state of Pa, there is some light emission. Since the state is very dark compared to the brightness of the EL element that emits light, it can be regarded as substantially a non-emission state.

[0007]

However, when the power supply to the EL element is turned off, a voltage for performing a non-light emitting operation cannot be applied. The internal polarization charge Q
The state where c or Qg remains remains. As described above, if the internal polarization charge Qc or Qg remains, even when a voltage for performing a non-light emitting operation is applied when the power is turned on next time, the discharge is accompanied by polarization during the discharge process. Since a weak light emission operation is involved, erroneous light emission may occur for a moment, reproducing the state displayed immediately before the power is turned off.

Therefore, conventionally, in order to prevent such erroneous light emission when the power is turned on, the internal polarization charge is eliminated as follows, for example. That is, as disclosed in the earlier application, Japanese Patent Application Laid-Open No. 11-95724, the applicant of the present invention discharges internal charges by applying an erase pulse voltage when the power is off, and then turns off the power. This figure shows a configuration in which erroneous light emission is prevented when the light is turned on.

However, in the present invention, it has been shown that the internal charge is eliminated by applying one or more erase pulse voltages. However, actually, the characteristics of the film of the EL element and the film formation process are reduced. Due to the manufacturing variation of the device, there is a case where the internal charge cannot be sufficiently eliminated only by once applying the erase pulse voltage which is substantially equal to the pulse width of the drive voltage in the non-light emitting operation. In this case, a similar problem occurs when the power is turned on.

On the other hand, since the application of such an erase pulse voltage is performed once or more, it can be applied without any limitation thereafter. Even when a non-light emitting voltage is applied due to the influence of electric charge, there is a slight light emitting phenomenon. For example, when the surroundings are dark, for example, in a dark place or at night, the entire body shines, so that the user becomes particularly conspicuous, and the user may feel uncomfortable.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce the application time of an erasing voltage applied when stopping a display operation while sufficiently lowering the light emission luminance and causing a user to feel uncomfortable. It is an object of the present invention to provide an EL display device capable of setting an optimal application time to such an extent that the user does not feel the problem.

[0012]

According to the first aspect of the present invention, the driving means selectively supplies a driving voltage supplied from a power supply means to a plurality of EL elements based on display data, and performs light emission driving. Then, the display operation is performed, and the erasing voltage applying means stops the display operation by the driving means.
An erasing voltage set near the light emission start voltage is applied to the L element, thereby eliminating the internal polarization charge component associated with the light emission operation of the EL element. Thus, when the EL element is driven next time, it is possible to eliminate a display operation caused by the remaining polarization charges.

At this time, in the EL element, even if the erasing voltage is in the vicinity of the light emission start voltage, a slight light emission phenomenon occurs,
In particular, the tendency is increased in an EL element that has just performed a light emitting operation. The erasing voltage applying means sets the application time of the erasing voltage as a time during which the luminance of the EL element accompanying the erasing voltage application becomes equal to or less than a predetermined luminance. , Even if the next light emission operation is performed, EL
Erroneous light emission caused by the internal charge of the element is not recognized by the user. Therefore, for example, polarization charge is sufficiently eliminated by short-time application of an erasing voltage due to variations in film thickness of an insulating film, a light-emitting layer, and the like when forming an EL element, and variations in other driving conditions. Even when the display cannot be performed, this can be surely solved, and erroneous light emission at the start of the next display operation can be reliably prevented.

According to the second aspect of the present invention, the application time of the erasing voltage by the erasing voltage applying means is set to 1c as a predetermined luminance.
Since the brightness is set to about d / m ² or less, it is possible to sufficiently achieve the above-mentioned object and to unnecessarily set a long application time.

According to the third aspect of the present invention, the erasing voltage is applied in the same manner as in the first aspect of the present invention. Since the luminance ratio of low luminance to high luminance is set to about 0.7 or more, it is necessary to set relative conditions even if absolute luminance is not sufficient. Thus, even when the light emission is erroneous in the next display operation, the display can be reduced to such a degree that the display is not bothersome. Conversely, the purpose can be sufficiently achieved by applying the erasing voltage only until the luminance condition is satisfied.

According to a fourth aspect of the present invention, in the first to third aspects of the present invention, in the case where a translucent filter member is provided on the front surface of the display unit, a display state by light emission of the display unit is provided. Is dimmed, so that even if the luminance at which the EL element emits light in response to the application of the erasing pulse voltage does not satisfy the above-described condition, the luminance seen by the user is reduced. The original purpose is to prevent erroneous light emission at the time of the next display operation, so that the application time of the erase voltage may be set so as to satisfy the condition. As a result, in the configuration in which the filter member is provided, the erase voltage is reduced. Can be shortened, and the light emitting state accompanying the application of the erasing voltage when the display operation is stopped can be completed in a short time, so that the user is not bothered.

According to the fifth aspect of the present invention, the erasing voltage application means controls the application of the erasing voltage by the pulse voltage in the same cycle as the light emitting operation. The control can be easily performed by performing the non-light-emission control without performing the control.The purpose can be sufficiently achieved by repeatedly applying the pulse voltage and setting the time as described above. Will be able to

According to the sixth aspect of the present invention, the application of the pulse voltage is controlled by setting the pulse voltage to a dimming condition as compared with the light emission operation so as to lower the luminance of the EL element. In such a case, the erasing state can be applied without worrying about the light emitting state.
According to the seventh aspect of the present invention, the dimming condition is set so that the luminance becomes equal to or less than the predetermined luminance when a predetermined time has elapsed after the application of the erasing voltage. Therefore, the luminance can be rapidly reduced. It is possible to complete the processing in a short time while achieving the function of preventing erroneous light emission due to the above-mentioned manufacturing variation.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention, when the dimming condition is set so that the luminance becomes equal to or less than a predetermined luminance when a predetermined time has elapsed, the application of the pulse voltage is controlled. When the display operation is started, the erasing voltage is applied to the EL element that is not driven to emit light by the erasing voltage applying means under the same condition as the dimming condition, so that light emission due to the polarization charge remaining during the non-light emitting operation is prevented. Will be able to

According to the ninth aspect of the present invention, when the erasing voltage is applied by the erasing voltage applying means, the pulse width of the driving voltage applied during the light emission operation is made narrower as the dimming condition. Is applied, the light emission time can be shortened to reduce the light. Claim 10
According to the invention, since the voltage value is set to be lower than the voltage for the non-light emitting operation applied during the light emitting operation, the light emission intensity itself can be reduced to reduce the light. Furthermore, according to the eleventh aspect of the present invention, as the dimming condition, the pulse voltage is applied with a repetition period longer than the repetition period applied during the light emission operation, so that the number of light emission per unit time can be reduced to reduce the light. become able to.

According to the twelfth aspect of the invention, the erasing voltage application means selectively controls the application of the erasing voltage for the EL element which has just performed the light emitting operation. Since the erasing voltage is applied only to those which could not be performed, the current consumption can be reduced. In addition, when the number of EL elements that have just emitted light is small, useless current is almost consumed. It can be implemented without.

According to the thirteenth aspect of the present invention, the period during which the erase voltage is applied by the erase voltage applying means is stopped at a maximum of 1 second if the time satisfying the above condition is within 1 second. As described above, the waste of applying the erasing voltage can be eliminated, and the weak light emitting state during the application of the erasing voltage can be prevented from continuing unnaturally, so that the operation can be completed without giving the user a sense of incongruity.

According to the fourteenth aspect of the present invention, when the display section is made of a light-transmitting EL element, the application time of the erasing voltage by the erasing voltage applying means differs from the above case by 0.5. Set about seconds as the upper limit. When such a display unit is provided, the display unit may be placed in a state in which an object located on the back surface can be seen through in a non-display state. If 1 second is set as the upper limit time as described above, it may be unnatural that the weak light emitting state during the application of the erase voltage is continued, which may cause a feeling of strangeness. Correspondingly, since 0.5 seconds is set as the upper limit, it is possible to suppress the user from feeling uncomfortable.

According to the fifteenth aspect of the present invention, the power supply circuit comprises switching means and a switching control section for driving and controlling the switching means, and the switching control section performs switching when the control of the erasing voltage application by the erasing voltage applying means ends. The power supply operation is stopped by turning off the means. Further, according to the invention of claim 16, the power supply to the power supply circuit is stopped when the control of the application of the erase voltage is completed by the erase voltage applying means. Thus, the power supply from the power supply circuit to the driving unit can be stopped at the time when the application control of the erase voltage is completed. In the invention of claim 16, the power supply to the power supply circuit itself is also stopped.
When applied to an apparatus using a battery or the like, consumption of dark current or the like can be prevented.

According to the seventeenth aspect of the present invention, the power supply circuit is constituted by the switching means fed from the vehicle-mounted power supply circuit and the switching control unit for controlling the driving of the power supply circuit, and the control of the application of the erase voltage by the erase voltage applying means is completed. Then, since the power supply from the vehicle power supply circuit is stopped,
It can be operated under the usage conditions of the vehicle-mounted power supply circuit. In addition, when the power supply stop condition of the vehicle-mounted power supply circuit is set to a condition that the ignition switch or the accessory switch (ACC) stops at a predetermined time from the time of turning off,
For example, when the time is about one second, the condition used in claim 13 can be applied as it is to adopt a configuration for stopping power supply.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) The present invention is applied to a display section in which an EL display device in which EL elements are arranged in a matrix is mounted on an automobile or the like and is driven by a vehicle battery. The first embodiment in such a case will be described with reference to FIGS. FIG. 1 shows the entire electrical configuration, and an EL display panel 1 serving as a display unit includes:
A large number of EL elements 100 are arranged and formed in a matrix, and the display operation is controlled by a drive circuit unit including two scan electrode drive circuits 2 and 3 and a data electrode drive circuit 4. I have.

Scan electrode drive circuits 2 and 3 are supplied with drive voltages output from power supply circuit 5 and switched by scan voltage supply circuit 6 via drive lines L1 and L2. The drive voltage output from the power supply circuit 5 is supplied to the data electrode drive circuit 4 via power supply lines L3 and L4. Note that the power supply circuit 5 and the scanning voltage supply circuit 6 constitute a power supply unit according to the present invention.

The power supply circuit 5 outputs a DC modulation voltage Vm (for example, 45 V) to the power supply line L3, and outputs a ground voltage (0 V) to the power supply line L4, as described later. The power supply circuit 5 outputs a floating voltage (Vr-Vm) (for example, 210 V) to the scanning voltage supply circuit 6 and a floating control voltage Vc (for example, 5 V).
Is output. The scanning voltage supply circuit 6 supplies a driving voltage Vr (for example, 255 V) or a ground voltage (0 V) to the power supply line L1.
V) by switching setting (in FIG. 2, indicated as a scanning voltage supply circuit 6a), and a modulation voltage Vm or a driving voltage − (Vr−Vm) (for example, −21) is applied to the power supply line L2.
0V) is applied by switching setting (in FIG. 2, it is indicated as a scanning voltage supply circuit 6b).

The power supply circuit 5 supplies the output voltage + B of the positive terminal of the on-vehicle battery Ba to the primary side of the transformer and controls the switching to output the desired voltage to the secondary side as a desired voltage. Control power is supplied via 7. The switch control circuit 7 receives a control signal Pon from a control circuit 8 to which power is supplied when the ACC switch 9 of the vehicle is turned on. Hereinafter, details of these configurations will be described.

As shown in a schematic cross section in FIG. 4, a large number of EL elements 100 constituting the EL display panel 1 have a transparent electrode 102, an insulating layer 103, a light emitting layer 104, an insulating layer 105, Each thin film of the back electrode 106 is sequentially laminated. By applying a positive or negative driving voltage between the transparent electrode 102 and the back electrode 106, a light emitting operation is performed based on a well-known operation principle, and erroneous light emission is performed by applying an erasing voltage as described later. Perform preventive action.

The emission output of the EL element 100 is
A display operation is performed by selectively driving a large number of EL elements 100 to emit light, which is obtained from the glass substrate 101 from the 02 side. In addition, by forming the back electrode 106 with a transparent electrode, in a non-light emitting state, a transparent glass plate can be seen through an object behind,
In the light emitting state, the transparent type EL display panel 1 capable of extracting light output from both the near side and the back side can be configured.

Next, in order to obtain a structure in which the EL display panel 1 is provided with a large number of EL elements 100 having the above-described structure,
As shown in FIG. 2, a transparent electrode 102 and a back electrode 106 formed on a glass substrate 101 are formed as a large number of linear electrodes so as to be orthogonal to each other. Specifically, odd-numbered scan electrodes 201, 202,
, Scanning electrodes 301, 302,... Are formed in even numbers, and data electrodes 401, 402,.

Scan electrodes 201, 301, 202, 30
, And data electrodes 401, 402,..., The above-described EL elements 100 are formed. These are used as EL elements 111 and 112 as pixels.
, 121, 122, ... are provided. Since these EL elements are capacitive loads due to their characteristics, they are indicated by capacitors in the figure. Scan electrodes 201, 202,... And scan electrode 30
Are connected to the scanning electrode driving circuits 2 and 3, respectively, and the data electrodes 401, 402,... Are connected to the data electrode driving circuit 4.

The scanning electrode driving circuit 2 is provided with each scanning electrode 20.
, 202,..., A drive voltage is output from a push-pull type drive circuit, and each of the drive circuits includes a p-channel FET 21 connected to a power supply line L1.
, and n-channel FETs 21b, 22b,... connected to the power supply line L2. Note that each of the FETs 21a, 22a,.
, b are parasitic diodes 21c, 22c,.
21d, 22d,...

For example, a p-channel FET 21 is supplied to the scan electrode 201 by a control signal from the logic circuit 20.
Turning on either the a or n-channel FET 21b connects to the power supply line L1 or L2.
Similarly, the power supply line L for the other scan electrodes 202,.
1 or L2. Note that the scanning electrode drive circuit 3 is also configured in the same manner, and the description is omitted.

The data electrode drive circuit 4 similarly outputs a drive voltage from a push-pull type drive circuit to each of the data electrodes 401, 402,..., And each drive circuit connects to the power supply line L3. , And n-channel FET 41 connected via power supply line L4
, b, 42b,... In addition, each FET
41a, 42a,..., 41b, 42b,. ON / OFF of each FET is controlled by a drive signal given from the logic circuit 40.

The power supply circuit 5 includes a transformer 50, an n-channel FET 51 as switching means, a power supply drive circuit 52 as a switching control section, and the like. The transformer 50 includes a primary coil 50a and three secondary coils 50b, 50c, and 50d. The primary coil 50a is connected to the positive terminal of the battery Ba and an F-source connected to the source.
The secondary coils 50b to 50d are connected between the drain terminal of the ET 51 and the diodes 53a to 53c and the smoothing capacitors 54a to 54c, respectively. One terminal of the secondary coil 50b is connected to the ground terminal, and serves as a DC power supply that outputs the above-described modulation voltage Vm. Secondary coils 50c and 50
d is used as a floating power supply in which none of the terminals is grounded, and is provided as a DC power supply for outputting a control voltage Vc and a DC voltage (Vr-Vm), respectively.

The power supply drive circuit 52 is supplied with power from the battery Ba via the switch control circuit 7, and its control output terminal is connected to the ground terminal via the resistors 55a and 55b, and also via the resistor 55a. It is connected to the gate of FET51. The power supply drive circuit 52 has a modulation voltage V that is an output voltage of the secondary coil 50b of the transformer 50.
m is inputted via a voltage dividing circuit of the resistors 56a and 56b, and a control signal outputted from a control output terminal is adjusted according to the voltage value. In this case, the power supply drive circuit 52 outputs a predetermined DC voltage to each of the secondary coils 50b to 50c by performing PWM control on the FET 51.

The switch control circuit 7 is mainly composed of two transistors 71 and 72. The pnp transistor 71 has an emitter connected to the positive terminal of the battery Ba, a collector connected to the power supply terminal of the power supply drive circuit 52, and a base connected to the collector of the npn transistor 71 via the resistor 73. . Transistor 7
Reference numeral 1 denotes an emitter grounded, and a base is connected to an output terminal of the control circuit 8 via a resistor 74 and a resistor 75
Connected to the ground terminal. Transistor 72
Is turned on when a high-level power-on signal Pon is supplied from the control circuit 8, thereby turning on the transistor 71 and supplying the output of the battery Ba to the power supply drive circuit 52.

The control circuit 8 is provided so as to be driven when the ACC switch 9 is turned on, and the control part for the power supply circuit 5 is configured as shown in FIG. That is, it is mainly composed of the counter 81 and the flip-flop 82. The counter 81 sets the time for applying the erase voltage, and receives a clock signal of 2 Hz.
When the clear terminal CLR goes low and becomes operable, two clocks are counted and a high-level signal is output from the output terminal Q2 and applied to the reset input terminal R of the flip-flop 82. The flip-flop 82
When a high-level signal is applied to the set input terminal S, a high-level signal Pon is output from the output terminal Q. When a high-level signal is applied to the reset input terminal R, a low-level signal is output from the output terminal Q.

The npn-type transistor 83 has an emitter grounded, a collector connected to a power supply terminal via a resistor 84a, and supplied with a control power supply Vd (for example, 5 V). The base of the transistor 83 is connected to A via a resistor 84b.
It is connected to the CC switch 9 and to the ground terminal via the resistor 84c. Further, the collector of the transistor 83 is connected to the clear terminal CLR of the counter 81 and to one input terminal of the AND circuit 86 via the inverter circuit 85.

The output terminal of the inverter circuit 85 is connected to the set input terminal S of the flip-flop 82. A
The ND circuit 86 receives a data signal from a display data output circuit (not shown) to the other input terminal, and outputs a data signal when a high-level signal is supplied to one input terminal.

(1) Description of Display Operation Next, the operation of the present embodiment will be described with reference to FIGS. First, the display operation will be briefly described.
In the display operation, a positive field in which light emission is performed by applying a positive drive voltage to the EL element 100 and a negative field in which light emission is performed by applying a negative drive voltage are alternately set. , Positive and negative fields are performed a total of 480 times per second, or 480 Hz drive frequency.

As shown in FIGS. 5 (j) and 5 (k), in the operation in the positive field, the driving voltage Vr (255 V) is applied from the scanning voltage supply circuit 6 to the power supply line L1.
Is supplied to the power supply line L2 and the modulation voltage Vm (45
V). In the operation of the negative field, the ground voltage (0 V) is applied to the power supply line L1 from the scanning voltage supply circuit 6, and the DC voltage − is applied to the power supply line L2.
(Vr−Vm) (−210 V). The power supply line L3 to the data electrode drive circuit 4 has a modulation voltage V
m (45 V) is applied, and the ground voltage (0 V) is applied to the power supply line L4.

First, the operation of the primary field will be described with reference to the timing chart of FIG. In this field, since the voltage is applied to each of the power supply lines L1 to L4 as described above, the scan electrodes 201, 301, 202, 3
02,... Are set to the modulation voltage Vm as an offset voltage by the action of a parasitic diode provided in association with each FET of the scan electrode driving circuits 2 and 3 (FIG.
(F)). In the positive field, the data electrode driving circuit 4 turns on the FETs 41a, 42a,... And modulates the voltage of each data electrode 401, 402,.
m (see (g) in the figure). Therefore, in this state, the modulation voltage Vm is applied to both electrodes of all the EL elements 111, 112,..., And no voltage is applied between the electrodes (0 V) (see FIG. ) And (i)), and no light is emitted.

Thereafter, the light emission operation is started in the positive field. First, the p-channel FET 21a of the scan electrode control circuit 2 connected to the scan electrode 201 in the first row is turned on (see FIG. 7A), and the potential of the scan electrode 201 is set to the light emission drive voltage Vr (see FIG. (E)). Further, all the FETs at the output stages of the scan electrode driving circuits 2 and 3 connected to the other scan electrodes are turned off, and those scan electrodes 30 are turned off.
,... Are brought into a floating state (see FIG. 3F).

Further, among the data electrodes 401, 402,..., P
The channel FET is turned off and the n-channel FET is turned on.
T is kept on and the n-channel FET is kept off.

As a result, the voltage of the data electrode 401 of the EL element 111 to be made to emit light among the EL elements 111, 112,... Connected to the scanning electrode 201 becomes the ground voltage (see FIG. ), The light emission drive voltage Vr is applied between the electrodes of the EL element 111 (see FIG. 2H), and the light emission operation is performed. Also,
Since the data electrodes 402,... Remain at the modulation voltage Vm, the EL elements 112,... That do not emit light do not emit light because only the modulation voltage Vm is applied between the terminals (see FIG. State is maintained.

Thereafter, the p-channel FET 21 of the scan electrode drive circuit 2 connected to the scan electrode 201 in the first row
a is turned off, and the n-channel FET 21b is turned on (see FIGS. 3A and 3B) to discharge the electric charge accumulated in the EL element 111 of the scan electrode 201. As a result, the voltage of each section returns to the state before the EL element 111 emits light.

Next, a light emitting operation is performed in the same manner for the scanning electrodes 301 in the second row. Now, for example, it is assumed that the EL element 121 does not emit light. First, the p-channel FET 31a of the scan electrode drive circuit 3 is turned on (see FIG. 4C), and the voltage of the scan electrode 301 is set to the light emission drive voltage Vr (see FIG. 4F). Other scan electrode 20
All the FETs connected to 1, 202, 302,... Are turned off, and each scan electrode is brought into a floating state (see FIG. 3E). The data electrodes 401, 402,... Operate the FETs of the data electrode drive circuit 4 corresponding to the EL elements that emit light and the EL elements that do not emit light, respectively (see FIG. 9G).

As a result, the light emission drive voltage Vr is applied between the electrodes of the EL element that emits light, and a voltage (Vr−Vm) equal to or lower than the emission start voltage is applied between the electrodes of the EL element that does not emit light, for example, the EL element 121. (See FIG. (I))
The state where no light is emitted is maintained. Thereafter, the p-channel FET 31a connected to the scan electrode 301 in the second row is turned off, and the n-channel FET 31b is turned on (see FIGS. 3 (c) and 3 (d)). The discharged charge is discharged. Hereinafter, in the same manner, the above operation is repeatedly performed until the last scan electrode is reached, and the light emission operation is sequentially performed for each scan electrode to cause the entire EL display panel 1 to perform the display operation.

Next, the light emitting operation in the negative field will be described. In this case, the power supply line L1 is set to the ground voltage (0 V) by the scanning voltage supply circuit 6 (see FIG. 10 (j)), and the power supply line L2 is set to the DC voltage − (Vr−V).
m) (see (k) in the figure). The power supply lines L3 and L4 are supplied with the same voltage as the positive field. In this state, each EL element 111,
No voltage is applied between the electrodes 121,... And no light is emitted.

The light emitting operation is the same as in the normal field.
The voltage of the scan electrode 201 in the first row is changed to an n-channel FET.
21b is turned on (see FIG. 3 (b)).
r−Vm) (see FIG. 3E). Data electrode 40
The data electrode 401 corresponding to the EL element 111 to emit light among 1, 402,... Turns on the p-channel FET 41a (see (g) in the figure) and sets the modulation voltage Vm. The data electrodes 40 corresponding to the EL elements 121 that do not emit light
2,... Hold the n-channel FETs 42b,.

As a result, the EL element 111 emits light by applying the light emission drive voltage −Vr between the electrodes (FIG. 9 (h)).
) And the EL elements 121,... Are kept in a non-light-emitting state only by applying the DC voltage -Vm (see FIG. 1 (i)). Thereafter, after discharging the accumulated charges in the same manner as in the operation of the positive field, the light-emitting operation in the second and subsequent rows is repeatedly performed, and when the light-emitting operation is completed to the last row, one cycle of the positive and negative fields is performed. When the display operation is completed, and the display operation is to be performed further, this operation is repeatedly performed.

Now, as described above, the EL element 111,
When the light emitting operation of 121,... Is performed, the light emitting drive voltage Vr is applied to the EL element corresponding to the scanning electrode in the selected row, and the direct current voltage (less than the light emission starting voltage) is applied to the EL element not emitting light. (Vr−Vm).
At this time, a DC voltage (Vr−Vm) near the light emission start voltage is applied to the non-emission EL element without emitting light, and as a result, as described above, the polarization charge remaining inside after the voltage application is stopped. Is discharged. That is, in the EL element that emits light in the previous positive or negative field and does not emit light in the next negative or positive field, the internal polarization charge is eliminated in the negative or positive field.

When a voltage (Vr-Vm) near the light-emission starting voltage is applied in a state where polarized charges remain inside, the EL element emits a little light, but performs a display operation as a whole. In the state, both the emission and non-emission E
There is no concern about light emission due to the difference in luminance between the L elements.

(2) Description of Operation for Applying Erase Pulse Voltage Next, the operation for ending the display operation will be described with reference to FIGS. 6 and 7. When the display operation is ended, the display operation is stopped in a state where the internal polarization charges after the light emission operation as described above are not eliminated. Therefore, in this embodiment, the EL element that emits light last ends in a state where the internal polarization charge has been surely eliminated.

First, the power supply operation of the power supply circuit 5 will be described with reference to FIG.
This will be described with reference to FIG. The display operation is terminated by, for example, turning off the ACC switch of the ignition. Then, in the control circuit 8, since the power supply from the battery Ba is stopped (see FIG. 3B), the transistor 83 is turned off, and the collector thereof is connected to the power supply voltage Vc.
Invert to a nearby level, that is, a high level (see FIG. 3). Then, the counter 81 transits from the reset state to the active state, and starts the counting operation. The counter 81 is provided with a clock signal of 2 Hz at a clock terminal CLK.
Since a high-level signal is output from 2, the high-level signal is output after one second has elapsed.

In the flip-flop 82, when the ACC switch 9 is on, a high-level signal is given to the set input terminal S via the inverter circuit 85.
The output terminal Q outputs a high-level signal, that is, a power-on signal Pon. When the ACC switch 9 is turned off, the high-level signal applied to the set input terminal S changes to a low-level signal. As a result, a low-level signal is output from the output terminal Q. That is, the power-on signal Pon is stopped when one second has elapsed since the ACC switch 9 was turned off.

On the other hand, since the collector output of the transistor 83 is input as a low level signal to the AND circuit 86 via the inverter circuit 85, the output of the AND circuit 86 is turned off to block the data signal and output a low level signal. As a result, a non-light emitting data signal is forcibly applied to the data electrode driving circuit 4. Accordingly, the erasing voltage application period T (see FIG. 3C,
During this period, all data signals are output as signals indicating no light emission. Then, the signal indicating non-light emission is used to generate an erase pulse voltage as an erase voltage. The erasing voltage application period T is set based on the reason described later.

Next, the EL during the application period of the erase pulse voltage is
The operation of the display panel 1 will be briefly described with reference to FIG. That is, since the data signals as display data are all signals indicating no light emission, it is the same as controlling to emit no light in the above-described light emission operation, so that each of the scan electrodes 201, 301, 202,. Is selected, all EL elements 111,
112 are voltages near the light emission start voltage (Vr−V
m) (in the case of the positive field) will be given as the erase pulse voltage. In the negative field, a DC voltage − (Vr−Vm) is applied as an erase pulse voltage.

That is, an erasing pulse voltage is applied to the light emitted in the previous field so that the remaining polarization charge is eliminated. At this time, as described above, the erase pulse voltage is a voltage (Vr) near the light emission start voltage.
−Vm), each of the EL elements 111, 112,... However, in this light emitting operation, when the luminance is reduced to 1 cd / m ² or less as the application of the erasing pulse voltage progresses, the light emitting state becomes almost invisible to the user. Further, such a light emitting state is stopped when one second, which is the erase voltage application period T, has elapsed, so that the light emitting state can be ended with almost no uncomfortable feeling.

As a result, all of the EL elements 111, 112,... Constituting the EL display panel 1 can sufficiently eliminate the polarization charges remaining therein, and
When the switch 9 is turned on to start the display operation, erroneous light emission due to the polarization charge can be prevented, and the display operation without a sense of incongruity can be started.

Now, the above-mentioned application period T of the erase pulse voltage
Will be described with reference to FIG. As described above, a number of EL elements constituting the EL display panel 1 are shown in FIG.
In the process of forming a film, the film thickness varies during the film forming process. As a result, the degree of light emission due to the application of the erasing pulse voltage is different, and there is a difference in the time for eliminating the polarization charge. For example, in an EL display panel A, the luminance at which light is emitted rapidly decreases due to the application of the erase pulse voltage and the time tA
(<1 second) has passed becomes 1 cd / ^{m 2} or less, a 1 cd / ^{m 2} or less at another EL display panel B is the time tB (tA <tB <1 second) has elapsed.

However, the reference 1 cd / m
^When the luminance is about ² , almost no human eyes are conscious, and therefore, even when the display operation is stopped in the dark or at night, the user does not feel uncomfortable. Then, when a sufficient erase pulse voltage application operation is performed, the operation is further continued, and one second is set as the erase pulse voltage application period T as in this embodiment. The one second is, for example, set as a time limit that does not cause a human to feel a sense of discomfort statistically. This idea is based on, for example, taking various stop measures when the ACC switch of a car is turned off. This period is also used as a period from when the power is turned off, and by adjusting this time, the erase pulse voltage can be applied with less discomfort.

According to the present embodiment as described above, the application time of the erasing pulse voltage to the plurality of EL elements constituting the EL display panel 1 must be at least 1 cd / luminance of the light emission accompanying the application of the erasing pulse voltage. with respect to the time over which the m ^2, since the set to 1 second is the time in excess of this, E
The polarization charge remaining after the light emitting operation of the L element can be reliably eliminated. Therefore, even if there is a variation in the degree of elimination of the residual polarization charge due to manufacturing variations of the EL element, the user does not feel uncomfortable with the luminance of the light emission caused by the application of the erase pulse voltage while reliably eliminating the polarization charge. You will be able to finish it in a time that you will not remember.

(Second Embodiment) FIG. 9 shows a second embodiment of the present invention.
This embodiment is different from the first embodiment in that the reason for setting the lower limit value of the application period T of the erase pulse voltage is set from a different viewpoint.
That is, in the first embodiment, the period is set to be equal to or longer than the time when the luminance of light emission accompanying the application of the erase pulse voltage is 1 cd / m ² or less. Is set to

As shown in FIG. 9, in the above-described operation of applying the erase pulse voltage, since both the EL element that has just emitted light and the EL element that does not emit light are applied, the erase pulse voltage is applied to both of them. It is intended to make the ratio of the luminance of light emission in a state where the light emission is performed to a certain value or more. The reference of the ratio is set, for example, to a period tp (<1 second) during which the ratio of the low luminance Loff to the high luminance Lon (= Lon / Loff) becomes 0.7 or more. Since this ratio is such that the human eye does not perceive it as a large luminance difference, if the luminance ratio between the two becomes a higher value, that is, if the luminance difference is reduced, then substantially the next This is because it is possible to prevent erroneous light emission from occurring when the light emission operation is started.

The upper limit value of the erase pulse voltage application period T is
As described above, one second is set. If an appropriate period T is set within a range not exceeding one second from the above-described period tp, the second period is obtained.
According to the embodiment, the same operation and effect as described above can be obtained.

(Third Embodiment) FIG. 10 shows a third embodiment of the present invention.
This embodiment is different from the first embodiment in that an EL display panel 1 having a translucent EL element 100a is provided instead of the EL display panel 1. The EL element 100a has a back electrode 1
In place of 06, a transparent electrode 106a formed of the same material as the transparent electrode 101 is provided.

The EL element 100a is formed to have such a degree of transparency that it can be seen through an object behind it. For example, the EL display panel 1 is arranged on the front of another display object in the same manner as a glass plate. . When the EL display panel 1 is not emitting light, the display objects behind it can be seen through, and during the light emitting operation, the EL element 100a emits light to perform light emitting display. At this time, the light emission output is output from the glass substrate 101 to be displayed and also from the opposite transparent electrode 106a.

In this configuration, since the EL display panel 1 is provided in a state where another display object is arranged behind, the upper limit of the erase pulse voltage application period T is different from the first embodiment. The value is set to about 0.5 second instead of 1 second. This is because if the light emitting operation accompanying the application of the erasing pulse voltage lasts for about one second, it is easy to recognize that the glass plate provided on the front of the display is emitting light, and the EL display is displayed in a normal use state. This is because, even when the user does not want the user to recognize that the panel 1 is used, the user may be able to recognize the light emission by applying the erase pulse voltage. Therefore, such a situation is avoided by setting the upper limit value of the period T for applying the erase pulse voltage to about 0.5 seconds.

(Fourth Embodiment) FIGS. 11 and 12 show a fourth embodiment of the present invention. The difference from the first embodiment is that a filter plate 107 is provided on the front surface of the EL display panel 1. This is where the application period T of the erase pulse voltage is set in the case where the configuration is provided. Filter plate 107
Is, for example, using a smoke filter, etc.
The light emitted from the EL display panel 1 is reduced and transmitted.

The brightness when the user views through such a filter plate 107 depends on the EL element 1 which is actually emitting light.
The brightness is lower than 00. Therefore, even during the above-described application period of the erasing pulse voltage, the luminance at which the light is emitted is reduced. Therefore, in consideration of the decrease, when the filter plate 107 is provided, compared with the case where the filter plate 107 is not provided, Since the reduction of the luminance of light emission accompanying the application of the erase pulse voltage is quickened, the application period can be shortened.
Or, in other words, by applying the erasing pulse voltage only during the same application period, the remaining polarization charge can be more reliably eliminated, and the operation can be performed without causing the user to feel uncomfortable.

(Fifth Embodiment) FIG. 13 shows a fifth embodiment of the present invention.
This embodiment is different from the first embodiment in that the pulse voltage conditions for applying the erase pulse voltage are changed and applied. More specifically, the erase pulse voltage is applied. A condition for reducing the luminance of light emission accompanying the application, that is, a dimming condition is set and applied.

In this case, the dimming condition is, for example, 3
There are two ways. First, a method of shortening the pulse width of the erase pulse voltage to shorten the application time per operation,
A method of lowering the applied voltage of the erase pulse voltage,
There is a method of lowering the repetition driving frequency. Here, when these dimming conditions are specifically implemented,
As described above, the data signal is controlled on the scan electrode drive circuits 2 and 3 so as to satisfy these conditions.

For example, when the pulse width of the erase pulse voltage in the first method is reduced, the scan electrodes 201, 301,
FET of the output stage so as to shorten the pulse width of 202, ...
On / off control. When the applied voltage of the erase pulse voltage in the second method is reduced, it is performed by setting the level of the voltage applied to the power supply lines L1 and L2 to be low. When the driving frequency in the third method is lowered, the entire driving operation is performed by driving the above-mentioned 480 Hz under a condition such as a half or a quarter.

By changing the driving conditions in this way, FIG.
As shown in FIG. 3, by applying the erase pulse voltage under the dimming condition as compared with the case where the erase pulse voltage is applied under the same condition as the normal light emitting operation as described in the first embodiment, After applying the erasing pulse voltage as described above, the luminance of light emission decreases in a short time. This allows
Unlike the case where the erasing pulse voltage is applied for a time having the upper limit of one second as described above, the brightness can be reduced even if the erasing pulse voltage is applied for a longer time, so that the user does not feel discomfort. Can be performed in a state in which is eliminated.

When the erase pulse voltage is applied under the dimming condition as described above, the luminance of the light emission accompanying the application can be reduced, but the effect of the erase pulse voltage application is reduced by that much. Become. However, regarding such a point, when the next light emitting operation is started, no light is emitted.
By applying a pulse voltage corresponding to the erase pulse voltage to the L element under the same dimming condition, it becomes possible to prevent erroneous light emission and start driving.

(Sixth Embodiment) FIG. 14 shows a sixth embodiment of the present invention.
This embodiment is different from the first embodiment in that a power supply drive circuit 52a that drives the power supply drive circuit 52 at 5V is used.
A three-terminal regulator 76 is provided in a part from the transistor 71 to the transistor 71 to supply a DC voltage of 5V. The same operation and effect as in the first embodiment can be obtained by such a configuration.

(Other Embodiments) The present invention is not limited to the above embodiment, but can be modified or expanded as follows. In each of the above embodiments, the erase pulse voltage is applied to all the EL elements. Alternatively, the control may be performed such that the erase pulse voltage is selectively applied only to the EL elements that have emitted light. Although the matrix type EL display panel has been described, the present invention can be applied to a segment type EL display panel using a plurality of EL elements.

Although an independent power supply circuit is used,
It is also possible to adopt a configuration that also serves as a power supply circuit mounted on a vehicle. In this case, in the case of a normal in-vehicle system, when a CPU is provided, a period in which the system power is not turned off is provided until the CPU is set to the sleep mode after the IG is turned off. Therefore, the configuration may be such that the erase pulse voltage is applied using the period. This allows
A configuration in which the counter 81 for setting the application period T for applying the erase pulse voltage and the like can be omitted.

The counter 81 is operated by using a clock of 2 Hz. Instead of this, a timer for starting a time counting operation by turning off the ACC switch 9 is provided. For example, when the timer time of 1 second elapses, the power-on signal Pon Can be turned off.

In the case of a vehicle, the switch control circuit 7 is provided in consideration of battery consumption. However, in the case of a consumer product or the like which can always supply power, the switch control circuit 7 is omitted. As a configuration, the power supply input terminal of the power supply drive circuit 52 may be directly connected to the + B terminal of the battery Ba.

[Brief description of the drawings]

FIG. 1 is an overall electrical configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an electrical configuration diagram centering on an EL display panel.

FIG. 3 is an electrical configuration diagram of a control circuit.

FIG. 4 is a schematic sectional view of an EL element.

FIG. 5 is a timing chart showing a state of each part during a light emitting operation.

FIG. 6 is a time chart showing the state of each unit when the display operation is stopped.

FIG. 7 is a diagram corresponding to FIG. 5 when an erase pulse voltage is applied.

FIG. 8 is a diagram showing a light emitting state of an EL element when an erase pulse voltage is applied.

FIG. 9 is a view corresponding to FIG. 8, showing a second embodiment of the present invention;

FIG. 10 is a view corresponding to FIG. 4, showing a third embodiment of the present invention;

FIG. 11 is a view corresponding to FIG. 4, showing a fourth embodiment of the present invention;

FIG. 12 is a diagram corresponding to FIG. 8;

FIG. 13 is a view corresponding to FIG. 8, showing a fifth embodiment of the present invention;

FIG. 14 is an electrical configuration diagram showing a sixth embodiment of the present invention.

FIG. 15 is a diagram showing a relationship between an internal polarization charge and an applied voltage of an EL element showing a conventional example.

[Explanation of symbols]

1 is an EL display panel (display unit), 2 and 3 are scan electrode drive circuits, 4 is a data electrode drive circuit, 5 is a power supply circuit, 6 is a scan voltage supply circuit, 7 is a switch control circuit, 8 is a control circuit, 9 Is an ACC switch, 51 is an n-channel FET
(Switching means), 52 is a power supply drive circuit (switching control unit), 81 is a counter, 82 is a flip-flop, 100, 111, 112,.
, 202, 301, 302,...
Are data electrodes and L1 to L4 are power supply lines.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 3K007 AB00 BA06 BB06 CA01 CB01 DA05 GA00 5C080 AA06 BB05 DD09 EE25 EE28 FF03 FF07 FF12 JJ02 JJ03 JJ04 JJ05 JJ06 5C094 AA01 AA60 BA27 CA19 EA05 EB02 GA03

Claims (17)

[Claims] A display unit having a plurality of EL elements; a driving unit for performing a display operation by emitting light by selectively applying a driving voltage to the EL elements of the display unit based on display data; Power supply means for supplying a driving voltage to the means, and erasing voltage applying means for applying an erasing voltage set near a light emission start voltage to the EL element when the display operation of the display section is stopped, An EL display device, wherein the application time of the erasing voltage by the erasing voltage applying means is set to be equal to or longer than a time at which the emission luminance of the EL element accompanying the erasing voltage application becomes equal to or less than a predetermined luminance. 2. The EL display device according to claim 1, wherein the application time of the erasing voltage by the erasing voltage applying means is equal to or longer than a time when the predetermined brightness is set to about 1 cd / m ² or less. An EL display device characterized in that: 3. A display unit having a plurality of EL elements, a driving unit for performing a display operation by emitting light by selectively applying a driving voltage to the EL elements of the display unit based on display data; Power supply means for supplying a driving voltage to the means, and erasing voltage applying means for applying an erasing voltage set near a light emission start voltage to the EL element when the display operation of the display section is stopped, The application time of the erasing voltage by the erasing voltage applying means was set to be equal to or longer than the time at which the luminance ratio of the low-luminance EL element to the low-luminance EL element that emits light with the application of the erasing voltage was about 0.7. An EL display device. 4. The E according to claim 1, wherein
In the L display device, when a light-transmitting filter member is provided on the front surface of the display unit, the erasing voltage application unit may adjust the erasing voltage of the EL element with the filter member interposed therebetween. EL characterized by setting application time
Display device. 5. The E according to claim 1, wherein
In the L display device, the erasing voltage applying means is configured to apply an erasing voltage by a pulse voltage in the same cycle as the light emitting operation when applying the erasing voltage. apparatus. 6. The EL display device according to claim 5, wherein the erasing voltage applying unit reduces a pulse voltage to a level lower than that in a light emitting operation so as to lower the luminance of the EL element by applying the erasing voltage. The EL display device is configured to perform application control by setting to (1). 7. The EL display device according to claim 6, wherein the erasing voltage applying means sets a dimming condition such that the brightness becomes equal to or lower than the predetermined brightness when a predetermined time has elapsed after the application of the erasing voltage. An EL display device comprising: 8. The EL display device according to claim 6, wherein the erasing voltage applying unit is configured to execute the erasing voltage under the dimming condition with respect to the EL element that is not driven to emit light when the display operation is started next time. An EL display device configured to apply an erasing voltage. 9. The E according to claim 6, wherein
In the L display device, the erasing voltage application unit is configured such that, when the erasing voltage is applied, a pulse width of the erasing voltage is smaller than a pulse width of a driving voltage applied during the light emitting operation. EL display device. 10. The non-light emitting operation according to claim 6, wherein said erasing voltage applying means applies said voltage value during said light emitting operation when said erasing voltage is applied. An EL display device configured to apply an erasing voltage set lower than a voltage for use in the EL display. 11. The EL display device according to claim 6, wherein the erasing voltage application unit, when applying the erasing voltage, has a repetition period longer than a repetition period applied during the light emitting operation. An EL display device configured to apply a pulse voltage. 12. The EL display device according to claim 1, wherein the erasing voltage application unit selectively controls the application of the erasing voltage with respect to the EL element for which a light emitting operation was performed immediately before. E, characterized in that
L display device. 13. The EL display device according to claim 1, wherein a period during which the erasing voltage is applied by the erasing voltage applying means is a time that satisfies the condition and is 1 second or less. An EL display device, wherein the time is set to: 14. The EL display device according to claim 1, wherein, when the display unit is formed of a translucent EL element, the erase voltage is applied by the erase voltage applying unit. The application period is set to a predetermined time within a range not less than a time satisfying the above condition and not more than 0.5 second.
Display device. 15. The EL display device according to claim 1, wherein the power supply circuit includes a switching unit and a switching control unit for driving and controlling the switching unit. An EL display device characterized in that when the control of the application of the erase voltage by the application means is completed, the power supply operation is stopped by turning off the switching means. 16. The EL display device according to claim 1, wherein the power supply circuit includes a switching unit and a switching control unit for controlling the driving of the switching unit, and the erasing voltage application unit includes the erasing voltage. An EL display device, wherein the power supply to the power supply circuit is stopped when the control of the voltage application is completed. 17. The EL display device according to claim 1, wherein the power supply circuit includes switching means supplied from a vehicle-mounted power supply circuit, and a switching control unit for driving and controlling the switching means. An EL display device, wherein the power supply from the vehicle-mounted power supply circuit is stopped when the control of the application of the erasing voltage by the voltage application unit is completed.