JP2001077380A - Solar cell and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a solar cell to be stabilized in output characteristics and improved in performance without lowering its photoelectric conversion efficiency. SOLUTION: A solar cell device is composed of a solar cell formed of a first conductive-type semiconductor substrate 1 and a first second conductive- type region 2 formed on the light receiving surface of the semiconductor substrate 1 and a MOS transistor composed of a second second conductive-type semiconductor region 2' which is formed apart from the first second conductive- type semiconductor region 2 by a prescribed distance confronting it and set equal in potential to the first conductive-type semiconductor substrate 1, an insulating film formed on the surface of the semiconductor substrate 1 between the first second conductive-type region 2 and the second second conductive-type semiconductor region 2', and a gate electrode formed on the surface of the insulating film and set equal in potential to the first or second second conductive-type semiconductor region, 2 and 2'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a method for manufacturing the same, and more particularly, to a solar cell module in which solar cells are connected in series or in parallel, a PN generated in a shaded solar cell. The present invention relates to a solar cell and a method for manufacturing the same, which reduce the destruction of a joint.

[0002]

2. Description of the Related Art In recent years, various types of solar cells, such as crystalline silicon solar cells and amorphous silicon solar cells, have been known as solar cells that can directly use solar energy. 2. Description of the Related Art As a solar power supply system that obtains a desired output current and output voltage by solar energy, a solar cell module in which a plurality of solar cells are connected in series or in parallel is used. Also, many researches for practical use, such as improvement in photoelectric conversion efficiency, productivity, reliability, cost reduction, and multipurpose use of solar cells, are being actively pursued.

However, in a solar cell module used for space, for example, during attitude control of a satellite, sunlight may be partially blocked by a part of the satellite body or a structure such as an antenna. Similarly, in a solar cell module used for the ground, sunlight may be partially blocked by, for example, adhesion of an adjacent building or bird droppings.

[0004] In a solar cell of a solar cell module in which sunlight is partially blocked, a phenomenon occurs in which a voltage generated by another solar cell irradiated with sunlight is applied in a reverse bias direction. . When the voltage applied in the reverse bias direction (reverse bias voltage) exceeds the reverse withstand voltage of the solar cell, the PN junction is destroyed and a large current flows through the solar cell, and as a result, the entire solar cell module This causes the output characteristics to deteriorate.

Therefore, in order to prevent the PN junction of the solar cell from being destroyed by the application of the reverse bias voltage, the solar power supply system has a bypass for bypassing the reverse bias voltage for each individual solar cell or solar cell module. A solar cell with an external diode is used.

According to the description of Japanese Patent Application Laid-Open No. 3-269568, there is proposed a solar cell in which a Zener diode for bypassing a reverse bias voltage applied to a shaded solar cell is integrated. .

[0007]

However, a solar cell module comprising a solar cell with an external bypass diode is mounted on a substrate by mounting an externally mounted diode part and a solar cell formed on a substrate due to an increase in the number of manufacturing steps. There have been problems such as a decrease in density and an increase in manufacturing cost. Further, the solar cell described in Japanese Patent Application Laid-Open No. 3-269568 has a PN formed by a high-concentration impurity diffusion layer.
Since the Zener diode with the junction is integrated, the current characteristics when bypassing the reverse bias voltage become uneven due to the variation of the impurity diffusion layer, and as a result, the stabilization of the output characteristics of the solar cell module is hindered. Becomes

The present invention has been made in view of the above circumstances. For example, a reverse bias voltage applied to a shaded solar cell is bypassed through a MOS transistor having uniform current characteristics. This provides a solar cell module that contributes to stabilization of output characteristics and high performance of the solar cell without reducing the photoelectric conversion efficiency of the solar cell, and a method of manufacturing the solar cell module.

[0009]

According to the present invention, there is provided a solar cell comprising a semiconductor substrate of a first conductivity type and a first second conductivity type region formed on a light receiving surface side thereof, and a first second conductivity type semiconductor substrate. A second second-conductivity-type semiconductor region, a first second-conductivity-type semiconductor region, and a second second-conductivity-type semiconductor region which are opposed to the semiconductor region at a predetermined distance and formed to have the same potential as the potential of the first-conductivity-type semiconductor substrate Insulating film formed on the surface of the first conductive type semiconductor substrate located between the second conductive type semiconductor regions, and the first film on the surface of the insulating film.
Alternatively, the solar cell comprises a MOS transistor having a gate electrode formed to have the same potential as the potential of the second second conductivity type semiconductor region.

[0010] According to the present invention, the solar cell is MOS
By integrating (Metal-Oxide-Semiconductor) type transistors, the reverse bias voltage applied to the shaded solar cells can be bypassed through MOS type transistors having uniform current characteristics. The output characteristics of the solar cell can be stabilized and its performance can be improved without reducing the photoelectric conversion efficiency of the battery cell. Further, the manufacturing process of the solar cell and the manufacturing process of the MOS transistor are basically the same, and the manufacturing process is not changed. Therefore, it is possible to prevent a decrease in the productivity of the solar cell.

According to another aspect of the present invention, there is provided a method of manufacturing a solar cell including a solar cell and a MOS transistor, wherein the first conductive type semiconductor substrate and a first conductive layer formed on a light receiving surface thereof are formed. A plurality of solar cells formed of the second conductivity type region are formed so as to face the first second conductivity type semiconductor region at a predetermined distance and have the same potential as the potential of the first conductivity type semiconductor substrate. An insulating film formed on a surface of a first conductive type semiconductor substrate located between a first second conductive type semiconductor region and a second second conductive type semiconductor region; The first or second second
A method for manufacturing a solar cell is provided, wherein a MOS transistor including a gate electrode formed to have the same potential as the potential of the conductive semiconductor region is formed.

The photovoltaic cell includes a light-receiving surface formed in a non-reflective shape of the first second conductivity type semiconductor region, and the MOS transistor is formed of the first second conductivity type semiconductor region. A configuration including a partially flat region may be adopted. According to this configuration, it is possible to increase the amount of light incident on the light receiving surface of the photovoltaic cell and perform high-output photoelectric conversion.

The insulating film may be formed on the surface of the first conductivity type semiconductor substrate located between the first second conductivity type semiconductor region and the second second conductivity type semiconductor region by a CVD method. According to this configuration, an insulating film having a uniform thickness and quality can be formed.

A structure in which the gate electrode is formed on the surface of the insulating film by a CVD method using a transparent conductive electrode wiring material made of polycrystalline silicon, amorphous silicon and a transparent impurity additive showing conductivity. It may be. According to this configuration, it is possible to increase the amount of light incident on the light receiving surface of the photovoltaic cell and perform high-output photoelectric conversion.

The current path of the solar cell may be formed on the surface of the insulating film by using a conductive electrode wiring material. According to this configuration, the reverse bias voltage applied to the solar cell can be bypassed to the current path.

The first and second second conductivity type semiconductor regions may be formed in a comb shape having a predetermined length facing each other. According to this configuration, the effective length of the portion where the channel current flows can be increased, so that the reverse bypass current flows sufficiently and the rise of the reverse bias voltage can be effectively suppressed.

[0017] The MOS transistor may be formed continuously in a peripheral portion of the solar cell. According to this configuration, the light receiving surface of the solar battery cell can be enlarged to increase the photoelectric output of the solar battery cell.

[0018] The MOS transistor may be formed at an arbitrary position of the solar cell. According to this configuration, the light receiving surface of the solar cell can be enlarged to increase the photoelectric output of the solar cell.
The S-type transistor can be effectively operated on average.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. The present invention is not limited by this.

FIG. 1 is a diagram showing a planar structure of a solar cell according to one embodiment of the present invention. In FIG. 1, 1 is a P-type silicon substrate (first conductivity type semiconductor substrate), and 2 is a first N ⁺ type diffusion region (first second conductivity type semiconductor region) formed on the P-type silicon substrate 1. , 2 'and the second N ⁺ -type diffusion region (second second conductivity type semiconductor region) formed on a P-type silicon substrate 1, 3' P ⁺ -type formed on the P-type silicon substrate 1 The diffusion region (contact region) 5 is a P region located between the first N ⁺ type diffusion region 2 and the second N ⁺ type diffusion region 2 ′.
An oxide film (insulating film) formed on the surface of the silicon substrate 1, 7 is an N-side electrode serving as a gate electrode of an NchMOS transistor, 7 'is an N-side electrode, and 22' is electrically connected to the N-side electrode 7 '. 3 shows a contact window for connection.

The solar cell comprises a P-type silicon substrate 1 (first conductivity type semiconductor substrate) and a first N ⁺ type diffusion region 2 (first conductivity type semiconductor substrate).
(The second conductive type semiconductor region). Nch
In the MOS transistor, the first N ⁺ type diffusion region 2 is a drain region, the second N ⁺ type diffusion region 2 ′ is a source region,
The N-side electrode 7 is configured as a gate electrode. Further, the potential of the gate electrode is formed to be the same as the potential of the drain region.

FIG. 2 is a diagram showing a sectional structure of a solar cell according to an embodiment of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. 1 is a P-type silicon substrate (first
A conductive type semiconductor substrate), a first N ⁺ type diffusion region (first second type) serving as a light receiving surface formed on the P type silicon substrate 1;
A conductive type semiconductor region), 2 ′ is a second N ⁺ type diffusion region (second second conductive type semiconductor region) formed on the P-type silicon substrate 1, and 3 is formed on the back surface of the P-type silicon substrate P ⁺ -type diffusion region 3 ′ is a P ⁺ -type diffusion region formed on P-type silicon substrate 1, and 4 is an oxide film (insulating film) formed partially on the back surface of P ⁺ -type diffusion region 3. , 5 are P located between the first N ⁺ type diffusion region 2 and the second N ⁺ type diffusion region 2 ′.
Oxide film (insulating film) formed on the surface of the silicon substrate 1; 6, a thermal oxide film formed on the first N ⁺ -type diffusion region 2 and the second N ⁺ -type diffusion region 2 '; 7 'is an N-side electrode (current path), 8 is a P-side electrode formed in the P ⁺ type diffusion region 3, 9 is an antireflection film,
Reference numeral 2 'denotes a contact window for electrically connecting to the N-side electrode 7'.

FIG. 2A shows a sectional structure of FIG. 1A- (A '), and FIG. 2B shows a sectional structure of FIG.
The cross-sectional structure of (B ′) is shown. As in FIG. 1, the solar battery cell has a P-type silicon substrate 1 and a first N ⁺ -type diffusion region 2 as a basic configuration, and the P-type silicon substrate 1 and the first N ⁺ -type diffusion region 2 have a PN junction. ing. The NchMOS type transistor has a first N ⁺ type diffusion region 2 as a drain region and a second N ⁺ type
^{The +} type diffusion region 2 ′ is configured as a source region, and the N-side electrode 7 is configured as a gate electrode.

FIG. 3 is a diagram showing a basic configuration of a solar cell according to the present invention and an equivalent circuit thereof. FIG. 3A shows a basic configuration of a solar cell. As shown in FIG. 3A, the solar battery cell has a basic configuration including a P-type silicon substrate 1 and a first N ⁺ -type diffusion region 2 serving as a light receiving surface, and a P-type silicon substrate 1 and a first N ^{+ -type.} The mold diffusion region 2 has a PN junction. Similarly to FIGS. 1 and 2, the NchMOS transistor has a first N ⁺ -type diffusion region 2 as a drain region, a second N ⁺ -type diffusion region 2 ′ as a source region, and an N-side electrode 7 as a gate electrode G. Make up. The gate electrode G is fixed at the potential of the drain region D, and the source region S is fixed at the potential of the P-type silicon substrate.

FIG. 3B shows an equivalent circuit of the solar cell.
As shown in FIG. 3B, an NchMO is applied to the solar cell SC.
S-type transistors MT are connected in parallel, and the source region S
Is connected to the P-type silicon substrate 1 of the solar cell SC,
The drain region D is connected to the N ⁺ type diffusion region 2 of the solar cell SC, and the gate electrode G is connected to the drain region D.

FIG. 4 is a graph showing the Ir-Vr characteristics of a MOS transistor. Vr indicates an input voltage of the gate electrode, Ir indicates an output current (channel current) with respect to the input voltage Vr, and Vth indicates a threshold voltage at which the MOS transistor starts an ON operation.

For example, the solar cell S shown in FIG.
The light receiving part of C enters the shade, and the first N ⁺Positive to mold diffusion region 2
Potential, a reverse bias voltage that becomes a negative potential on the P-type silicon substrate 1.
It is assumed that the pressure Vr is applied. At this time, the gate electrode G
The potential becomes higher than that of the P-type silicon substrate 1 and the MOS transistor
Transistor threshold voltage Vth (P-type silicon under the gate electrode)
If the voltage exceeds the surface inversion voltage of the substrate 1, the drain region 2
Channel on the surface of the P-type silicon substrate between
Layer is formed, and the channel current shown in the Ir-Vr characteristic of FIG.
Ir flows. That is, the reverse bias current shown in FIG.
Ir flows between the drain region D and the source region S
Further suppress the rise of the reverse bias voltage Vr, the solar cell
Of the PN junction can be prevented.

FIG. 5 is a diagram showing a method of manufacturing a solar cell according to one embodiment of the present invention. In FIG. 5A, in the step of FIG. 5A, a thermal oxide film (mask) of, for example, 200 to 400 nm is formed on the surface of the P-type silicon substrate 1 having a desired thickness in an oxidizing atmosphere. A thermal oxide film is selectively removed by a well-known photolithography technique to form a substrate contact region 3 'which is a high-concentration P ⁺ type diffusion region on a main surface for forming an N ⁺ type diffusion region as a light receiving surface. I do. At this time, the thermal oxide film on the back surface of the P-type silicon substrate 1 is also removed at the same time.

In the step of FIG. 5B, high concentration P ⁺ -type diffusion regions 3 'and 3 of about 1 × 10 ²⁰ cm ^-3 are formed on both surfaces of the P-type silicon substrate 1 by using BBr ₃ or the like. FIG.
Thermal oxide film formed in the step (a) is used as a mask to form the P ⁺ -type diffusion region is entirely removed after the formation of the P ⁺ -type diffusion region.

In the step of FIG. 5C, a P-type silicon substrate
CVD method (Chemical Vapor Deposition:
Oxide film 4 having a thickness of about 400 nm by chemical vapor deposition or the like.
5 is formed, and N on the light receiving surface side is formed.⁺Form mold diffusion region
The oxide film 5 in the region for the
POCl after removal using surgical and etching techniques _Three
1 × 10¹⁹cm^-3First N of degree⁺Diffusion area
2 and the second N⁺A mold diffusion region 2 'is formed.

In the step of FIG. 5D, the N ⁺ type diffusion region 2
After forming a thin thermal oxide film 6 of about 20 nm on the surface of the P-type silicon substrate 1, a contact window 21 for electrically connecting to the P-side electrode 8 is formed on the back surface of the P-type silicon substrate 1, and a light-receiving surface is further formed. A contact window 22 for electrically connecting to the N-side electrode 7 is formed on the surface of the N ⁺ type diffusion region 2 on the side.

Further, as shown in FIG.⁺Diffusion area
A capacitor for electrically connecting to the N-side electrode 7 'on the surface of 2'
A tact window 22 'is formed. Thereafter, using well-known technology
An N-side electrode 7 and a P-side electrode 8 are formed. At this time, N side
The electrode 7 has a first N⁺Diffusion area 2
Of the second N-type diffusion region 2 ′.
You. Furthermore, N⁺Diffusion region 2 'and high-concentration P ⁺Mold diffusion
An N-side electrode 7 'covering the region 3 # is formed. Also,
Then, an antireflection film 9 is formed on the light receiving surface side, and
NchMOS type transistor bypassing reverse bias voltage
To obtain the final shape of the solar cell with integrated data.

As shown in FIG. 3A, the light receiving surface, which is a large part of the first N ⁺ type diffusion region 2, is made non-reflective,
By making the region of the MOS transistor flat, the amount of light incident on the light receiving surface of the solar cell can be increased, and a solar cell capable of high-power photoelectric conversion can be manufactured.

As shown in FIG. 2, a portion of the first N ⁺ type diffusion region 2 is formed by using a transparent conductive electrode wiring material made of polycrystalline silicon, amorphous silicon and a conductive impurity additive. N-side electrode 7 (gate electrode) covering only the top
It may be formed by a method. With this configuration, the first N ⁺
Light reaches the light receiving surface of the mold diffusion region 2 and high-power photoelectric conversion is enabled.

The current path of the solar cell may be formed on the surface of the insulating film 5 by using the conductive electrode wiring material. Insulating film 5
The upper current path may be another conductive electrode wiring material. With this configuration, the reverse bias current can be bypassed to the current path. This current path functions as an N-side electrode 7 '(collector electrode) for collecting the photovoltaic power of the solar cell.

FIG. 6 is a diagram showing a plan structure of a solar cell according to another embodiment of the present invention. 6, the same components as those in FIG. 1 are denoted by the same reference numerals. Also, as shown in FIG.
The first and second N ⁺ -type diffusion regions may be formed in a comb shape facing each other. With this configuration, the effective length of the portion where the channel current flows can be increased, the reverse bypass current Ir sufficiently flows, and the rise of the reverse bias voltage Vr can be effectively suppressed.

FIG. 7 is a diagram showing a layout example of a MOS transistor region with respect to the light receiving region of the solar cell of the present invention. As shown in FIG. 7A, the MOS transistor region 1 is continuously formed around the light receiving region 10 of the solar cell.
By forming 1, the effective light receiving area of the solar cell can be made large, and the output of the solar cell increases.

As shown in FIG. 7B, the MOS transistor region 11 can be formed discontinuously at an arbitrary position in the light receiving region of the solar cell. As a result, the reverse bias voltage bypass function works at many points,
From the shaded cell portion to the MOS transistor region 1
Since the distance to 1 is not long, the PN junction is less likely to break down.

[0039]

According to the present invention, MOS cells are used in solar cells.
The integrated reverse type transistor enables the reverse bias voltage applied to the shaded solar cell to be bypassed via the MOS type transistor having uniform current characteristics, thereby improving the photoelectric conversion efficiency of the solar cell. Without reducing, the output characteristics of the solar cell can be stabilized and the performance can be improved. Further, the manufacturing process of the solar cell and the manufacturing process of the MOS transistor are basically the same, and the manufacturing process is not changed. Therefore, it is possible to prevent a decrease in the productivity of the solar cell.

[Brief description of the drawings]

FIG. 1 is a diagram showing a planar structure of a solar cell according to one embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional structure of a solar cell according to an embodiment of the present invention.

FIG. 3 is a diagram showing a basic configuration of a solar cell of the present invention and an equivalent circuit thereof.

FIG. 4 is a diagram showing Ir-Vr characteristics of a MOS transistor.

FIG. 5 is a diagram showing a method for manufacturing a solar cell according to one embodiment of the present invention.

FIG. 6 is a diagram showing a planar structure of a solar cell according to another embodiment of the present invention.

FIG. 7 shows an MO for a light receiving region of a solar cell according to the present invention.
FIG. 4 is a diagram illustrating a layout example of an S-type transistor region.

[Description of each part]

Reference Signs List 1 P-type silicon substrate (first conductivity type semiconductor substrate) 2 First N ⁺ -type diffusion region (first second conductivity-type semiconductor region) 2 ′ Second N ⁺ -type diffusion region (second second conductivity type) Type semiconductor region) 3 P ⁺ type diffusion region 3 ′ P ⁺ type diffusion region 4 oxide film (insulating film) 5 oxide film (insulating film) 6 thermal oxide film 7 N-side electrode (gate electrode) 7 ′ N-side electrode (current Path) 8 P-side electrode 9 anti-reflection film 10 light receiving region of solar cell 11 MOS transistor region 21 contact window 22 contact window 22 ′ contact window

Claims (9)

[Claims] 1. A photovoltaic cell comprising a first conductivity type semiconductor substrate and a first second conductivity type region formed on a light-receiving surface side thereof, facing a first second conductivity type semiconductor region at a predetermined distance. And a second second conductivity type semiconductor region formed so as to have the same potential as the potential of the first conductivity type semiconductor substrate.
An insulating film formed on a surface of a first conductive type semiconductor substrate located between a conductive type semiconductor region and a second second conductive type semiconductor region, and a first or second second conductive type semiconductor on a surface of the insulating film. A MOS transistor comprising a gate electrode formed to have the same potential as the potential of the region. 2. The photovoltaic cell includes a non-reflective light receiving surface of the first second conductivity type semiconductor region, and the MOS transistor includes a first second conductivity type semiconductor region. The solar cell according to claim 1, wherein the solar cell includes a partially flat region. 3. The method according to claim 1, wherein the insulating film is formed by a first second process by a CVD method.
2. The solar cell according to claim 1, wherein the solar cell is formed on a surface of the first conductivity type semiconductor substrate located between the conductivity type semiconductor region and the second second conductivity type semiconductor region. 4. The gate electrode is formed on the surface of the insulating film by CVD using a transparent conductive electrode wiring material made of polycrystalline silicon, amorphous silicon, and an impurity additive showing conductivity.
The solar cell according to claim 1, wherein the solar cell is formed by a method. 5. The solar cell according to claim 1, wherein a current path of the solar cell is formed on a surface of the insulating film using a conductive electrode wiring material. 6. The solar cell according to claim 1, wherein said first and second second conductivity type semiconductor regions are formed in a comb shape having a predetermined length facing each other. 7. The solar cell according to claim 1, wherein the MOS transistor is formed continuously around the solar cell. 8. The solar cell according to claim 1, wherein the MOS transistor is formed at an arbitrary position of the solar cell. 9. A method for manufacturing a solar cell comprising a solar cell and a MOS transistor, comprising: a solar cell comprising a first conductive type semiconductor substrate and a first second conductive type region formed on a light receiving surface side thereof. A battery cell is formed, a second second conductive type semiconductor region is opposed to the first second conductive type semiconductor region at a predetermined distance and formed to have the same potential as the potential of the first conductive type semiconductor substrate.
A conductive semiconductor region, a first second conductive semiconductor region and a second conductive semiconductor region.
An insulating film formed on the surface of the first conductive type semiconductor substrate located between the second conductive type semiconductor regions and the same potential as the potential of the first or second second conductive type semiconductor region on the surface of the insulating film. A method for manufacturing a solar cell, comprising forming a MOS transistor comprising a gate electrode formed as follows.