JP2001077115A - Method and device for designing dummy pattern, semiconductor device comprising dummy pattern, and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design method for a dummy pattern which is applicable to an IC where no automatic arrangement/wiring is used and a wiring data which is corrected manually. SOLUTION: This is a design method for dummy patterns 21, 24, and 26 which is inserted in wiring patterns 11-14 on a reticule. A plurality of basic dummy patterns comprising light-shielding data are arranged at a prescribed interval in a first chip formation region, and then the translucent data and the light-shielding data are inverted. After the wiring pattern, comprising light- shielding data, is arranged in a second chip-forming region, the wiring pattern is enlarged in both the X and Y-directions by at least corresponding to a minimum space of a design rule. By having the translucent data and light-shielding data in the first chip-forming region synthesized with those of the second chip- forming region, and then they are inverted. Such light-shielding data being less than minimum design rule width is deleted, and then the translucent data and light-shielding data are synthesized with those of the wiring pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a dummy pattern applicable to an IC that does not use automatic placement and routing and wiring data that has been manually corrected, a semiconductor device having a dummy pattern, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 12 is a plan view for explaining a conventional dummy pattern designing method. A method for designing the dummy pattern is disclosed in Japanese Patent Application Laid-Open No. 7-153844.

That is, if there is a virtual grid 101 for automatic placement and routing that is not used for a sparse wiring 102 in a peripheral portion of a chip for which automatic placement and routing has been completed, dummy wiring patterns 103 and 104 are generated there. . The signal wiring 102 is connected to a transistor, a passive element, or the like (not shown), and is a wiring for transmitting and receiving signals. Dummy wiring 103 is GND (ground), dummy wiring 1
04 is connected to the power supply VDD at a portion not shown. These dummy wirings 103 and 104 are arranged on a vertical and horizontal grid. Also, the dummy wirings 103 and 10
No. 4 is generated by using a CAD tool for the automatic layout result data.

[0004]

By the way, in the above-described conventional dummy pattern designing method, the virtual grid 10
It can be applied only to products using automatic placement and routing represented by a gate array in which wiring is regularly formed on the device. Therefore, the conventional dummy pattern design method cannot be applied to a custom IC that does not use the automatic placement and routing or wiring data that has been manually corrected.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of designing a dummy pattern applicable to an IC that does not use automatic placement and routing and wiring data that has been manually corrected. An object of the present invention is to provide a semiconductor device having a pattern and a method of manufacturing the same.

[0006]

In order to solve the above-mentioned problems, a method of designing a dummy pattern according to the present invention is a method of designing a dummy pattern to be inserted into a wiring pattern on a reticle, comprising a light transmission data. A first step of arranging a plurality of basic dummy patterns each formed of a predetermined shape of light-shielded data at a predetermined interval in the first chip formation area, and inverting the light-transmitted data and the light-shielded data in the first chip formation area; A second step of arranging a wiring pattern made of light-shielded data in a second chip formation area made of light-transmitting data; and a step of arranging the wiring pattern in the second chip formation area in the X direction. A fourth step of enlarging at least the minimum space of the design rule in the Y direction, and a light transmission data in the first chip formation region after being inverted in the second step. And combining the light-shielded data with the light-transmitted data and the light-shielded data in the second chip-formed area after the enlargement in the fourth step, thereby creating a third chip-formed area including the light-transmitted data and the light-shielded data. A fifth step, a sixth step of inverting the light transmission data and the light shielding data in the third chip formation area, and a seventh step of deleting the light shielding data less than the minimum line width of the design rule in the third chip formation area. And the light-transmitting data and light-shielding data in the third chip formation area after being deleted in the seventh step, and the light-transmitting data and light-shielding data in the second chip formation area after being disposed in the third step. An eighth step of forming a fourth chip formation region including the light-transmitting data and the light-shielded data by combining Ninth step of enlarging the pattern consisting of at least the minimum space of the design rule in both the X direction and the Y direction, and inverting the light-transmitted data and the light-shielded data in the fourth chip formation region expanded by the ninth step The tenth step, and the light transmission data and the light shielding data in the fourth chip formation region after the inversion in the tenth step are converted into the light transmission data and the light shielding in the fourth chip formation region created in the eighth step. An eleventh step of creating a fifth chip formation region including light-transmitting data and light-shielding data by combining the data with data;
It is characterized by having.

In the above-described dummy pattern designing method, mask pattern data having a dummy pattern can be automatically created only by logic synthesis of data even for a custom IC that does not use automatic placement and routing or wiring data that has been manually corrected. it can. Therefore, unlike the conventional dummy pattern designing method, the present invention is not applied only to a product using automatic placement and routing represented by a gate array in which wiring is regularly formed on a virtual grid.

An apparatus for designing a dummy pattern according to the present invention is an apparatus for designing a dummy pattern to be inserted into a wiring pattern on a reticle. Means for inverting light-transmitted data and light-shielded data in a first chip formation region after arranging a plurality of basic dummy patterns each consisting of a plurality of basic dummy patterns, and forming a second chip formed of light-transmitted data After arranging a wiring pattern made of light-shielded data in the area, expanding the wiring pattern in the second chip formation area by at least the minimum space of the design rule in both the X direction and the Y direction; The second chip after the light transmitting data and the light shielding data in the first chip forming area after being inverted by the means are enlarged by the second means. A third means for creating a third chip forming area composed of the light transmitting data and the light shielding data by combining the light transmitting data and the light shielding data in the formation area, and a light transmitting data and a light shielding in the third chip forming area. After inverting the data and deleting the light-shielded data less than the minimum line width of the design rule, the light-transmitted data and the light-shielded data in the third chip formation region are replaced by the second means after the wiring pattern is arranged by the second means. A fourth means for creating a fourth chip forming area composed of the light transmitting data and the light shielding data by combining with the light transmitting data and the light shielding data in the chip forming area, and a light shielding data in the fourth chip forming area. After enlarging the pattern in the X direction and the Y direction by at least the minimum space of the design rule, the light transmission data and By inverting the optical data and synthesizing the light-transmitted data and the light-shielded data with the light-transmitted data and the light-shielded data in the fourth chip formation region created by the fourth means, the fourth data composed of the light-transmitted data and the light-shielded data is obtained. And a fifth means for forming five chip formation regions.

A semiconductor device according to the present invention includes a wiring pattern formed on a first insulating film, a dummy pattern formed on the first insulating film, the wiring pattern, the dummy pattern, and the first pattern. A second insulating film formed on the insulating film, wherein the dummy pattern is formed in a first chip forming region made of light-transmitting data.
A plurality of basic dummy patterns each including light-shielded data having a predetermined shape are arranged at a predetermined interval from each other, and the light-transmitted data and the light-shielded data are inverted in the first chip-formed area, and the second chip-formed area formed from light-transmitted data is formed. A wiring pattern made of light-shielded data is arranged in the second chip forming region, and the wiring pattern is enlarged in the X direction and the Y direction by at least the minimum space of the design rule. By combining the light transmitting data and the light shielding data in the formation region with the light transmitting data and the light shielding data in the enlarged second chip forming region, the third chip forming region including the light transmitting data and the light shielding data is formed. Then, the light transmission data and the light shielding data are inverted in the third chip formation region, and the design rule is formed in the third chip formation region. And the light transmission data and light shielding data in the third chip formation region after the deletion are replaced with the light transmission data in the second chip formation region after the wiring pattern is arranged. Then, a fourth chip formation region including the light transmission data and the light shielding data is created by combining the light transmission data and the light shielding data, and the pattern including the light shielding data is defined in the fourth chip formation region in the X direction and the Y direction according to the design rule. The light transmission data and the light shielding data are inverted in the fourth chip formation region after the enlargement by the minimum space or more, and the light transmission data and the light shielding data in the fourth chip formation region after the inversion are converted into the fourth chip formation region. By combining the light transmission data and the light shielding data in the chip formation region of No. 4 with the fifth chip type composed of the light transmission data and the light shielding data. Characterized in that it is a pattern consisting of obtained light-shielding data by creating a region.

[0010] A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a step of exposing a resist film using a reticle having a wiring pattern and a dummy pattern. A plurality of basic dummy patterns each including a predetermined shape of light-shielded data are arranged at predetermined intervals in a first chip-forming region made of, and the light-transmitted data and the light-shielded data are inverted in the first chip-formed region. A wiring pattern made of light-shielded data is arranged in a second chip formation region made of optical data, and the wiring pattern is enlarged in the second chip formation region by at least the minimum space of the design rule in both the X and Y directions, The light-transmitting data and the light-shielding data in the first chip formation area after the inversion are converted into the second chip after the enlargement. A third chip forming region including the light transmitting data and the light shielding data is created by combining the light transmitting data and the light shielding data in the formation region, and the light transmitting data and the light shielding data are inverted in the third chip forming region; In the third chip formation area, light-shielded data less than the minimum line width of the design rule is deleted, and the light-transmitted data and light-shielded data in the third chip formation area after the deletion are replaced with the light-shielded data after the wiring pattern is arranged. The fourth chip forming region including the light transmitting data and the light shielding data is created by combining the light transmitting data and the light shielding data in the second chip forming region, and the pattern including the light shielding data is formed in the fourth chip forming region. Both the X direction and the Y direction are enlarged by the minimum space of the design rule, and in the fourth chip formation region after the enlargement, The optical data and the light-shielded data are inverted, and the light-transmitted data and the light-shielded data in the fourth chip formation area after the inversion are combined with the light-transmitted data and the light-shielded data in the fourth chip formation area, thereby obtaining the light-transmitted data. Fifth data and light-shielded data
The pattern is characterized by being a pattern composed of light-shielded data obtained by creating the chip formation region of FIG.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 11 are plan views for explaining a method of designing a dummy pattern according to the first embodiment of the present invention.

First, as shown in FIG. 1, a first chip formation region 10 made of light-transmitting data is prepared, and a plurality of basic dummy patterns 1 made of light-shielded data are placed on this chip formation region 10 in a space. Sd is placed apart. The basic dummy pattern 1 is a rectangle having a size of Ld × Ld. The space Sd is preferably a space that is equal to or larger than the minimum space of the design rule.

Next, the first chip forming region 1 shown in FIG.
At 0, the light transmission data and the light shielding data are inverted. As a result, as shown in FIG.
In the area 3, a region 3 other than the basic dummy pattern 1 'made of light-transmitting data and the basic dummy pattern made of light-shielded data is formed.

Thereafter, as shown in FIG. 3, a second chip forming area 30 including light transmission data is prepared, and the first to fourth real wiring patterns 11 to 11 including light shielding data are provided in the chip forming area 30. 14 is arranged. The first to fourth actual wiring patterns 11 to 14 have the minimum design rule Line / Space =
It is composed of La / Sa. The distance X1 between the second actual wiring pattern 12 and the third actual wiring pattern 13 is
It is narrower than 2Sa + 2La + Sd. However, Sa
Is the minimum space width of the design rule, and La is the minimum line width of the design rule.

Next, the second chip formation region 3 shown in FIG.
0, the first to fourth real wiring patterns 11 to 14 formed of the light-shielded data are replaced with the minimum space S of the design rule.
Both the X and Y directions are enlarged by a. Thereby, as shown in FIG. 4, the first to fourth enlarged wiring patterns 11 'to 14' are formed in the second chip formation region 30. At this time, the distance X2 between the second enlarged real wiring pattern 12 'and the third real wiring pattern 13' is smaller than 2La + Sd.

Thereafter, the light transmitting data and the light shielding data in the first chip forming region 10 shown in FIG. 2 are added to the light transmitting data and the light shielding data in the second chip forming region 30 shown in FIG. As a result, as shown in FIG. 5, a third chip formation region 40 including the regions 1 ′ to 4 ′ including the light-transmitting data and the region 20 including the light-shielding data is created. In other words, when an area composed of light-transmitting data and an area composed of light-shielded data are overlapped by addition and synthesis, the area becomes an area composed of light-shielded data. When the areas of the translucent data overlap each other, the area becomes the area of the translucent data.
The areas 2 'and 3' of the areas 1 'to 4' formed of the translucent data have a narrow width. The width X3 of the region 2 'and the width X4 of the region 3' are both smaller than the minimum line width La of the design rule. Since the distance between the region 2 'and the region 3' is Sd, the entire width X5 of the region 2 'and the region 3' is smaller than 2La + Sd.

Next, the third chip formation region 4 shown in FIG.
At 0, the light transmission data and the light shielding data are inverted. Thereby, as shown in FIG. 6, the third chip formation region 40 is formed.
Are formed with a region 19 composed of light-transmitting data and patterns 21 to 24 composed of light-shielding data.

Thereafter, of the patterns 21 to 24 formed of the light-shielded data in the third chip formation region 40 shown in FIG. 6, the patterns smaller than the minimum line width La of the design rule are deleted. As a result, the patterns 22 and 23 are deleted, and the final dummy patterns 21 and 24 including the light-shielded data are formed in the third chip formation region 40 as shown in FIG.

Thereafter, the final dummy pattern 2 shown in FIG.
The light transmitting data and the light shielding data in the second chip forming region 30 having the actual wiring patterns 11 to 14 shown in FIG. I do. As a result, as shown in FIG. 8, in the fourth chip formation region 50, mask pattern data including the dummy patterns 21 and 24 and the first to fourth real wiring patterns 11 to 14 made of light shielding data are created. . At this time, there is no dummy pattern between the second real wiring pattern 12 and the third real wiring pattern 13, and the interval X1 is smaller than 2Sa + 2La + Sd as described above. Therefore, the maximum space width X1 in the fourth chip formation region 50 including the dummy patterns 21 and 24 is 2Sa + 2La +
Sd may be reached.

Next, the fourth chip formation region 5 shown in FIG.
At 0, the first to fourth real wiring patterns 11 to 14 and the dummy patterns 21 and 24, which are formed of light-shielded data, are enlarged in the X and Y directions by the minimum space Sa of the design rule. As a result, as shown in FIG. 9, a fourth chip formation region 50 having enlarged patterns 21 'and 24' made of light-shielded data is formed. At this time, the distance X6 between the enlarged patterns 21 'and 24' is 2La.
It becomes narrower than + Sd.

Thereafter, the light transmission data and the light shielding data are inverted in the fourth chip formation region 50 shown in FIG. As a result, as shown in FIG. 10, in the fourth chip formation region 40, the patterns 22 'and 23' made of the translucent data are provided.
And a pattern 26 composed of light-shielded data. At this time, the width X6 of the pattern 26 is smaller than 2La + Sd.

Next, of the patterns formed of the light-shielded data in the fourth chip formation region 50 shown in FIG. 10, a pattern smaller than the minimum line width La of the design rule is deleted.
Thereafter, the light transmission data and the light shielding data in the fourth chip formation region 50 having the pattern 26 shown in FIG.
The light transmission data and the light shielding data in the third chip formation region 40 having the actual wiring patterns 11 to 14 and the dummy patterns 21 and 24 shown in FIG. As a result, as shown in FIG.
0, the final dummy pattern 2 consisting of light-shielded data
1, 24, 26 and the first to fourth actual wiring patterns 11 to
14 is generated.

At this time, the second actual wiring pattern 12 and the third
X1 between the actual wiring pattern 13 and the dummy pattern 2
6, and the interval X1 is 2Sa, as described above.
+ 2La + Sd, the dummy pattern 2
6 has a width X6 smaller than 2La + Sd. Therefore, the fifth dummy pattern including the final dummy patterns 21, 24, 26
The maximum space width in the chip formation region 60 is 2S
a + La.

Thereafter, a reticle having a mask pattern shown in FIG. 11 is formed. Next, a silicon substrate having a first insulating film on its surface is prepared, and an Al alloy film is formed as a conductive film over the first insulating film. Next, a resist film is applied on the Al alloy film, and after exposing the resist film using the reticle, the resist film is developed. Thereby, the actual wiring patterns 11 to 14 are formed on the Al alloy film.
Then, a resist pattern to which the final dummy patterns 21, 24, and 26 have been transferred is formed.

Thereafter, the Al alloy film is etched using the resist pattern as a mask to form a real wiring pattern and a final dummy pattern made of the Al alloy film on the first insulating film. Next, a second insulating film is formed on the actual wiring pattern and the final dummy pattern.

According to the first embodiment, like the conventional dummy pattern designing method, a product using an automatic placement and routing represented by a gate array in which wiring is regularly formed on a virtual grid. Will not be applicable only to In other words, custom ICs that do not use automatic placement and routing
Pattern data having a dummy pattern can be automatically generated only by an algorithm for data logical synthesis with respect to wiring data subjected to manual correction or the like.

By forming a reticle using the mask pattern data and patterning the Al alloy film using the reticle, the sparse and dense portions of the wiring pattern can be equalized by the dummy pattern. It is possible to solve the problem caused by the density of the wiring pattern. Therefore, the etching processability of the Al alloy film can be improved.

As for the density of the final dummy pattern 21, the average pattern density can be easily changed by changing the size and shape of Ld × Ld of the basic dummy pattern 1.

The fourth chip formation region 5 shown in FIG.
In the dummy patterns 21 and 24 and the actual wiring patterns 11 to 14 at 0, the minimum space width is Sa, and the maximum space width X1 reaches 2Sa + 2La + Sd. Therefore, even if the dummy patterns 21 and 24 are inserted into the actual wiring pattern, a space variation of Sa to 2Sa + 2La + Sd occurs. However, by further performing the steps of FIGS. 9 to 11, the maximum space width can be suppressed within 2Sa + La, as described above. Therefore, FIG.
8 can reduce the space variation width by La + Sd as compared with the dummy pattern 21.24 shown in FIG. 8, improve the etching processability, and improve the manufacturing yield.

In the first embodiment, the basic dummy pattern 1 having a rectangular shape is used. However, the present invention is not limited to the rectangular shape, and it is also possible to use a basic dummy pattern having another shape.

In this embodiment, the actual wiring pattern 1 is formed in the second chip formation region 30 in the step shown in FIG.
Although 1 to 14 are expanded in the X direction and the Y direction by the minimum space Sa of the design rule, the actual wiring pattern may be expanded in the same direction by the minimum space of the design rule.

In the present embodiment, the steps shown in FIGS. 3 and 4 are performed after the steps shown in FIGS. 1 and 2, but after the steps shown in FIGS. The process shown in FIG. 2 can be performed.

Next, a method of designing a dummy pattern according to the second embodiment of the present invention will be described. Only the portions different from the first embodiment will be described.

In the step shown in FIG. 4, in the second chip formation region 30, the first to fourth real wiring patterns 11 to 14 composed of light-shielded data are formed in the X direction with a size larger than the minimum space Sa of the design rule. Enlarge both in the Y direction. Thus, an enlarged wiring pattern is formed in the second chip formation region 30. This enlarged wiring pattern is the first
The pattern is larger than that of the embodiment.

In the step shown in FIG. 9, in the fourth chip formation region 50, the first to fourth actual wiring patterns 11 to 14 and the dummy patterns 21,
Is enlarged in both the X and Y directions with a size larger than the minimum space Sa of the design rule. As a result, the fourth
The enlarged pattern is formed in the chip forming region. This enlarged pattern is a pattern larger than that according to the first embodiment.

In the second embodiment, the same effect as in the first embodiment can be obtained.

In the step shown in FIG. 4, the first to fourth real wiring patterns 11 to 14 are enlarged to have a size larger than the minimum space Sa of the design rule, and in the step shown in FIG. The fourth actual wiring patterns 11 to 14 and the dummy patterns 21 and 24 are enlarged with a size larger than the minimum space Sa of the design rule. For this reason, the space between the actual wiring pattern and the final dummy pattern can be made wider than the minimum space Sa of the design rule. Thereby, the parasitic capacitance between the actual wiring pattern and the dummy pattern can be reduced as compared with that of the first embodiment, and as a result, the deterioration of the signal transmission delay characteristic due to the parasitic capacitance can be suppressed.

The minimum space width between the actual wiring pattern and the final dummy pattern in the above case corresponds to the oversize amount obtained by enlarging the actual wiring pattern 14 by a size larger than the minimum space Sa of the design rule. Therefore, the parasitic capacitance value can be set in a desired capacitance value range by arbitrarily adjusting the oversize amount.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
Since there is a trade-off between the parasitic capacitance value between the actual wiring pattern and the dummy pattern and the etching workability of the actual wiring pattern in the second embodiment, both the parasitic capacitance value and the workability are within an allowable range. It is preferable to appropriately change the oversize amount according to the type of the device so as to fall within the range.

[0041]

As described above, according to the present invention, there is provided a dummy pattern designing method, a dummy pattern designing apparatus, and a dummy pattern applicable to an IC that does not use automatic placement and routing and wiring data that has been manually corrected. A semiconductor device and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a method for designing a dummy pattern according to a first embodiment of the present invention.

FIG. 2 is a plan view illustrating a method of designing a dummy pattern according to the first embodiment of the present invention and illustrating a step subsequent to FIG. 1;

FIG. 3 is a plan view for explaining the method of designing a dummy pattern according to the first embodiment of the present invention, and showing the next step of FIG. 2;

FIG. 4 is a plan view for explaining the method for designing a dummy pattern according to the first embodiment of the present invention and showing a step subsequent to FIG. 3;

FIG. 5 is a plan view for explaining the dummy pattern designing method according to the first embodiment of the present invention and showing a step subsequent to FIG. 4;

FIG. 6 is a plan view for explaining the method of designing the dummy pattern according to the first embodiment of the present invention and showing a step subsequent to FIG. 5;

FIG. 7 is a plan view for explaining the method of designing the dummy pattern according to the first embodiment of the present invention and showing a step subsequent to FIG. 6;

FIG. 8 is a plan view for explaining the dummy pattern designing method according to the first embodiment of the present invention and showing a step subsequent to FIG. 7;

FIG. 9 is a plan view for explaining the method of designing the dummy pattern according to the first embodiment of the present invention, and showing the next step of FIG. 8;

FIG. 10 is a plan view for explaining the dummy pattern designing method according to the first embodiment of the present invention, and showing the next step of FIG. 9;

FIG. 11 is a plan view for explaining the method of designing the dummy pattern according to the first embodiment of the present invention, and showing the next step of FIG. 10;

FIG. 12 is a plan view for explaining a conventional dummy pattern designing method.

[Explanation of symbols]

1, 1 'basic dummy pattern 2', 3 ', 4' area composed of translucent data 3 area other than basic dummy pattern 10 first chip formation area 11 to 14 first to fourth real wiring pattern 11 'to 14 'first to fourth enlarged wiring patterns 19 area composed of light-transmitting data 20 area composed of light-shielded data 21, 24, 26 final dummy pattern 21', 2
4 'Enlarged pattern 22, 23 Pattern composed of light-shielded data 22', 23 'Pattern composed of light-transmitted data 30 Second chip formation area 40 Third chip formation area 50 Fourth chip formation area 101 Virtual grid 102 Signal wiring 103,10
4 Dummy wiring pattern

Claims (4)

[Claims] 1. A method of designing a dummy pattern to be inserted into a wiring pattern on a reticle, comprising: a plurality of basic dummy patterns each formed of light shielding data having a predetermined shape in a first chip forming area formed of light transmitting data; A first step of arranging at a predetermined interval; a second step of inverting the light transmission data and the light shielding data in the first chip formation area; A third step of arranging a wiring pattern consisting of
A fourth step in which the direction and the Y direction are enlarged by the minimum space of the design rule or more, and a light transmission data and a light shielding data in the first chip formation region after being inverted in the second step are obtained by the fourth step. A fifth step of creating a third chip forming area including the light transmitting data and the light shielding data by combining the light transmitting data and the light shielding data in the enlarged second chip forming area with a third chip; A sixth step of inverting the light-transmitted data and the light-shielded data in the formation area, a seventh step of deleting light-shielded data smaller than the minimum line width of the design rule in the third chip formation area, and a deletion in the seventh step The light transmission data and the light blocking data in the third chip formation region after the light transmission data and the light blocking in the second chip formation region after the placement in the third step. An eighth step of creating a fourth chip formation region including light-transmitting data and light-shielded data by combining the data with the data; and forming a pattern including light-shielded data in the fourth chip formation region in both the X and Y directions. A ninth step of enlarging by at least the minimum space of the design rule, a tenth step of inverting the light-transmitted data and the light-shielded data in the fourth chip formation region enlarged by the ninth step, a tenth step By combining the light transmission data and the light shielding data in the fourth chip formation region after inversion by the above with the light transmission data and the light shielding data in the fourth chip formation region created in the eighth step, the light transmission data and the light shielding data are combined. First to create a fifth chip formation region composed of light-shielded data
1. A method for designing a dummy pattern, comprising: 2. An apparatus for designing a dummy pattern to be inserted into a wiring pattern on a reticle, comprising: a plurality of basic dummy patterns each formed of light shielding data having a predetermined shape in a first chip forming area formed of light transmitting data; A first means for inverting the light-transmitted data and the light-shielded data in the first chip formation area after being arranged at a predetermined interval; and a wiring pattern made of the light-shielded data in the second chip formation area made of the light-transmitted data Is arranged, in the second chip formation region, the wiring pattern is expanded in the X direction and the Y direction by at least the minimum space of the design rule.
Means for transmitting light-transmitted data and light-shielded data in the first chip formation area after being inverted by the first means, and light-transmitted data and light-shielded data in the second chip formation area after being expanded by the second means Third means for creating a third chip formation region including light transmission data and light shielding data by combining the data with the data; and inverting the light transmission data and light shielding data in the third chip formation region, After deleting the light-shielded data smaller than the minimum line width, the light-transmitted data and the light-shielded data in the third chip formation area are replaced with the light-transmitted data and the light-shielded data in the second chip formation area after the wiring pattern is arranged by the second means. A fourth means for creating a fourth chip forming area composed of the light transmitting data and the light shielding data by combining with the light shielding data; After enlarging the pattern of the light shielding data in the X direction and the Y direction by at least the minimum space of the design rule, the light transmitting data and the light shielding data are inverted in the fourth chip formation region, and the light transmitting data and the light shielding data are Fifth means for creating a fifth chip formation area composed of light transmission data and light shielding data by combining the light transmission data and light shielding data in the fourth chip formation area created by the fourth means. An apparatus for designing a dummy pattern, comprising: 3. A wiring pattern formed on the first insulating film, a dummy pattern formed on the first insulating film, and a wiring pattern formed on the wiring pattern, the dummy pattern and the first insulating film. A second insulating film, wherein the dummy pattern comprises a plurality of basic dummy patterns each formed of light-shielded data having a predetermined shape in a first chip formation region formed of light-transmitted data. Disposing the light-transmitting data and the light-shielded data in the first chip formation region at an interval, and disposing a wiring pattern made of the light-shielded data in the second chip formation region made of the light-transmitted data; In the chip forming region, the wiring pattern is
In both the direction and the Y direction, the light transmission data and the light shielding data in the first chip formation area after the inversion are enlarged by the minimum space of the design rule, and the light transmission data in the second chip formation area after the enlargement are changed. By combining the data with the data and the light-shielded data, the third
The light transmission data and the light shielding data are inverted in the third chip formation region, and the light shielding data less than the minimum line width of the design rule is deleted in the third chip formation region. The light transmitting data and the light shielding data in the third chip forming region are combined with the light transmitting data and the light shielding data in the second chip forming region after the wiring patterns are arranged, so that A fourth chip formation area is formed, and a pattern formed of light-shielded data is enlarged in the fourth chip formation area by at least the minimum space of the design rule in the X direction and the Y direction. The light transmission data and the light shielding data are inverted in the formation area, and the light transmission data and the light shielding in the fourth chip formation area after the inversion are inverted. The data is combined with the light-transmitting data and the light-shielded data in the fourth chip-forming region, thereby forming a pattern including the light-shielded data obtained by creating the fifth chip-formed region including the light-transmitted data and the light-shielded data. A semiconductor device, comprising: 4. A method for manufacturing a semiconductor device, comprising: exposing a resist film using a reticle having a wiring pattern and a dummy pattern, wherein the dummy pattern is formed in a first chip formation region including light transmission data. A plurality of basic dummy patterns each formed of light-shielded data having a predetermined shape are arranged at a predetermined interval from each other, and the light-transmitted data and the light-shielded data are inverted in the first chip formation region, and a second chip formed of light-transmitted data is formed. A wiring pattern composed of light-shielded data is arranged in the area, and the wiring pattern is replaced with X in the second chip formation area.
In both the direction and the Y direction, the light transmission data and the light shielding data in the first chip formation region after the inversion are enlarged by the minimum space of the design rule, and the light transmission data in the second chip formation region after the enlargement are enlarged. By combining the data with the data and the light-shielded data, the third
The light transmission data and the light shielding data are inverted in the third chip formation region, and the light shielding data less than the minimum line width of the design rule is deleted in the third chip formation region. The light transmitting data and the light shielding data in the third chip forming region are combined with the light transmitting data and the light shielding data in the second chip forming region after the wiring patterns are arranged, so that A fourth chip formation area is formed, and a pattern formed of light-shielded data is enlarged in the fourth chip formation area by at least the minimum space of the design rule in the X direction and the Y direction. The light transmission data and the light shielding data are inverted in the formation area, and the light transmission data and the light shielding in the fourth chip formation area after the inversion are inverted. The data is combined with the light-transmitting data and the light-shielded data in the fourth chip-forming area, thereby forming a fifth chip-forming area including the light-transmitting data and the light-shielded data. A method for manufacturing a semiconductor device, comprising: