JP2001076491A - Latch type sense amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to perform surely latch of complementary signals having minute potential difference even when threshold voltage of a pair of field effect transistors being a driving element are unbalanced, with respect to a latch type sense amplifier incorporated and used in a semiconductor device requiring a circuit for amplifying a complementary signal having minute potential difference. SOLUTION: nMOS transistors 27, 29 having a large ON-resistance value are temporarily turned on before data are read out from a memory cell, a minute current is made to flow in nMOS transistors 22, 23 being a driving element, potentials of nodes N6, N7 are temporarily lowered, even when threshold voltage Vth22, Vth23 of nMOS transistors are unbalanced, source potentials of the nMOS transistors 22 23 are set to a potential at which normal latch operation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device requiring a circuit for amplifying a complementary signal having a small voltage difference, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory) or a ROM (R).
The present invention relates to a latch type sense amplifier mounted and used in an ead only memory).

LS used for portable equipment such as portable telephones
I is required to reduce power consumption without impairing high-speed performance. In order to reduce power consumption, it is effective to lower the power supply voltage, and it is desirable to avoid a circuit system in which current flows constantly.

For example, in an SRAM, a current mirror type differential amplifier has been used as a sense amplifier for amplifying a minute voltage difference between a pair of bit lines. Therefore, it is difficult to operate at a high speed with a low power supply voltage. Therefore, recently, a latch type sense amplifier has been used instead of the current mirror type differential amplifier.

[0004]

2. Description of the Related Art FIG. 10 is a circuit diagram showing a part of an SRAM having an example of a conventional latch type sense amplifier. In FIG. 10, WL is a word line, and BL and / BL are a pair of bit lines.

Further, 1 is a 6-transistor type (complete CMO)
S-type) memory cell, 2 is a VDD power supply line for supplying a power supply voltage VDD, 3 and 4 are pMOS transistors, 5
-8 are nMOS transistors.

Reference numeral 9 denotes a bit line clamp circuit for clamping the bit lines BL and / BL to a power supply voltage VDD as required. Reference numerals 10 and 11 denote VDD power supply lines, 12 and
13 is a pMOS transistor, and CLK1 is an internal clock for driving the bit line clamp circuit 9.

Reference numeral 14 denotes an example of a conventional latch-type sense amplifier. Reference numeral 15 denotes a VDD power supply line;
OS transistors, 22 to 24 are nMOS transistors, DO and / DO are sense amplifier outputs, and CLK2 is an internal clock for driving the latch type sense amplifier 14.

The bit lines BL and / BL are connected to a large number of memory cells in addition to the memory cell 1, and have a large parasitic capacitance. Also, bit lines BL, / B
A writing circuit is connected to L, and writing to a selected memory cell is performed.

Actually, there are a plurality of bit line pairs including bit lines BL and / BL, and a column switch is provided between the plurality of bit line pairs and the latch type sense amplifier 14. , One bit line pair selected from the plurality of bit line pairs is connected to the latch type sense amplifier 14, but here, for the sake of simplicity, the bit line pairs other than the bit lines BL and / BL are connected. The illustration of the column switches is omitted. Therefore, FIG. 10 is equivalent to a state where the bit lines BL and / BL are selected.

FIG. 11 is a waveform diagram for explaining the operation of the conventional latch type sense amplifier 14 shown in FIG. 10, and shows the potential of the word line WL and the internal clocks CLK1 and CLK2.
, Potentials of bit lines BL and / BL, sense amplifier outputs DO and / DO, and nMO in latch type sense amplifier 14.
Node N which is a common source of S transistors 22 and 23
1 is shown.

In the memory cell 1, the pMOS
Transistor 3 = OFF, pMOS transistor 4 = O
N, nMOS transistor 5 = ON, nMOS transistor 6 = OFF, node N2 is at L level, and node N3 is at H level.

Here, the conventional latch type sense amplifier 14
Before the time T1, which is the start timing of reading data from the memory cell 1, the word line WL and the internal clocks CLK1 and CLK2 are at the L level.

At time T1, which is the start timing of reading data from the memory cell 1, the word line WL and the internal clock CLK1 are set to the H level, and thereafter, it is the timing to drive the latch type sense amplifier 14. At time T2, the internal clock CLK2
Are set to the H level.

Then, at time T3 when the drive of the latch type sense amplifier 14 is completed, the word line WL and the internal clocks CLK1 and CLK2 are returned to the L level.

Here, the word line WL and the internal clock C
Memory cell 1 in which LK1 and CLK2 are at L level
In the steady state before reading data from memory cell 1,
, NMOS transistors 7 and 8 = OFF, pMOS transistors 12 and 13 = ON in bit line clamp circuit 9, pMOS transistors 18 to 21 = ON in latch type sense amplifier 14, nMO
The S transistor 24 is off.

As a result, the bit lines BL and / BL are clamped to the power supply voltage VDD via the pMOS transistors 12 and 13, respectively, and the sense amplifier outputs DO and / D
O is also clamped to the power supply voltage VDD.

The nMOS transistors 22 and 23
Is turned off with the potential of the node N1 raised to VDD-Vth because the nMOS transistor 24 is turned off. Here, Vth is a threshold voltage of the nMOS transistors 22 and 23. Also, since the sense amplifier outputs DO and / DO are clamped to the power supply voltage VDD, the pMOS transistors 16 and 17
FF.

From this state, the memory cell 1 is selected,
At time T1, when the word line WL and the internal clock CLK1 are set to the H level, in the memory cell 1, nMO
S transistors 7, 8 = ON, bit line clamp circuit 9
, The pMOS transistors 12, 13 = OFF
The bit lines BL and / BL are connected to the memory cell 1 and released from the bit line clamp circuit 9.

As a result, a cell current flows from the bit line BL to the ground through the nMOS transistors 7 and 5, the charge of the parasitic capacitance of the bit line BL is discharged, and the potential of the bit line BL is slowly lowered from the power supply voltage VDD. .

On the other hand, since the potential of node N3 in memory cell 1 is maintained at power supply voltage VDD, bit line / BL
Is not discharged, and the potential of the bit line / BL is maintained at the power supply voltage VDD.

In the latch type sense amplifier 14, the pMOS transistors 18 and 19 are turned off.
The sense amplifier outputs DO and / DO which have been clamped to the power supply voltage VDD are released.

As a result, the potential of the sense amplifier output DO is slowly lowered from the power supply voltage VDD following the potential of the bit line BL. On the other hand, the potential of sense amplifier output / DO is equal to power supply voltage V
DD is maintained.

The nMOS transistors 22 and 23
Since the internal clock CLK2 is at the L level and the nMOS transistor 24 is OFF, the OFF state is maintained with the potential of the node N1 raised to VDD-Vth.

Further, the potential of the sense amplifier output DO is only slightly lowered, for example, about 100 mV from the power supply voltage VDD before the latch type sense amplifier 14 is driven. Until the pMOS transistors 16 and 17 are turned off
Maintain state.

Then, the timing for driving the latch type sense amplifier 14, that is, the timing T2 at which the voltage difference .DELTA.VBL between the bit lines BL and / BL becomes a certain value (for example, about 100 mV), becomes the internal clock C.
When LK2 is set to the H level, the pMOS transistor 2
0, 21 = OFF, the nodes N4, N5 are disconnected from the bit lines BL, / BL, the nMOS transistor 24 is turned ON, and the potential of the node N1 is set to the ground voltage G.
Reduced to ND.

Here, the nMOS transistors 22 and 23
Of the node N1 which is the common source of the
Are reduced to nMOS transistors 22 and 23
Starts to turn on, but the potential of the sense amplifier output DO = V
DD−ΔVBL, potential of sense amplifier output / DO = VD
Since it is D, the nMOS transistor 22 is turned on first, and the sense amplifier output DO is rapidly reduced.

On the other hand, the nMOS transistor 23
Starts turning on later than the nMOS transistor 22 and starts lowering the sense amplifier output / DO. However, since the sense amplifier output DO applied to its gate is rapidly lowered by the nMOS transistor 22, it turns off immediately, and , The sense amplifier output / DO is not reduced.

Further, the pMOS transistor 1 which was turned off before the latch type sense amplifier 14 was driven is turned off.
6 and 17, the pMOS transistor 17 whose gate is applied with the sense amplifier output DO which is rapidly lowered is turned on, and the sense amplifier output / DO is connected to the power supply voltage VD.
D will be returned.

Since the pMOS transistor 16 returns to the power supply voltage VDD immediately after the sense amplifier output / DO applied to the gate is slightly lowered,
The sense amplifier output DO remains at the node N1
Does not prevent the voltage from being lowered to the ground voltage GND.

As described above, the latch type sense amplifier 1
4 amplifies the small voltage difference ΔVBL between the bit lines BL and / BL, and outputs the sense amplifier output DO of GND level and V
The sense amplifier output / DO at the DD level is output. The sense amplifier outputs DO and / DO output from the latch type sense amplifier 14 are output to the outside of the SRAM via a latch circuit (not shown).

When the word line WL and the internal clocks CLK1 and CLK2 are returned to the L level at time T3 when the driving of the latch type sense amplifier 14 ends, in the memory cell 1, the nMOS transistor 7 8 = OFF, and the memory cell 1 is disconnected from the bit lines BL and / BL.

In the bit line clamp circuit 9, the pMOS transistors 12, 13 = ON, and in the latch type sense amplifier 14, the nMOS transistor 2
4 = OFF, pMOS transistors 18-21 = ON, bit lines BL, / BL and sense amplifier output D
The potentials of O and / DO are returned to the power supply voltage VDD.

As a result, the pMOS transistors 16, 1
7 = OFF, and the nMOS transistor 22
23 turns off the potential of the node N1 to VDD-Vth, and returns to the steady state until the next read or write.

Here, the read operation when the node N2 in the memory cell 1 is at the L level and the node N3 is at the H level has been described. However, since the circuit is symmetrical, the node N2 is at the H level. The read operation in the case where the node N3 is at the L level is performed in the same manner as in the above case with the left and right symmetrical.

Here, the latch type sense amplifier 14 has the advantage that the current does not flow in the steady state and the current only flows during the transition of the data latch in the read operation, and the power consumption is small.

[0036]

By the way, the threshold voltage Vth22 of the nMOS transistors 22 and 23,
If Vth23 is completely equal, if a slight potential difference is applied between bit lines BL and / BL, latch type sense amplifier 14
Can correctly latch data read from a memory cell.

However, in practice, it is difficult to avoid manufacturing variations in the threshold voltage of the MOS transistor, and even between two adjacent MOS transistors such as the nMOS transistors 22 and 23, the threshold voltage of the MOS transistor cannot be reduced. A relative difference occurs between Vth22 and Vth23. These threshold voltages Vth22, Vth2
The imbalance of No. 3 tends to increase as the gate length decreases.

FIG. 12 shows nMOS transistors 22 and 23.
Is a circuit diagram for explaining a problem that occurs when the threshold voltages Vth22 and Vth23 are not equal, that is, a problem of the conventional latch-type sense amplifier 14. In this case, the bit lines BL and / It is assumed that the bit line BL of BL is lowered.

Here, the output nodes N4 and N5 of the latch type sense amplifier 14 are connected to the bit lines BL and / BL until immediately before the latch type sense amplifier 14 is driven. Immediately before driving, the voltage difference between the sense amplifier outputs DO and / DO becomes ΔVBL, like the voltage difference between the bit lines BL and / BL.

In this case, the normal latch of the data read from the memory cell is performed when the nMOS transistor 22
However, since the gate potential of the nMOS transistor 23 is lower than the gate potential of the nMOS transistor 22 by ΔVBL, when Vth22 ≦ Vth23, the latch type sense amplifier 14 is read from the memory cell. Obviously, the data can be latched normally.

Therefore, when Vth22> Vth23, a condition under which the latch type sense amplifier 14 can normally latch data read from the memory cell will be considered.

First, at time T1 shown in FIG.
The potential of the node N1 is at least (VDD−Vth2
2) and (VDD-Vth23), it should have been raised to the higher one, but here, Vth22> Vth
23, the potential of the node N1 is (VDD-Vth23).

Since the node N1 is in a high impedance state and there is no factor for lowering the potential of the node N1, the potential of the node N1 is higher than (VDD-Vth23) due to noise and leakage of the nMOS transistors 22 and 23. It can be.

Next, by the time T2, the nMOS transistor 23 has its gate potential changed from the power supply voltage VDD to ΔV
Although the voltage drops only by BL, even if the gate potential drops, the source node N1 is in a high impedance state and there is no factor for lowering the potential.
(VDD-Vth23) or more.

Here, at time T2, the internal clock CLK
2 becomes H level, and the nMOS transistor 24 is turned on.
Then, the potential of the node N1 decreases and the nMOS transistors 22 and 23 try to be turned on. However, the potential of the node N1 required for turning on the nMOS transistor 22 is VDD−Vth22, which is necessary for turning on the nMOS transistor 23. The potential of the node N1 is VDD−ΔVBL−Vth23.

Therefore, the condition for turning on the nMOS transistor 22 first is as follows: VDD−Vth22> VDD−ΔVBL−Vth23, that is, ΔVBL> Vth22−Vth23.

It is clear from this that the voltage difference ΔVBL between the bit lines BL and / BL must be (Vth22-Vth23) in order for the data read from the memory cell to be normally latched by the latch type sense amplifier 14. ).

Therefore, the conventional latch type sense amplifier 1
In No. 4, there was a problem that the timing of raising the internal clock CLK2 could not be advanced, and it was difficult to shorten the access time of the SRAM.

If nMOS transistors 22 and 23 having a long gate length are used as the nMOS transistors 22 and 23, the imbalance between the threshold voltages Vth22 and Vth23 of the nMOS transistors 22 and 23 can be suppressed to some extent, but they are completely zero. Can not be.

In view of the above, the present invention can reliably latch a complementary signal having a small voltage difference even when the threshold voltages of a pair of field effect transistors forming a driving element are unbalanced. Even if the threshold voltage of the pair of field effect transistors forming the driving element has an imbalance, the latching of the complementary signal having a small voltage difference can be performed reliably and at high speed. It is an object of the present invention to provide a latch-type sense amplifier capable of performing the following.

[0051]

According to the present invention, there is provided a latch type sense amplifier comprising: a pair of field effect transistors each having a gate and a drain cross-connected; a drain of each of the pair of field effect transistors; And a second pair of switch means connected between a source of each of the pair of field effect transistors and a second power supply. And a third pair of switch means having an on-resistance value higher than the on-resistance value of the second pair of switch means.

In the present invention, a complementary signal having a minute voltage difference is applied between the drains of the pair of field effect transistors, and the first and third pair of switch means are turned off, and the second pair of switch means are turned on. By doing so, the latch operation of the complementary signal of the minute voltage difference can be started, but before the start of the latch operation, the first and third pair of switch means are temporarily turned on, and the pair of field effect Even if a threshold current of the pair of field-effect transistors is unbalanced by temporarily passing a small current through the transistors, the source potentials of the pair of field-effect transistors can be normally latched. Can be set to a potential that allows

[0053]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a latch type sense amplifier according to first to third embodiments of the present invention will be described with reference to FIGS. 1, 4, and 8, portions corresponding to FIG. 10 are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1 is a circuit diagram showing a part of an SRAM having a latch type sense amplifier according to a first embodiment of the present invention.
The portion denoted by reference numeral 25 is the latch type sense amplifier according to the first embodiment of the present invention.

In the latch type sense amplifier 25 according to the first embodiment of the present invention, the sources of the nMOS transistors 22 and 23 are separated, and the nMOS transistors 26 and 27 are connected between the source of the nMOS transistor 22 and the ground. The nMOS transistors 28 and 29 are connected between the source of the nMOS transistor 23 and the ground, and the others are connected to the conventional latch type sense amplifier 14 shown in FIG.
It is configured similarly to.

Here, the nMOS transistors 26 and 28
Are turned on when nMOS transistors 22
The nMOS transistors 27 and 29 have an ON resistance value of a high resistance value, for example, by increasing the gate length or decreasing the gate width. Then, at the time of ON, each is configured so that a minute drain current flows.

The ON and OFF of the nMOS transistors 26 and 28 are controlled by the internal clock CLK2.
The nMOS transistors 27 and 29 are connected to the internal clock CLK.
3 controls ON and OFF.

FIGS. 2 and 3 are a waveform diagram and a circuit diagram, respectively, for explaining the operation of the latch type sense amplifier 25 according to the first embodiment of the present invention. FIG. 2 shows the potential of the word line WL and the internal clock. CLK1 to CLK3 and bit line B
L, / BL potential and sense amplifier outputs DO, / DO
And the potentials of the nodes N6 and N7 which are the sources of the nMOS transistors 22 and 23. In FIG. 3, reference numerals 30 and 31 denote nMOS transistors 27,
29 shows the ON resistance.

Also in this example, in the memory cell 1, p
MOS transistor 3 = OFF, pMOS transistor 4 = ON, nMOS transistor 5 = ON, nMOS transistor 6 = OFF, node N2 is at L level,
It is assumed that the node N3 is at the H level.

Here, in the SRAM including the latch type sense amplifier 25 according to the first embodiment of the present invention, before the time T4, which is a predetermined time before the time T1, which is the start timing of reading data from the memory cell 1, Word line WL and internal clocks CLK1 to CLK3 are at L level.

Prior to reading data from memory cell 1, internal clock CLK3 is temporarily set to an H level from time T4 to time T5.

At time T1, which is the start timing of reading data from the memory cell 1, the word line WL and the internal clock CLK1 are set to the H level, and thereafter, the latch type sense circuit according to the first embodiment of the present invention is used. At time T2, which is the timing for driving the amplifier 25, the internal clock CLK2 goes high.

Then, at time T3 when the driving of the latch type sense amplifier 25 according to the first embodiment of the present invention ends, the word line WL and the internal clock CL are turned off.
K1 and CLK2 are at L level.

Here, the word line WL and the internal clock C
In a steady state before time T4 when LK1 to CLK3 are at L level, in the memory cell 1, the nMOS transistors 7, 8 = OFF, in the bit line clamp circuit 9, the pMOS transistors 12, 13 = ON, In the latch type sense amplifier 25 according to the first embodiment of the present invention, the pMOS transistors 18 to 21 = ON, nMO
The S transistors 26 to 29 are turned off.

As a result, the bit lines BL and / BL are clamped to the power supply voltage VDD via the pMOS transistors 12 and 13, respectively, and the sense amplifier outputs DO and / D
O is also clamped to the power supply voltage VDD and the node N
6 is in a high impedance state at (VDD-Vth22) or higher potential, and the node N7
Is in a high impedance state at (VDD-Vth23) or higher. Further, since the sense amplifier outputs DO and / DO are clamped at the power supply voltage VDD, the pMOS transistors 16 and 17 are turned off.
are doing.

At time T4, the internal clock CLK
3 is set to the H level, the nMOS transistor 27,
29 = ON, and as shown in FIG. 3, the nMOS transistors 27 and 29 each have a small drain current I2.
7, I29 flows, and the potential of the node N6 is reduced to VDD−Vth22−ΔV27, and the potential of the node N7 is reduced to VDD−Vth23−ΔV29.

Where ΔV27 is the nMOS transistor 2
2 is a voltage required for flowing the minute current I27, and ΔV29 is a voltage required for the nMOS transistor 23 to flow the minute current I29.
Are the same size, I27 and I29 have substantially equal current values, and ΔV27 and ΔV29 have substantially equal voltage values.

Thereafter, at time T5, the internal clock CLK
When 3 is returned to the L level, the potential of the node N6 returns to VDD-Vth22, and the potential of the node N7 returns to VDD-Vth23 in parallel at the same speed.

It takes a long time for the potential of the node N6 to completely return to VDD-Vth22 and for the potential of the node N7 to completely return to VDD-Vth23.

Therefore, immediately before time T2, the potential of the node N6 becomes VDD-Vth22-.DELTA.V, and the potential of the node N7 becomes VDD-Vth23-.DELTA.V. Here, ΔV is a minute voltage.

As described above, the nMOS transistor 27,
Reference numeral 29 denotes a high impedance state, in which the potentials of the nodes N6 and N7 whose potentials are uncertain are temporarily reduced, and the potential of the node N6 is reliably reduced to VDD-Vth22-ΔV until immediately before the latch operation is started. At the same time, the function of reliably setting the potential of the node N7 to VDD−Vth23−ΔV is achieved.

At time T1, when word line WL and internal clock CLK1 are set to H level, memory cell 1
, The nMOS transistors 7 and 8 = ON, the pMOS transistors 12 and 13 = OFF in the bit line clamp circuit 9, and the bit lines BL and / BL are
Connected to the memory cell 1 and released from the bit line clamp circuit 9.

As a result, a cell current flows from the bit line BL to the ground through the nMOS transistors 7 and 5, the charge of the parasitic capacitance of the bit line BL is discharged, and the potential of the bit line BL is slowly lowered from the power supply voltage VDD. .

On the other hand, since the potential of node N3 in memory cell 1 is maintained at power supply voltage VDD, bit line / BL
Is not discharged, and the potential of the bit line / BL is maintained at the power supply voltage VDD.

In the latch type sense amplifier 25 according to the first embodiment of the present invention, the pMOS transistor 1
8 and 19 are turned off, and the sense amplifier outputs DO and / DO which have been clamped to the power supply voltage VDD are released.

As a result, the potential of the sense amplifier output DO is slowly lowered from the power supply voltage VDD, following the potential of the bit line BL. On the other hand, the sense amplifier output / DO is maintained at the power supply voltage VDD, similarly to the bit line / BL.

Here, the potential of the bit line BL is changed to the power supply voltage V
At time T2 at which the sense amplifier output DO decreases by ΔVBL from the power supply voltage VDD, the gate-source voltage Vgs of the nMOS transistor 22 becomes VDD− (VDD−Vth22−ΔV) = Vth22 + ΔV, and the nMOS The gate-source voltage Vgs of the transistor 23 is VDD−ΔVBL− (VDD−Vth23−ΔV) = Vth
23 + ΔV−ΔVBL.

Further, the potential of the sense amplifier output DO is slightly lowered, for example, about 100 mV from the power supply voltage VDD before the latch type sense amplifier 25 of the first embodiment of the present invention is driven. Therefore, the latch type sense amplifier 2 according to the first embodiment of the present invention
5 is driven until the pMOS transistors 16, 17
Is OFF.

Then, the timing for driving the latch type sense amplifier 25 according to the first embodiment of the present invention, that is, the time when the potential difference ΔVBL between the bit lines BL and / BL becomes a certain value (for example, about 100 mV). T2
When the internal clock CLK2 is set to the H level,
In the latch type sense amplifier 25 according to the first embodiment of the present invention, the pMOS transistors 20 and 21 are turned off, the nodes N4 and N5 are disconnected from the bit lines BL and / BL, and the nMOS transistors 26 and 28 are turned on.
And the potentials of the nodes N6 and N7 are reduced to the ground potential GND.

Here, the gate-source voltage Vgs of the nMOS transistor 22 is set to Vth22 + ΔV, and the nMOS transistor 22 is already in a shallow ON state.
Immediately turns on completely. On the other hand, nMOS
The transistor 23 has a gate-source voltage Vgs of Vth23 + ΔV−ΔVBL.
It turns on later than the transistor 22.

As described above, in the latch type sense amplifier 25 according to the first embodiment of the present invention, when (potential of the bit line BL) <(potential of the bit line / BL), the nMOS
The threshold voltage Vth2 of the transistors 22 and 23
2. Irrespective of the imbalance of Vth23, the nMOS transistor 22 is turned on first and the sense amplifier output DO
Will be reduced rapidly.

On the other hand, nMOS transistor 23
Starts turning on later than the nMOS transistor 22 and starts lowering the sense amplifier output / DO. However, since the sense amplifier output DO applied to its gate is rapidly lowered by the nMOS transistor 22, it turns off immediately, and , The sense amplifier output / DO is not reduced.

Further, the p-state which was turned off before the latch-type sense amplifier 25 of the first embodiment of the present invention was driven.
Of the MOS transistors 16 and 17, the pMOS transistor 17 whose gate is supplied with the sense amplifier output DO which is rapidly lowered is turned on, and the sense amplifier output / DO is returned to the power supply voltage VDD.

Since the pMOS transistor 16 returns to the power supply voltage VDD immediately after the sense amplifier output / DO applied to the gate is slightly lowered,
The sense amplifier output DO remains at the node N6
Does not prevent the voltage from being lowered to the ground voltage GND.

As described above, the latch type sense amplifier 25 according to the first embodiment of the present invention amplifies the minute voltage difference ΔVBL between the bit lines BL and / BL, and outputs the GND level sense amplifier output DO and VDD. The level of the sense amplifier output / DO is output. The sense amplifier outputs DO and / DO output from the latch type sense amplifier 25 according to the first embodiment of the present invention are sent to a latch circuit (not shown) and output outside the SRAM.

Then, at time T3 which is the timing to end the driving of the latch type sense amplifier 25 according to the first embodiment of the present invention, the word line WL and the internal clock CLK are reached.
1, when the CLK2 is set to the L level, in the memory cell 1, the nMOS transistors 7, 8 are turned off,
Memory cell 1 is disconnected from bit lines BL and / BL.

In the bit line clamp circuit 9, the pMOS transistors 12 and 13 are turned on. In the latch type sense amplifier 25 according to the first embodiment of the present invention,
The nMOS transistors 26 and 28 = OFF, the pMOS transistors 18 to 21 = ON, and the bit lines BL and /
The potentials of BL and sense amplifier outputs DO and / DO are returned to power supply voltage VDD.

As a result, the pMOS transistors 16, 1
7 = OFF and the nMOS transistor 22
Means that the potential of the node N6 is lowered to VDD-Vth22 to be turned off, and the nMOS transistor 23 is lowered to the potential of the node N7 to VDD-Vth23 to be turned off to return to the steady state until the next reading or writing. Become.

Here, the read operation when the node N2 in the memory cell 1 is at the L level and the node N3 is at the H level has been described. However, since the circuit is bilaterally symmetric, the node N2 is at the H level. The read operation in the case where the node N3 is at the L level is performed in the same manner as in the above case with the left and right being symmetrical.

As described above, according to the latch type sense amplifier 25 of the first embodiment of the present invention, p
By setting the MOS transistors 18 and 19 = ON and the nMOS transistors 27 and 29 = ON, a minute current is temporarily applied to the nMOS transistors 22 and 23, and nM
The threshold voltage Vth of the OS transistors 22 and 23
22, even if Vth23 has imbalance,
The source potential of the nMOS transistors 22 and 23 can be set to a potential at which a normal latch operation can be performed.

Therefore, the nMOS transistor 22,
Even when the threshold voltages Vth22 and Vth23 of 23 are unbalanced, the data read from the memory cell can be reliably latched.

Second Embodiment FIG. 4 to FIG. 7 FIG. 4 is a circuit diagram showing a part of an SRAM having a latch type sense amplifier according to a second embodiment of the present invention.
The portion denoted by reference numeral 32 is a latch type sense amplifier according to the second embodiment of the present invention.

The latch-type sense amplifier 32 according to the second embodiment of the present invention has a capacitor 33 connected between nodes N6 and N7, and the rest is the latch-type sense amplifier according to the first embodiment of the present invention shown in FIG. The configuration is the same as that of No. 25. The capacitance of this capacitor 33 is determined by nodes N6, N
It is desirable that the parasitic capacitance is sufficiently larger than the parasitic capacitance between each of the electrodes 7 and the other electrode (for example, the capacitance with respect to the substrate).

FIG. 5 is a circuit diagram showing the configuration of the capacitor 33. Since the latch type sense amplifier 32 of the second embodiment of the present invention is symmetrical,
MOS capacitors 34 and 3 composed of MOS transistors
5 are connected in parallel so that the gates are not connected to each other, so that left-right symmetry of the circuit can be maintained. It should be noted that the capacitor 33 may be constituted by a capacitance between wirings or a PN junction capacitance.

FIGS. 6 and 7 are waveform diagrams and circuit diagrams for explaining the operation of the latch type sense amplifier 32 according to the second embodiment of the present invention. FIG. 6 shows the potential of the word line WL and the internal clock. CLK1 to CLK3 and bit line B
L, / BL potential and sense amplifier outputs DO, / DO
And the potentials of the nodes N6 and N7 in the latch type sense amplifier 32.

Also in this example, in the memory cell 1, p
MOS transistor 3 = OFF, pMOS transistor 4 = ON, nMOS transistor 5 = ON, nMOS transistor 6 = OFF, node N2 is at L level,
It is assumed that the node N3 is at the H level.

Here, in the SRAM including the latch type sense amplifier 32 according to the second embodiment of the present invention, before the time T6, which is a predetermined time before the time T1, which is the start timing of reading data from the memory cell 1, Word line WL and internal clocks CLK1 to CLK3 are at L level.

Prior to reading data from memory cell 1, internal clock CLK3 is temporarily set to an H level from time T6 to time T1.

At time T1, the word line WL
And the internal clock CLK1 is set to the H level,
The internal clock CLK3 is set to the L level, and thereafter, at time T2 which is the timing for driving the latch type sense amplifier 32 according to the second embodiment of the present invention, the internal clock C
LK2 is set to the H level.

Then, at time T3 when the driving of the latch type sense amplifier 32 according to the second embodiment of the present invention ends, the word line WL and the internal clock CL are turned off.
K1 and CLK2 are at L level.

Here, the word line WL and the internal clock C
In the steady state before time T6 when LK1 to CLK3 are at L level, in the memory cell 1, the nMOS transistors 7, 8 = OFF, in the bit line clamp circuit 9, the pMOS transistors 12, 13 = ON, In the latch type sense amplifier 32 according to the second embodiment of the present invention, the pMOS transistors 18 to 21 = ON, nMO
The S transistors 26 to 29 are turned off.

As a result, the bit lines BL and / BL are clamped to the power supply voltage VDD via the pMOS transistors 12 and 13, respectively, and the sense amplifier outputs DO and / D
O is also clamped to the power supply voltage VDD and the node N
6 is in a high impedance state at (VDD-Vth22) or higher potential, and the node N7
Is in a high impedance state at (VDD-Vth23) or higher.

At time T6, the internal clock CLK3
Is at H level, the nMOS transistors 27, 2
9 = ON, and as shown in FIG. 7, the nMOS transistors 27 and 29 each have a small drain current I27,
I29 flows, and the potential of the node N6 is reduced to VDD−Vth22−ΔV27, and the potential of the node N7 is reduced to VDD−Vth23−ΔV29.

As described above, ΔV27 is the voltage required for the nMOS transistor 22 to flow the minute current I27,
ΔV29 indicates that the nMOS transistor 23 has a small current I29.
Is necessary to supply the current, but since the nMOS transistors 27 and 29 have the same size,
29 have substantially equal current values, and ΔV27 and ΔV29 have substantially equal voltage values.

Then, at time T1, when the word line WL and the internal clock CLK1 are set to the H level and the internal clock CLK3 is set to the L level, in the memory cell 1, the nMOS transistors 7, 8 are turned on and the bit In the line clamp circuit 9, the pMOS transistors 12, 13 are turned off, and the bit lines BL, / BL
Are connected to the memory cell 1 and released from the bit line clamp circuit 9. In the latch type sense amplifier 32 according to the second embodiment of the present invention, the pMOS transistors 18 and 19 are OFF and the nMOS transistors 27 and 29
= OFF.

As a result, a cell current flows from bit line BL through nMOS transistors 7 and 5, and bit line BL
Is discharged, and the potential of the bit line BL is slowly lowered from the power supply voltage VDD.

On the other hand, the potential of node N3 in memory cell 1 is maintained at power supply voltage VDD, so that bit line / BL
Is not discharged, and the potential of the bit line / BL is maintained at the power supply voltage VDD.

In the latch type sense amplifier 32 according to the second embodiment of the present invention, the sense amplifier outputs DO and / DO which have been clamped to the power supply voltage VDD are released.

As a result, the potential of the sense amplifier output DO is slowly lowered from the power supply voltage VDD following the potential of the bit line BL. On the other hand, the sense amplifier output / DO is maintained at the power supply voltage VDD, similarly to the bit line / BL.

The potential of the node N6 returns toward VDD-Vth22, and the potential of the node N7 returns toward VDD-Vth23.

Here, the potential of the node N6 returns to VDD-Vth22-.DELTA.V even when the capacitor 33 is not provided, but the potential of the bit line BL changes from the power supply voltage VDD by .DELTA.
Since the voltage drops by VBL, the potential of the node N7 returns only to VDD−Vth23−ΔV−ΔVBL without the capacitor 33. Here, ΔV is a minute voltage as described above.

Therefore, the latch type sense amplifier 32 according to the second embodiment of the present invention includes a capacitor 33. Since the capacitor 33 works to maintain the relative potential difference between both ends, the potential of the node N6 and the potential of the node N7 are
It is pulled up in parallel at almost the same speed, and the potential of the node N7 becomes almost VDD−Vth23−ΔV.

Therefore, at time T2 when the sense amplifier output DO drops by ΔVBL from the power supply voltage VDD, the gate-source voltage Vgs of the nMOS transistor 22 becomes VDD− (VDD−Vth22−ΔV) = Vth22 + ΔV, and the nMOS transistor The gate-source voltage Vgs of 23 is: VDD−ΔVBL− (VDD−Vth23−ΔV) = Vth
23 + ΔV−ΔVBL.

As described above, in the latch type sense amplifier 32 according to the second embodiment of the present invention, by providing the nMOS transistors 27 and 29 and the capacitor 33,
In the high impedance state, the potentials of the nodes N6 and N7 whose potentials are uncertain are temporarily lowered, and
Immediately before the latch type sense amplifier 32 of the embodiment starts the latch operation, the potential of the node N6 is reliably set to VDD−Vth22−ΔV, and the potential of the node N7 is reliably set to VDD−Vth23−ΔV. .

Then, the timing for driving the latch type sense amplifier 32 according to the second embodiment of the present invention, that is, the time when the potential difference ΔVBL between the bit lines BL and / BL becomes a certain value (for example, about 100 mV). T2
When the internal clock CLK2 is set to the H level,
In the latch type sense amplifier 32 of the second embodiment of the present invention, the pMOS transistors 20 and 21 are turned off, the nodes N4 and N5 are disconnected from the bit lines BL and / BL, and the nMOS transistors 26 and 28 are turned on.
And the potentials of the nodes N6 and N7 are reduced to the ground potential GND.

Here, the gate-source voltage Vgs of the nMOS transistor 22 is set to Vth22 + ΔV, and it is already in a shallow ON state.
Immediately turns on completely. On the other hand, nMOS
The transistor 23 has a gate-source voltage Vgs of Vth23 + ΔV−ΔVBL.
Turns on later than the transistor 22.

As described above, in the latch type sense amplifier 32 according to the second embodiment of the present invention, when (potential of bit line BL) <(potential of bit line / BL), nMOS
The threshold voltage Vth2 of the transistors 22 and 23
2. Irrespective of the imbalance of Vth23, the nMOS transistor 22 is turned on first and the sense amplifier output DO
Will be reduced rapidly.

On the other hand, nMOS transistor 23
Starts turning on later than the nMOS transistor 22 and starts lowering the sense amplifier output / DO. However, since the sense amplifier output DO applied to its gate is rapidly lowered by the nMOS transistor 22, it turns off immediately, and , The sense amplifier output / DO is not reduced.

On the other hand, before the latch type sense amplifier 32 according to the second embodiment of the present invention is driven, p
Of the MOS transistors 16 and 17, the pMOS transistor 17 whose gate is supplied with the sense amplifier output DO which is rapidly lowered is turned on, and the sense amplifier output / DO is returned to the power supply voltage VDD.

The pMOS transistor 16 returns to the power supply voltage VDD immediately after the sense amplifier output / DO applied to the gate is slightly lowered, so that the pMOS transistor 16
The sense amplifier output DO remains at the node N6
Does not prevent the voltage from being lowered to the ground voltage GND.

As described above, the latch type sense amplifier 32 according to the second embodiment of the present invention amplifies the minute voltage difference ΔVBL between the bit lines BL and / BL, and outputs the GND level sense amplifier output DO and VDD. The level of the sense amplifier output / DO is output. The sense amplifier outputs DO and / DO output from the latch type sense amplifier 32 according to the second embodiment of the present invention are sent to a latch circuit (not shown) and output outside the SRAM.

At time T3, which is the timing for terminating the driving of the latch type sense amplifier 32 according to the second embodiment of the present invention, the word line WL and the internal clock CL are turned off.
K1 and CLK2 are set to L level, and in the memory cell 1, the nMOS transistors 7 and 8 are turned off, and the memory cell 1 is disconnected from the bit lines BL and / BL.

In the bit line clamp circuit 9, the pMOS transistors 12 and 13 are turned on. In the latch type sense amplifier 32 according to the second embodiment of the present invention,
The nMOS transistors 26 and 28 = OFF, the pMOS transistors 18 to 21 = ON, and the bit lines BL and /
The potentials of BL and sense amplifier outputs DO and / DO are returned to power supply voltage VDD.

As a result, the pMOS transistors 16, 1
7 = OFF and the nMOS transistor 22
Means that the potential of the node N6 is lowered to VDD-Vth22 to be turned off, and the nMOS transistor 23 is lowered to the potential of the node N7 to VDD-Vth23 to be turned off to return to the steady state until the next reading or writing. Become.

Here, the read operation when the node N2 in the memory cell 1 is at the L level and the node N3 is at the H level has been described. However, since the circuit is symmetrical, the node N2 is at the H level. The read operation in the case where the node N3 is at the L level is performed in the same manner as in the above case with the left and right being symmetrical.

As described above, according to the latch type sense amplifier 32 of the second embodiment of the present invention, since the capacitor 33 is connected between the nodes N6 and N7, the threshold voltage Vth22 of the nMOS transistors 22 and 23 is Vth
Even if there is an imbalance in 23, the source potentials of the nMOS transistors 22 and 23 are set to a potential at which the latch operation can be performed normally, compared with the case of the latch type sense amplifier 25 of the first embodiment of the present invention. Can also be set in a short time.

Therefore, the nMOS transistor 22,
Even if the threshold voltages Vth22 and Vth23 of 23 are unbalanced, the latch of the data read from the memory cell is ensured and the latch-type sense amplifier 25 of the first embodiment of the present invention is used. Can also be done at high speed.

FIG. 8 and FIG. 9 FIG. 8 is a circuit diagram showing a part of an SRAM having a latch type sense amplifier according to a third embodiment of the present invention.
The portion denoted by reference numeral 36 is the latch type sense amplifier according to the third embodiment of the present invention.

The latch type sense amplifier 36 according to the third embodiment of the present invention is configured such that the pMOS transistors 18 and 19 are turned on,
OFF is controlled by the internal clock CLK4 and nM
The ON and OFF of the OS transistors 20 and 21 are controlled by the internal clock CLK5.
It has the same configuration as the latch type sense amplifier 32 of the second embodiment of the present invention shown in FIG.

FIG. 9 is a waveform chart for explaining the operation of the latch type sense amplifier 36 according to the third embodiment of the present invention.
The potential of the word line WL and the internal clocks CLK1 to CLK
5, potentials of bit lines BL and / BL, sense amplifier outputs DO and / DO, and potentials of nodes N6 and N7 in latch type sense amplifier 36 according to the third embodiment of the present invention.

Also in this example, in the memory cell 1, p
MOS transistor 3 = OFF, pMOS transistor 4 = ON, nMOS transistor 5 = ON, nMOS transistor 6 = OFF, node N2 is at L level,
It is assumed that the node N3 is at the H level.

Here, in the SRAM including the latch-type sense amplifier 36 according to the third embodiment of the present invention, before the time T1, which is the start timing of reading data from the memory cell 1, the word line WL and the internal clock CLK1 are output.
To CLK4 are at L level, and the internal clock CLK5 is at H level.

At time T1, which is the start timing of reading data from the memory cell 1, the word line WL and the internal clocks CLK1 and CLK3 are set to the H level.

Then, at time T2, which is the timing for driving the latch type sense amplifier 36 according to the third embodiment of the present invention.
, The internal clock CLK4 goes high and the internal clocks CLK3, CLK5
Are set to L level.

The time T2, which is the timing for driving the latch-type sense amplifier 36 according to the third embodiment of the present invention.
, The internal clocks CLK5 and CLK2 are set to the H level.

At time T3, which is the timing for terminating the driving of the latch type sense amplifier 36 according to the third embodiment of the present invention, the word line WL and the internal clock CL are turned off.
K1, CLK4, and CLK2 are at the L level.

Here, the word line WL and the internal clock C
In a steady state before time T1 when LK1 to CLK4 are at L level and the internal clock CLK5 is at H level, in the memory cell 1, the nMOS transistors 7 and 8 are OFF, and the bit line clamp circuit is turned off. 9
In pMOS transistors 12, 13 = ON,
In the latch type sense amplifier 36 according to the third embodiment of the present invention, the pMOS transistors 18 to 21 = ON, nM
The OS transistors 26 to 29 are turned off.

As a result, the bit lines BL and / BL are clamped to the power supply voltage VDD via the pMOS transistors 12 and 13, respectively, and the sense amplifier outputs DO and / D
O is also clamped to the power supply voltage VDD and the node N
6 is in a high impedance state at (VDD-Vth22) or higher potential, and the node N7
Is in a high impedance state at (VDD-Vth23) or higher.

At time T1, which is the start timing of reading data from memory cell 1, word line W
When L and the internal clocks CLK1 and CLK3 are set to H level, in the memory cell 1, the nMOS transistors 7, 8 = ON, and in the bit line clamp circuit 9,
The pMOS transistors 12 and 13 are turned off, and the bit lines BL and / BL are connected to the memory cell 1 and released from the bit line clamp circuit 9.

As a result, a cell current flows from bit line BL through nMOS transistors 7 and 5, and bit line BL
Is discharged, and the potential of the bit line BL is slowly lowered from the power supply voltage VDD.

On the other hand, the potential of node N3 in memory cell 1 is maintained at power supply voltage VDD, so that bit line / BL
Is not discharged, and the potential of the bit line / BL is maintained at the power supply voltage VDD.

In the latch type sense amplifier 36 according to the third embodiment of the present invention, the nMOS transistor 2
7, 29 = ON, the nMOS transistors 27, 2
9, the small drain currents I27 and I29 flow, and the potential of the node N6 is reduced to VDD-Vth22-.DELTA.V27, and the potential of the node N7 is reduced to VDD-Vth23-.DELTA.V29.

As described above, ΔV27 is a voltage required for the nMOS transistor 22 to flow the minute current I27,
ΔV29 indicates that the nMOS transistor 23 has a small current I29.
Is necessary to supply the current, but since the nMOS transistors 27 and 29 have the same size,
29 have substantially equal current values, and ΔV27 and ΔV29 have substantially equal voltage values.

Then, at time T7, the internal clock CLK
4 is set to the H level, and the internal clocks CLK3,
When CLK5 is set to L level, the pMOS transistors 18 and 19 are turned off and the nMOS transistors 27 and 29 are turned off.
= OFF, pMOS transistors 20 and 21 = ON.

As a result, the potential of the sense amplifier output DO rapidly becomes the same potential as the bit line BL from the power supply voltage VDD. On the other hand, the sense amplifier output / DO is connected to the bit line / B
It is maintained at the same potential as L, that is, the power supply voltage VDD.

The potential of the node N6 returns toward VDD-Vth22, and the potential of the node N7 returns toward VDD-Vth23.

As in the case of the latch type sense amplifier 32 according to the second embodiment of the present invention, the sense amplifier output D
At time T2 when O drops by ΔVBL from the power supply voltage VDD, the potential of the node N6 returns to VDD−Vth22−ΔV, and the potential of the node N7 returns to VDD−Vth23−ΔV.

Therefore, at time T2 when the sense amplifier output DO drops by ΔVBL from the power supply voltage VDD, the gate-source voltage Vgs of the nMOS transistor 22 becomes VDD− (VDD−Vth22−ΔV) = Vth22 + ΔV, and the nMOS transistor The gate-source voltage Vgs of 23 is: VDD−ΔVBL− (VDD−Vth23−ΔV) = Vth
23 + ΔV−ΔVBL.

Then, the timing for driving the latch type sense amplifier 36 according to the third embodiment of the present invention, that is, the time when the potential difference ΔVBL between the bit lines BL and / BL becomes a certain value (for example, about 100 mV). T2
When the internal clocks CLK5 and CLK2 are set to the H level, the pMOS transistors 20 and 21 are turned off, the nodes N4 and N5 are disconnected from the bit lines BL and / BL, and the nMOS transistors 26 and 28 are turned off.
N, and the potentials of the nodes N6 and N7 are reduced to the ground potential GND.

Here, the gate-source voltage Vgs of the nMOS transistor 22 is set to Vth22 + ΔV, and the nMOS transistor 22 is already in a shallow ON state.
Immediately turns on completely. On the other hand, nMOS
The transistor 23 has a gate-source voltage Vgs of Vth23 + ΔV−ΔVBL.
It turns on later than the transistor 22.

As described above, in the latch type sense amplifier 36 according to the third embodiment of the present invention, when (the potential of the bit line BL) <(the potential of the bit line / BL), the nMOS
The threshold voltage Vth2 of the transistors 22 and 23
2. Irrespective of the imbalance of Vth23, the nMOS transistor 22 is turned on first and the sense amplifier output DO
Will be reduced rapidly.

On the other hand, nMOS transistor 23
Starts turning on later than the nMOS transistor 22 and starts lowering the sense amplifier output / DO. However, since the sense amplifier output DO applied to its gate is rapidly lowered by the nMOS transistor 22, it turns off immediately. , The sense amplifier output / DO is not reduced.

On the other hand, before the latch type sense amplifier 36 of the third embodiment of the present invention is driven, p
Of the MOS transistors 16 and 17, the pMOS transistor 17 whose gate is supplied with the sense amplifier output DO which is rapidly lowered is turned on, and the sense amplifier output / DO is returned to the power supply voltage VDD.

Since the pMOS transistor 16 returns to the power supply voltage VDD immediately after the sense amplifier output / DO applied to the gate is slightly lowered,
The sense amplifier output DO remains at the node N6
Does not prevent the voltage from being lowered to the ground voltage GND.

As described above, the latch type sense amplifier 36 according to the third embodiment of the present invention amplifies the minute voltage difference ΔVBL between the bit lines BL and / BL, and outputs the GND level sense amplifier output DO and VDD. The level of the sense amplifier output / DO is output. The sense amplifier outputs DO and / DO output from the latch type sense amplifier 36 according to the third embodiment of the present invention are sent to a latch circuit (not shown) and output outside the SRAM.

Then, at time T3 which is the timing to end the driving of the latch type sense amplifier 36 according to the third embodiment of the present invention, the word line WL and the internal clock CLK are reached.
When CLK1, CLK4 and CLK2 are set to L level, in the memory cell 1, the nMOS transistors 7, 8 = OF
F, and the memory cell 1 is disconnected from the bit lines BL and / BL.

In the bit line clamp circuit 9, the pMOS transistors 12 and 13 are turned on. In the latch type sense amplifier 36 according to the third embodiment of the present invention,
The nMOS transistors 26 and 28 = OFF, the pMOS transistors 18 and 19 = ON, and the bit lines BL and /
The potentials of BL and sense amplifier outputs DO and / DO are returned to power supply voltage VDD.

As a result, the pMOS transistors 16, 1
7 = OFF and the nMOS transistor 22
Means that the potential of the node N6 is lowered to VDD-Vth22 to be turned off, and the nMOS transistor 23 is lowered to the potential of the node N7 to VDD-Vth23 to be turned off to return to the steady state until the next reading or writing. Become.

Here, the read operation when the node N2 in the memory cell 1 is at the L level and the node N3 is at the H level has been described. However, since the circuit is symmetrical, the node N2 is at the H level. The read operation in the case where the node N3 is at the L level is performed in the same manner as in the above case with the left and right symmetrical.

As described above, according to the latch type sense amplifier 36 of the third embodiment of the present invention, the capacitor 33 is connected between the nodes N6 and N7, and the bit lines BL and /
During the period until the voltage difference ΔVBL between BLs is sufficiently opened (period from time T1 to time T2), the potentials of the nodes N6 and N7 can be controlled so as to be temporarily reduced, so that before the time T1. Even if there is no need to perform any operation and the threshold voltages Vth22 and Vth23 of the nMOS transistors 22 and 23 are unbalanced, the source potentials of the nMOS transistors 22 and 23 are set to potentials at which the latch operation can be performed normally. In addition, it can be set in a shorter time than in the case of the latch type sense amplifier 32 of the second embodiment of the present invention.

Therefore, the nMOS transistor 22,
Even when the threshold voltages Vth22 and Vth23 of 23 are unbalanced, the latch of the data read from the memory cell can be surely performed and the latch type sense amplifier 32 of the second embodiment of the present invention can be used. Can also be done at high speed.

Here, when the contents of the present invention are arranged, the present invention includes at least the following latch type sense amplifier.

(1) A pair of first conductivity type field-effect transistors whose gates and drains are cross-connected, and each pair of field-effect transistors is connected between each drain and a first power supply. A third pair of load means, a first pair of switch means, a second pair of switch means connected between a source of each of the pair of field effect transistors and a second power supply, and a high resistance; And a pair of switch means.

(2) In the latch type sense amplifier according to the above (1), the pair of load means are a pair of second conductivity type field effect transistors having respective gates and drains cross-connected. The first pair of switch means is a pair of field effect transistors of the second conductivity type, and the second pair of switch means is a pair of field effect transistors of the first conductivity type, and the third pair of Wherein the switch means is a pair of first conductivity type field effect transistors having a small drain current.

(3) In the latch type sense amplifier according to the above (1) or (2), a capacitor is provided between a source of the pair of first conductivity type field effect transistors, each of which has a gate and a drain cross-connected. A latch-type sense amplifier which is connected.

(4) In the latch type sense amplifier according to the above (3), the capacitor is a first and a second M.
A latch-type sense amplifier, comprising an OS capacitor connected in parallel so that gates are not connected to each other.

(5) In the latch type sense amplifier according to (4), the first conductivity type MOS transistor is an nMOS transistor, and the second conductivity type MOS transistor is
An OS transistor is a pMOS transistor, and the first power supply has a higher potential than the second power supply.

[0168]

As described above, according to the present invention, before the start of the latch operation, the first and third pair of switch means are temporarily turned on, and the pair of field effect transistors forming the driving element are temporarily turned on. Even when the threshold voltage of the pair of field effect transistors forming the driving element is imbalanced by flowing a small current, the source potential of the pair of field effect transistors forming the driving element can be normally latched. Can be set to a potential at which the complementary signal having a small voltage difference can be latched.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of an SRAM including a latch type sense amplifier according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining an operation of the latch type sense amplifier according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining the operation of the latch type sense amplifier according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a part of an SRAM including a latch type sense amplifier according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a capacitor included in a latch type sense amplifier according to a second embodiment of the present invention.

FIG. 6 is a waveform chart for explaining an operation of the latch type sense amplifier according to the second embodiment of the present invention.

FIG. 7 is a circuit diagram for explaining an operation of the latch type sense amplifier according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a part of an SRAM including a latch type sense amplifier according to a third embodiment of the present invention.

FIG. 9 is a waveform chart for explaining an operation of the latch type sense amplifier according to the third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a part of an SRAM including an example of a conventional latch type sense amplifier.

FIG. 11 is a waveform diagram for explaining the operation of the conventional latch-type sense amplifier shown in FIG.

FIG. 12 is a circuit diagram for explaining a problem that the conventional latch-type sense amplifier shown in FIG. 10 has.

[Explanation of symbols]

 WL Word line BL, / BL Bit line CLK1 to CLK5 Internal clock DO, / DO Sense amplifier output

Claims (1)

[Claims] A pair of field-effect transistors each having a gate and a drain cross-connected to each other; a pair of load means connected between each drain of the pair of field-effect transistors and a first power supply; A pair of switch means, a second pair of switch means connected between a source of each of the pair of field effect transistors and a second power supply, and an ON resistance value of the second pair of switch means. A latch type sense amplifier, comprising: a third pair of switch means having a higher on-resistance value.