JP2001075521A - Error spread processing method of display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce picture interference such as periodical pattern noise that appears during an error spread processing. SOLUTION: An inverse gamma compensating circuit 2 performs inverse gamma compensation for 8 bit R, G and B signals with 12 bits. An error spread processing circuit 3 performs error spread for low-order 4 bits of the 12 bit R, G and B signals, and inputs the signals equivalent 12 bit into a plasma display panel(PDP) 4. In the circuit 3, an error spread coefficient for at least one signal of the R, G and B signals is made different from the error spread coefficients for other signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error diffusion processing method used for a display device, and more particularly to a plasma display panel display device (PDP), a field emission display device (FED), a digital micromirror device (DMD), 2. Description of the Related Art In a display device such as an electroluminescence display (EL) that expresses digitally limited intermediate gradations, a display capable of reducing image quality disturbance caused by multi-gradation processing by error diffusion processing. The present invention relates to an apparatus error diffusion processing method.

[0002]

2. Description of the Related Art Among display devices for displaying video signals, for example, a PDP which divides one field into a plurality of subfields to display gradations, an FED which displays gradations by pulse width modulation (PWM), and an FED. In a matrix type display device such as a DMD, an image can be expressed only with a digitally limited number of gradations depending on a driving method. In addition, it is necessary to perform inverse gamma correction processing on the video signal to which the gamma characteristic has been applied to return to a linear gradation.

In these display devices, there are cases where the number of gradations (the number of bits) of the input signal is larger than the number of gradations (the number of bits) that can be expressed by the display device. In some cases, the number of tones (bits) expressed by the display device is intentionally reduced from the number of tones (bits) of the input signal.

Further, when the inverse gamma correction circuit performs an inverse gamma correction process to return to a linear gradation, the number of bits may be once higher than the number of bits that can be expressed by a display device. This is for the following reasons. When the inverse gamma correction process is performed to return to a linear gradation, the number of gradations at a low luminance level may be damaged, and image quality may often be disturbed due to loss of gradation continuity. In particular, PDP
In the case of (1), one field is composed of a plurality of subfields having different weights of the light emission amount, and the gradation is expressed by selecting a plurality of the subfields. Therefore, depending on the selection condition of the subfield, the visual luminance difference with respect to the adjacent gray scale becomes large, and as a result, a pseudo contour-like image quality disturbance may occur. Therefore,
In order to prevent the gradation from being impaired as much as possible, inverse gamma correction may be performed with a bit number higher than the bit number of the original signal, and the bit number may be increased for output.

[0005] As described above, the number of bits of the input video signal or the number of bits of the video signal output from the inverse gamma correction circuit (the first number of gradations) corresponds to the number of bits expressed by the display device (the second number of gray levels). If it is larger than the number of gradations, the number of bits (the number of gradations) needs to be reduced.
If the number of bits is reduced, the gradation is impaired, so that the multi-gradation processing is performed by using the error diffusion method.

The multi-gradation processing by the error diffusion method is as follows, as an example, in order to obtain an image corresponding to the first number of gradations exceeding the digitally restricted second number of gradations. To do. In FIG. 4, P is one of the three dots constituting the target pixel, and is a dot having a gradation that cannot be expressed as it is with the second number of gradations. A is a dot on the right, B is a dot on the lower left, C is a dot on the lower right, and D is a dot on the lower right. As shown in FIG. 4, by spreading a plurality of peripheral dots A to D with a certain weight, the first number of gradations−the second number of gradations, which cannot be expressed in the target dot P, is apparent. In addition, a general method is to perform a multi-gradation process so that an image corresponding to the first number of gradations is obtained.

For example, if the display device has only 8-bit gradation capability and performs gradation display using the upper 8 bits of 12-bit dot data, a certain weight is given to the remaining lower 4 bits of dot data. By performing diffusion to the peripheral dots A to D, a gradation display equivalent to 12 bits is performed using a visual integration effect. In FIG. 4, 7/16, 3/16, 5/16, 1/1 added to the peripheral dots A to D.
6 is an example of an error diffusion coefficient indicating the degree of weighting. Note that a common error diffusion coefficient is used for the three primary color signals of R, G, and B.

[0008]

In the case of the above-described display device, particularly, a PDP, the apparent number of gradations is reduced by performing the multi-gradation processing by the error diffusion method as described above. In addition, the image disturbance of the pseudo contour is reduced. However, in the past,
Since a common error diffusion coefficient is used for the three primary color signals of R, G and B, by performing error diffusion, especially when displaying a fixed pattern or the like, periodic pattern noise or the like peculiar to error diffusion is used. However, there is a problem that image quality interference may occur.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an error diffusion processing method for a display device capable of reducing image quality disturbance such as periodic pattern noise that appears when performing error diffusion processing. The purpose is to provide.

[0010]

According to the present invention, in order to solve the above-mentioned problems of the prior art, R, G, and B signals having a first number of gradations are processed at a higher frequency than the first number of gradations. In reducing the number of gradations to a second number of gradations having a small number of tones, the first gradation in each pixel of interest constituted by dots of R, G, and B signals is used.
The error data obtained by multiplying the difference between the number of gradations and the second number of gradations by a predetermined error diffusion coefficient to a plurality of peripheral pixels of the target pixel. At least one of the R, G, B signals at
It is an object of the present invention to provide an error diffusion processing method for a display device, wherein an error diffusion coefficient for one signal is made different from an error diffusion coefficient for another signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an error diffusion processing method for a display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of a display device using the error diffusion processing method of the present invention, FIG. 2 is a block diagram showing a specific configuration example of an error diffusion processing circuit 3 in FIG. 1, and FIG. FIG. 3 is a diagram for explaining an example of an error diffusion processing method according to the present invention.

In this embodiment shown in FIG. 1, a case is shown in which a PDP is used as a matrix type display device capable of expressing an image only with a digitally limited number of gradations. Of course, as the display device of the present invention, a PD
It is not limited to P. In FIG. 1, R, G,
The three-system video signal composed of the B signal is input to the video signal processing circuit 1. The video signal processing circuit 1 performs various video signal processing on these video signals, and performs an inverse gamma correction circuit 2
To enter. The R, G, and B signals are 8-bit digital signals, for example, signals of 256 gradations.

The inverse gamma correction circuit 2 receives the input R,
The G and B signals are respectively subjected to inverse gamma correction processing having the same characteristics, and output as a 12-bit digital signal, that is, a signal of 1024 gradations, for example. The output of the 8-bit digital signal as a 12-bit digital signal is to prevent the number of gradations from being impaired by the inverse gamma correction processing as described above.

R, output from the inverse gamma correction circuit 2,
The G and B signals are input to the error diffusion processing circuit 3. The error diffusion processing circuit 3 includes an error diffusion processing circuit 3R for R, an error diffusion processing circuit 3G for G, and an error diffusion processing circuit 3B for B, and the R, G, and B signals are respectively processed by the error diffusion processing circuits 3R, 3G. , 3B. Error diffusion processing circuit 3
R, 3G, and 3B perform error diffusion processing on the input R, G, and B signals, and output the processed signals. That is, for example, the lower 4 bits of the 12-bit digital signal are replaced with the upper 8 bits.
The signal is spread into bits and output as an 8-bit digital signal.

At this time, the error diffusion processing circuits 3R, 3G,
3B does not use a common error diffusion coefficient, but makes different error diffusion coefficients used in at least one circuit.
That is, the present invention does not use the common error diffusion coefficient for the R, G, and B signals, but makes the error diffusion coefficient for any one of the signals different from the error diffusion coefficient for the other signals. It is characterized in that the error diffusion coefficients for the G and B signals are all different.

The R, G, B signals subjected to the error diffusion processing by the error diffusion processing circuits 3R, 3G, 3B are input to the PDP 4. The PDP 4 displays an R, G, B signal on a screen after performing drive circuit processing such as subfield processing.

Here, the error diffusion processing circuit 3 will be described with reference to FIG.
Is described below. The R error diffusion processing circuit 3R, the G error diffusion processing circuit 3G, and the B error diffusion processing circuit 3B have the same configuration, but have different error diffusion coefficients. Therefore, the G error diffusion processing circuit 3
The configuration of the G and B error diffusion processing circuits 3B is the same as that of the R error diffusion processing circuit 3R, so that the illustration is simplified and the description of the operation is omitted.

In FIG. 2, a 12-bit R signal input from the inverse gamma correction circuit 2 is added to an adder 31, which will be described later.
32, and the lower 4 bits of the 12-bit data output from the adder 32 are used for the R error detection circuit 3.
Input to 3R. The lower 4 bits correspond to a difference in gradation lost by reducing a 12-bit digital signal (1024 gradations) to an 8-bit digital signal (256 gradations). R error detection circuit 33R
FIG. 3 shows that the input lower 4 bits
The error data is generated by multiplying an error diffusion coefficient corresponding to the peripheral dots A 'to D' shown in FIG.

Terminals a to d shown in the R error detection circuit 33R
Output error data obtained by multiplying the lower 4-bit data by an error diffusion coefficient corresponding to the peripheral dots A 'to D'. In the case of FIG. 3A, error data obtained by multiplying the lower 4 bits of data by 7/16, 3/16, 5/16, and 1/16 are output from the terminals a to d, respectively. You. The relationship between the peripheral dots A 'to D' and the peripheral dots A to D will be described later.

The error data output from the terminal a is input to the adder 32, the error data output from the terminal b is input to the adder 35, and the error data output from the terminals c and d are input to the adder 34. Is entered. The adder 34 adds the input error data from the terminals c and d and inputs the result to the adder 35. The adder 35 adds the error data output from the terminal b and the output of the adder 34 and inputs the result to the line memory 36. The line memory 36 inputs the output of the adder 35 to the adder 31 with a delay slightly shorter than one line.

The adder 31 adds the input R signal and the output of the line memory 36 and inputs the result to the adder 32.
Assuming that the input R signal is a target dot P ′ shown in FIG. 3A, the adder 31 adds, to the target dot P ′, a line memory 36 that is error data generated by approximately one line in the past.
, Ie, B ′ × 3/16 + C ′ × 5/16 + D ′
An operation of adding × 1/16 is performed.

The adder 32 adds the output of the adder 31 and the error data output from the terminal a of the R error detection circuit 33R. That is, the adder 32 adds the error data generated approximately one line in the past to the target dot P 'to the output of the adder 31, and further adds the error data A' × An operation of adding 7/16 is performed. As described above, the error data obtained by multiplying the peripheral dots A 'to D' by the respective error diffusion coefficients are added to the target dot P 'shown in FIG. Of the 12-bit data output from the adder 32, the lower 4 bits are further input to the R error detection circuit 33R, and the above operation is repeated.

The upper 8 bits of the 12-bit data output from the adder 32 are input to the limiter 37. The limiter 37 restricts and outputs an amount (overflow) where the value of the data obtained by adding the error data to the target dot P ′ exceeds 8 bits.

As described above, the sequential addition of the error data to the target dot P 'is performed for each dot. As a result, as shown in FIG. 7/16, 3/16, 5 /
The peripheral dot A is multiplied by an error diffusion coefficient of 16, 1/16.
~ D.

In the example shown in FIG. 2, the error diffusion coefficient set in the G error detection circuit 33G in the G error diffusion processing circuit 3G is the same as the error diffusion coefficient set in the R error detection circuit 33R. The error diffusion coefficient set in the B error detection circuit 33B in the error diffusion processing circuit 3B is different from the error diffusion coefficient set in the R error detection circuit 33R and the G error detection circuit 33G. As shown in FIG. 3B, for the B signal, the data of the lower 4 bits of the dot of interest P is multiplied by error diffusion coefficients of 9/16, 2/16, 4/16, and 1/16. Diffusion is performed to the peripheral dots A to D.

In this manner, the error diffusion processing circuits 3R,
3G and 3B have different error diffusion coefficients for one or all of the R, G, and B signals in a target pixel composed of three dots of R, G, and B signals. By subjecting the signal to error diffusion processing,
The 12-bit data is output as 8-bit data. Note that all of the error diffusion coefficients for the peripheral dots A to D may be different, or only some of them may be different. In the example of FIG. 3, the error diffusion coefficient for the peripheral dots D is 1/16, which is common, and the error diffusion coefficients for the other peripheral dots A to C are different. Note that it is better to make the error diffusion coefficients slightly different from each other rather than greatly different.

As described above, in the present invention, even in the PDP 4 having only the 8-bit display capability, an image which can be apparently recognized as a display image equivalent to 12 bits is displayed by utilizing the visual integration effect. can do. Since a common error diffusion coefficient is not used as an error diffusion coefficient for the R, G, and B signals, even when displaying a fixed pattern or the like, image quality disturbance such as periodic pattern noise peculiar to error diffusion is visually recognized. Hard to do. Therefore, a high-quality display device can be provided.

[0028]

As described above in detail, the error diffusion processing method of the display device according to the present invention comprises an error diffusion coefficient for at least one signal for R, G and B signals, and an error diffusion coefficient for another signal. Since the difference is made, it is possible to reduce image quality disturbance such as periodic pattern noise that appears when the error diffusion processing is performed. Therefore, a display device with high image quality can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a display device using the present invention.

FIG. 2 is a block diagram showing a specific configuration example of an error diffusion processing circuit 3 in FIG.

FIG. 3 is a diagram illustrating an example of the present invention.

FIG. 4 is a diagram for explaining a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal processing circuit 2 Inverse gamma correction circuit 3 Error diffusion processing circuit 3R Error diffusion processing circuit for R 3G Error diffusion processing circuit for G 3B Error diffusion processing circuit for B 4 Plasma display panel display device

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[Procedure amendment]

[Submission date] October 19, 1999 (1999.10.
19)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

The inverse gamma correction circuit 2 receives the input R,
The G and B signals are subjected to inverse gamma correction processing having the same characteristics, and output as a 12-bit digital signal, that is, a signal of 4096 gradations, for example. The output of the 8-bit digital signal as a 12-bit digital signal is to prevent the number of gradations from being impaired by the inverse gamma correction processing as described above.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

In FIG. 2, a 12-bit R signal input from the inverse gamma correction circuit 2 is added to an adder 31, which will be described later.
32, and the lower 4 bits of the 12-bit data output from the adder 32 are used for the R error detection circuit 3.
Input to 3R. The lower 4 bits correspond to a difference in gradation lost by reducing a 12-bit digital signal ( 4096 gradations) to an 8-bit digital signal (256 gradations). R error detection circuit 33R
FIG. 3 shows that the input lower 4 bits
The error data is generated by multiplying an error diffusion coefficient corresponding to the peripheral dots A 'to D' shown in FIG.

Claims (1)

[Claims] When reducing R, G, B signals having a first number of gradations to a second number of gradations having a smaller number of gradations than the first number of gradations, R, G, B The first number of gradations and the second
An error data obtained by multiplying a difference from the number of gradations by a predetermined error diffusion coefficient to a plurality of peripheral pixels of the pixel of interest, wherein the R, G, and B signals of the pixel of interest are An error diffusion coefficient for at least one of the signals is different from an error diffusion coefficient for another signal.