JP2001069464A - Video signal reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a search picture that can be expressed in a natural motion by means of an image more easily be recognized in an HDD recorder or a DVD. SOLUTION: An I picture recorded in an MPEG-2 bit stream recorded in a hard disk 61 for each GOP is intermittently read, a read picture is divided in a vertical direction, any of them is selected and when the selected picture is stored in memory circuits 71A 3g, i, every time the selected picture among the divided picture is changed cyclicly to store the entire picture. Reading the entire pictures dividedly stored cyclicly can generate and display a search picture that can easily and visually be recognized and express a temporal motion change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal reproducing device, and more particularly to a device for reproducing a video signal recorded on a hard disk and reproducing a DVD so that a natural search image can be obtained.

[0002]

2. Description of the Related Art Conventionally, as a device for recording and reproducing a video signal, a device for encoding, recording, and reproducing a video signal by the MPEG system has been used. The MPEG system is an international standardization organization
SO / IEC moves to MPEG (Moving Picture Experts Gro
up) to establish an international standard for video coding and to establish a method to encode generated video signals with high efficiency. We are building an infrastructure to handle signals.

[0003] The encoding standard for moving pictures defined by the organization by MPEG is also called the MPEG standard.
The G standard method is a code that combines a method of reducing redundancy of spatial information performed by using a DCT (Discrete Cosine Transform) method and a method of reducing redundancy of temporal information performed by using a motion prediction method. It can be roughly considered as a generalization method.

[0004] In general encoding of a video signal by the MPEG system, a video signal composed of 30 frames per second is divided in units of 15 frames, and an image of the first frame of the first divided unit is divided. , And assigning the number of quantization bits to the DCT coefficient obtained by the operation,
Generates a compressed bit stream signal by encoding using a method such as Huffman coding that reduces redundancy of the code itself, as well as representation by a run-length encoding of a code string allocated and transmitted , For the images of the second to fifteenth frames, motion prediction is performed based on the image of the first frame, and a motion vector expressing the amount of movement of the image and a residual signal generated by changing the image are obtained. The residual signal is subjected to the same encoding as described above for DCT operation processing, and the images of the second to fifteenth frames obtain encoded data having a higher compression ratio than the compression ratio of the first frame, and In addition to the transmission data obtained by encoding the frame image, data of an encoded bit stream in units of 15 frames is obtained.

As described above, a digital video signal sequentially input in this manner is divided into, for example, every 15 frames, and encoding is performed in units of the divided video signal. GOP (Group of Pictu)
re), and encoding is performed for each of 15 frames of images forming the GOP, that is, for every 15 pictures. In the encoding process, the 15 frames of images are classified into three types of pictures. An encoding process is performed.

[0006] Three types of pictures for performing the encoding process include an I picture (Intra Coded Picture), a P picture (Predictive-coded Picture), and a B picture.
Picture (Bidirectionally predictiv
e-coded Picture), and the I picture treats one frame image as one still image, and performs encoding independently without regard to the preceding and following frame images.
The P picture is the P picture before or immediately before this I picture.
A picture is encoded using a one-way prediction method in terms of time, and a B picture is encoded using a two-way prediction method in terms of time from two image data of past and future I or P pictures. I do it.

FIG. 14 shows an example of the configuration of a GOP which is encoded as described above. In the figure, the shapes indicated by oblique squares indicate pictures, and each of them has the above-mentioned I
Picture, P-picture, and B-picture names are given, and at the start of encoding, a GOP extends from an I picture to a position immediately before the next I picture. P picture, B
A curved arrow is attached to the picture, and the arrow indicates the direction of image prediction. The P picture is coded by prediction from the preceding I picture or another P picture, and the B picture is on both sides. Is performed by bidirectional prediction using an I picture and a P picture or a P picture and another P picture.

[0008] The data encoded in this manner is recorded on a recording medium or transmitted using a communication channel. The decoding of the transmitted data at the receiving terminal first decodes an I picture, then decodes the P picture. The picture is decoded while performing unidirectional motion prediction from the already decoded I picture, and then the B picture is subjected to bidirectional motion prediction using these obtained P picture and I picture or two P pictures. While decrypting.

When the encoded bit stream is decoded, if the reproduction speed is the normal speed, all the I, P, and B pictures encoded in this manner are decoded and obtained. All pictures are displayed, but when the playback is performed as if searching for a high-speed image similar to the high-speed playback function of a VTR or the like, for example, an I-picture and a P-picture are Alternatively, only the I picture is selected, decoded, and displayed.

The pictures to be selected are an I picture and a P picture.
If the picture is a picture, one picture is selected and displayed for every three pictures, which corresponds to high-speed playback at 3 × speed. When only I pictures are selectively read and played, the playback speed is selected. Are displayed in the same manner as in the case of the high-speed reproduction of 15 times speed.

As described above, when performing high-speed reproduction by decoding a part of data encoded by the MPEG system,
It is generally performed using an I-picture, which requires less time for decoding, and a P-picture, if necessary, for recording a DVD and a hard disk for recording a bit stream created by the MPEG-2 system. When a high-speed reproduced image is displayed as a search image in a video signal recording / reproducing device such as an HDD recorder used as a medium, an I picture is read and decoded, and the decoded image signal is displayed as a signal of a frame constituting a video signal. High-speed reproduction is performed by displaying as a signal for one field of a frame signal composed of two fields.

FIG. 15 shows a first search image display example for displaying a signal decoded in this way. In the figure, squares consecutively numbered and attached are shown sequentially in order of image signals in GOP units, and the squares shown in the lower side represent images to be reproduced at high speed.
For example, when a video signal is displayed on a monitor screen, an image to be decoded and displayed for a frame unit image of the video signal is indicated by a GOP number. MPE
In the normal encoding by G-2, a GOP is divided in units of 15 frames. In the case of a standard television signal based on 525 lines in Japan and the United States, an image of 30 frames is displayed per second, so that one GOP is displayed. GOPs will be present at 0.5 second intervals.

In the example shown in FIG. 1, one for every two GOPs
The I-pictures are decoded and displayed at intervals of two frames. At that time, the playback speed of the search image is 2 frames.
The standard reproduction time of one GOP is one second, and this is divided by 66.7 milliseconds, which is the display time at the time of the search, to obtain 15 as the display speed of the search image. In this example two GOs
One I picture is decoded for each P because the time required for decoding the I picture requires 33.3 milliseconds or more. At that time, the image of the I picture is decoded from the hard disk. The time required to read the bit stream required for the
It is 5 times faster.

Here, in the future, when the decoding time of an I picture is reduced by improving the decoder and the reading speed of the bit stream is reduced by improving the hard disk, the image of the I picture included in one GOP will be reduced. Can be decoded and displayed within one frame time, in which case a search image with more smooth motion can be reproduced.

FIG. 16 shows a second search image display example for displaying at 15 × speed using an improved MPEG-2 decoder and a hard disk. In the figure, the upper side numbers the video signals in GOP units, and the lower side numbers the images in frame units,
In this case, I pictures included in each GOP are decoded, and the decoded images are displayed frame by frame.
Therefore, a search image of 15 times speed is displayed.

As described above, the I picture included in the GOP is decoded by the first and second search image display examples, and the I picture obtained over one frame period or two frame periods of the standard television signal is obtained. A picture of a picture was displayed, and it was shown that a high-speed playback image of a bit stream encoded by MPEG could be displayed. However, according to such a method, even when the decoding capability of the MPEG-2 decoder is high and an I picture can be decoded within one frame period, when the display image is updated every frame period, If the visual correlation between the updated images is low, the images are displayed as a series of still images that are hardly recognized by human eyes as ordinary moving images.

The reason for displaying as a series of still images is that, when recording and reproducing a general moving image, images transmitted in adjacent frames have high visual correlation, but frames which are separated from each other by time. This is because the longer the distance between the frames is, the lower the correlation between the two images becomes. In the bit stream coded by the MPEG system, in order to perform a high-speed search, the more the GOPs are skipped, the longer the distance on the time axis of the I picture to be decoded becomes, and an image with low correlation is displayed for each frame. Therefore, in a search image in which an I picture is displayed as it is, a change of a scene or a content of an image is often invisible to human eyes. Therefore, in order to make it easy for human eyes to understand the contents of the I picture constituting the search image, there is a method of solving the problem by, for example, displaying the same I picture image over a plurality of frames.

FIG. 17 shows a third search image display example for obtaining a 30 × search image in which the same I-picture image is displayed continuously over a plurality of frames. In the figure, one I picture is decoded for every eight GOPs, and the decoded I picture is displayed over four frames. The search image by such a method is 4
The I picture coded at a rate of one per second is decoded, and the decoded I picture is displayed for 133 milliseconds over four frames, so that a 30 × speed search image is displayed.

In the method according to the third search image display example, since the same image is displayed for 133 milliseconds during a period of four frames, the viewer can easily recognize each image. However, the image looks like a still image being displayed at random and at regular intervals. It is the I picture being displayed,
This is because images for the seven GOPs present between the next I-pictures to be displayed are not displayed at all, and have a drawback that the flow of change of the moving image, that is, the temporal movement of the image is difficult to see. It is due to.

For example, to obtain a 30 × speed search image from a bit stream obtained by encoding a movie by this method,
There are seven GOPs to be skipped, and 105-frame (picture) images are not displayed at all for 3.5 seconds between them. Therefore, it is difficult to grasp the contents of the movie while looking at the search image, and it is difficult to search for the location of the target image in the search operation. The difficulty in locating such an image increases as the search speed increases.

[0021]

By the way, in the search image by the high-speed reproduction shown in the above-mentioned conventional example, a normal I-picture image exists only at a rate of one in 15 frames. Since the amount of data of an I-picture having a low compression rate without processing by motion prediction is larger than that of a P-picture or a B-picture, the I-picture is selected, read from a recording medium, and decoded. This requires a relatively large amount of time.

When an I-picture can be decoded at a speed of 30 frames or more per second with an expensive decoder with an improved decoding time, a search image by high-speed reproduction is one.
Since a different I-picture image can be displayed for each frame, a reproduced image at 15 × speed can be obtained.
The time required for decoding a picture or the like is often insufficient for one frame period, and the decoded I-picture image is used over a plurality of display frame periods and is repeatedly displayed. However, even in a reproduced image displayed in such a manner, an independent still image appears as if discontinuously updated discontinuously, and it is difficult to understand the temporal connection of the images. It is difficult to sense the change.

In this case, if the search speed is further increased, it is necessary to thin out and decode the I-pictures, so that the displayed video looks as if the still image has been renewed more than before. In other words, it becomes difficult to determine whether the direction of the movement is the forward direction or even the reverse direction, and the disadvantages of such a method are further increased. I will. This kind of appearance is similar to a conventional analog VTR
Is very different from the appearance of the high-speed search screen.

FIG. 18 shows the operation of high-speed reproduction in the analog VTR. In the figure, a video signal for one field according to a track pattern 111 is recorded on an analog video tape 110.
Normally, the video signal is obtained by tracing the reproducing head in the direction of the head tracing direction 121 during normal reproduction. For example, when performing high-speed reproduction at 6 × speed, the head is moved in the direction of the head tracing direction 122 during search. The analog video tape 110 is fast-forwarded so as to be traced, and a video head (not shown) is traced on the head trace pattern 121 at the time of search, so that the video head diagonally crosses the track pattern 111 on the analog video tape 110. I have a search image.

FIG. 19 shows how the search image reproduced and displayed in this manner is viewed on the monitor TV. a to f
Are displayed in order from the top of the monitor screen, and a search image in which information from track pattern a to track pattern f is arranged in chronological order is obtained.

Therefore, as described above, an I frame is selected from data encoded by the MPEG-2 system, and a search image and an analog VTR to be decoded and displayed are selected.
Comparing the search image obtained from the above, the image quality itself is higher in the case of the MPEG method because it is a digital image with less deterioration, but the motion appearance in the search image depends on the analog VTR described later. Thus, smooth high-speed playback images could not be expressed.

In the case of the MPEG system, it is possible to decode all I-picture images having a large data amount in a short time and decode and display I-picture images that sequentially arrive at each field frequency or frame frequency. However, since a normal MPEG-2 decoder cannot perform processing because of the processing time required for decoding, it is not possible to easily obtain a search image that can be expressed by natural motion, such as displaying an I-picture image in a thinned form. The search image method using I-pictures has not been used effectively.

Therefore, in the present invention, an I-picture image is converted from a bit stream that has been subjected to inter-frame coding processing and intra-frame coding processing in a predetermined block unit, for example, a bit stream coded according to the MPEG-2 system. Then, decoding is performed, a part of the decoded frame image is divided and written into the frame memory circuit, and a plurality of divided frame images are combined, so that temporal movement is relatively continuous. The purpose of the present invention is to obtain search images that can be expressed naturally and to provide an inexpensive configuration for creating those search images. The signal processing is not required, and the processing can be performed using a conventionally used ordinary decoder circuit.

Further, by sequentially writing the above-described decoded frame images into a plurality of frame memory circuits, dividing and writing the written frame images from the respective frame memories, and synthesizing the divided frame images, more temporal movement can be achieved. It is also intended to obtain a search image that can be expressed continuously and naturally.

[0030]

The present invention comprises the following means 1) and 2) to solve the above-mentioned problems. That is,

1) A video signal which is allocated in a predetermined order in an inter-frame encoding process and an intra-frame encoding process in a predetermined block, and which is data-compressed, is recorded on a predetermined recording medium, and the recorded video signal is recorded. In a video signal reproducing apparatus for reproducing a signal, based on reproduction speed information selected by a selection unit, a control unit for controlling a reproduction operation of the predetermined recording medium, and a reproduction speed control by the control unit, Medium reproducing means for reading a video signal from a recording medium, decoding means for decoding the video signal read from the medium reproducing means, and video signal generating means for displaying a signal decoded by the decoding means on a display; And the decoding means sequentially obtains the signals subjected to the intra-frame encoding processing from the predetermined recording medium, and obtains the sequentially obtained signals. A decoding unit that decodes the decoded digital frame image data to obtain digital frame image data, a write control unit that divides the decoded digital frame image data into digital image data of a plurality of areas, and A video signal reproducing device comprising: an image memory for storing in a plurality of corresponding areas.

2) A video signal which has been assigned a predetermined sequence of inter-frame encoding processing and intra-frame encoding processing in a predetermined order and which has been data-compressed is recorded on a predetermined recording medium. In a video signal reproducing apparatus for reproducing a signal, based on reproduction speed information selected by a selection unit, a control unit for controlling a reproduction operation of the predetermined recording medium, and a reproduction speed control by the control unit, Medium reproducing means for reading a video signal from a recording medium, decoding means for decoding the video signal read from the medium reproducing means, and video signal generating means for displaying a signal decoded by the decoding means on a display; And the decoding means sequentially obtains the signals subjected to the intra-frame encoding processing from the predetermined recording medium, and obtains the sequentially obtained signals. A decoding unit that decodes the decoded digital frame image data to obtain digital frame image data, a write control unit that sorts the decoded digital frame image data for each image data, and a plurality of storage units that store the sorted digital image data. A video signal reproducing device comprising an image memory.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a video signal reproducing apparatus 40 according to the first embodiment. The video signal reproducing device 40 receives a television broadcast or receives a video signal from a video input terminal.
The digital video signal compressed by the encoding is recorded on the hard disk 61. To reproduce the recorded signal, a signal read from the hard disk is supplied to the decoder unit 70, and the encoded digital video signal is decoded to obtain an analog video signal, and the video signal recorded on the hard disk 61 is reproduced. Is to generate a high-speed reproduction signal for displaying the time smoothly.

The structure of the apparatus shown in FIG. The encoder unit 50 includes a TV tuner 51 that receives a TV broadcast, and a video input terminal 5 that inputs a video signal.
2, a video signal changeover switch 53 for switching between these output signals, an A / D converter 54 for converting an analog signal into a digital signal, It comprises an MPEG-2 encoder 55 for obtaining a stream.

The decoder section 70 is provided with the TV tuner 5 described above.
1 channel selection, the aforementioned MPEG-2 encoder 5
5, a recording signal to be supplied to the hard disk 61,
Recording and playback operations of the hard disk 61, MPEG described later
The hard disk 61 and a CPU 72 connected to a ROM 73 and a RAM 74 for controlling the decoding operation of the -2 decoder 71, on-screen information generated by an on-screen display generation circuit 79 described later, and the operation of each unit such as a remote control interface 85 described later. M supplied
The above-described MPEG-2 decoder 71 for decoding a bit stream encoded by the PEG-2 method to obtain a digital video signal, a D / A converter 78 for converting the digital video signal into an analog video signal, and a TV tuner 5
An on-screen display generation circuit 79 for multiplexing and displaying various information, such as the operation status of the receiving channel of the hard disk 61, the operation state of recording and reproduction of the hard disk 61, the key operation state of the remote controller 95, etc. on the output signal to the monitor TV 90; A remote control interface 85 receives, for example, a modulated infrared signal emitted by the remote control 95 and supplies the received information to the CPU 72.

Next, the operation of the apparatus having the above configuration will be described. TV tuner 51 of encoder unit 50
, A signal coming from an antenna is supplied, a signal obtained by demodulating a signal of a reception channel selected by a remote controller 95 or the like is obtained and supplied to one terminal of a video signal changeover switch 53, and a video signal changeover is performed. A video signal from a video device (not shown) to be recorded on the hard disk 61 is supplied to the other terminal of the switch 53 through the video input terminal 52, and one of these signals is selected by the video signal changeover switch 53.
The selected analog video signal is supplied to an A / D converter 54 to obtain a signal converted to a digital video signal. The digital video signal is supplied to an MPEG-2 encoder 55,
A bit stream signal encoded by the PEG-2 method is generated, and the generated bit stream signal is supplied to the hard disk 61.

The hard disk 61 records a bit stream supplied in response to a command from the CPU 72,
The operation of the recording / reproducing system configured by using the hard disk 61 is controlled by the CPU 72 while the hard disk 61 having excellent accessibility is provided.
, While playing, recording,
A bit stream for providing a search function while displaying a reproduced image to be described later is paused, fast-forwarded, rewinded, and supplied to the decoder unit 70.

The decoder unit 70 supplies a bit stream signal obtained from the hard disk 61 under the control of the CPU 72 to the MPEG-2 decoder 71 and
A signal encoded by the EG-2 method is decoded to obtain a digital video signal. The digital video signal is converted to an analog video signal by a D / A converter 78, and the digital video signal is added to the digital video signal.
1 to one input terminal and an adder 81
The other input terminal of the video signal reproduction device 40 supplied from the CPU 72 and necessary for the operation of the video signal reproduction device 40
An on-screen display generating circuit 79 for obtaining a signal indicating the operation state of the
The adder 81 supplies an analog video signal obtained by adding and synthesizing these signals to be output from the decoder 70. The signal output from the decoder 70 is supplied to the monitor TV 90. Supplied and displayed.

Here, the above-described CPU 72 has a ROM 7
3, RAM 74, and remote control interface 85
Is connected to the ROM 73. A computer program for operating the CPU 72 is stored in the ROM 73.
The computer program stored in M73 is read to operate CPU72.

The RAM 74 stores relatively large data, such as image data, when it is necessary to temporarily store the data when the CPU 72 is operating.

Further, the remote control interface 85 connected to the CPU 72 transmits the received operation information to the CPU 72 when the remote control 95 is operated and, for example, an infrared light is emitted and an operation signal for, for example, high-speed reproduction is received. In accordance with the supplied operation information, the CPU 72 controls the operation of the MPEG-2 encoder 55 for writing / reading data to / from the hard disk 61, for example, and a decoding method of the MPEG-2 decoder 71 described later. And so on.

In the case of normal reproduction, the MPEG-2 decoder 7
1 is a signal of a bit stream generated according to the MPEG-2 standard.
Although an I picture, a P picture, and a B picture are encoded in units of P (Group of Picture), the decoding operation first decodes the I picture, and then decodes the P picture using the decoded I picture. Then, the B picture is decoded using the last decoded I picture and P picture. Therefore, among these three types of pictures, the I-picture can be most easily decoded. In particular, when it is necessary to perform decoding in a short time, such as when obtaining a high-speed search image, the I-picture can be decoded. The picture is decoded and used.

The ratio of I-pictures present in a bit stream according to MPEG-2 is generally one for every 15 pictures in the case of a normal GOP structure, and a high-speed search image is obtained by selecting only this I-picture. The decoded image signal is displayed. At this time, the time required to decode the I picture may be longer than 33 milliseconds, which is the display time of one frame in the video signal, because the I picture has a lower compression ratio and a larger amount of data than other pictures. In many cases, a video signal is generated using a technique such as displaying the obtained I picture over a plurality of display frames.

Further, the hard disk 61 shown in this embodiment
A video signal reproducing apparatus 40 using a video recorder, which receives a television signal and a video signal from an externally connected device supplied thereto, encodes the video signal according to the MPEG-2 system and records it on a hard disk 61, as if using a VTR. Although a recorded signal can be reproduced at a high speed, in particular, the present apparatus uses a conventional analog VTR.
Has a function to reproduce a recorded video signal at a high speed with a smooth motion. The configuration and operation for realizing the function will be sequentially described in detail.

FIG. 2 is a diagram showing the main components of the MPEG-
It is a detailed block diagram of 2 decoder 71A. This MPE
The G-2 decoder 71A is obtained by adding a write control circuit 71A-2 and a frame memory unit 71A-3 to the MPEG-2 decoder 71A-1 having a well-known configuration. 1 division memory g, 2nd
There is a divided memory h and a third divided memory i. In these divided memories g, h and i, an I-picture image divided vertically into three is controlled by a write control circuit 71A-2, respectively. Are divided and supplied to the divided memories g, h, and i, and are temporarily stored.

Next, the form of the image signals temporarily stored in these divided memories g, h, i will be described. FIG.
Next, a first high-speed search image display example for displaying a 15-times speed search image using a divided memory will be described. In the figure, an image obtained by decoding a bit stream in GOP units obtained from the hard disk 61 has three images in the vertical direction.
The data is divided and written into predetermined divided memories g, h, and i under the control of the write control circuit 71A-2. How to write the data will be described.

The MPEG decoding unit 71A-1 decodes an I-picture into an encoded bit stream sequentially supplied from the hard disk 61. In FIG. The same numbers are assigned to them. A display frame image is obtained by synthesizing the outputs of the first to third divided memories g, h, and i in the vertical direction to obtain an image of one frame. In the lower part of FIG. The images from the divided memories g, h, and i are indicated by one square in the vertical direction.

The operation of the configuration block shown in FIG. 2 will be further described with reference to FIG. First, the first I picture obtained by decoding the first GOP signal is vertically divided into three parts. The upper third is stored in the first divided memory g and the middle one third is stored in the second divided memory g.
Each of the lower thirds is temporarily stored in the third divided memory i in the divided memory h, and the images stored in these divided memories are sequentially read out in the order of upper part, middle part, and lower part,
The image is synthesized and displayed as a frame image.

Next, the second GOP signal obtained by decoding the second GOP signal
Is vertically divided into three, and the upper third is temporarily stored in the first divided memory g.
And the lower third are not written into the memories h and i, and the images of the three divided memories g, h and i in that state are read out in the order of upper part, middle part and lower part, and their contents are displayed. .

Further, the third I picture obtained by decoding the third GOP signal is vertically divided into three parts, and the middle 1/3 image is temporarily stored in the second partial memory h.
The contents of the three divided memories g, h, and i are not sequentially rewritten, and the contents of the three divided memories g, h, and i are sequentially read and the contents are displayed.

Next, the fourth I picture obtained by decoding the fourth GOP signal is one of the three vertically divided images.
The third divided memory i is rewritten by the lower 1/3, and the images of these three divided memories g, h, and i are sequentially read and the contents are displayed.

Hereinafter, the I picture decoded in the same manner is divided into three, and one of the divided memories g, h, and i is sequentially rewritten, and the three divided memories g,
It operates to sequentially read the images of h and i and display the contents.

FIG. 4 shows a positional relationship where the display frame screen of FIG. 3 is displayed on an actual monitor.
The contents of the first divided memory g are on the upper part of the monitor, the contents of the second divided memory h are on the middle part of the monitor, and the third divided memory i is
Is displayed at the bottom of the monitor.

The search image displayed in this way is 3
Since the same image is displayed for each display frame, the image content is easily recognized. In addition, since each of the divided areas is updated for each display frame, the time It has a feature that movement can be easily recognized.

FIG. 5 shows a display example of a second high-speed search image for displaying a 15-times speed search image using these divided memories g, h, and i. In the figure, a bit stream in GOP units obtained from the hard disk 61 is decoded every other, and the obtained image is divided into three in the vertical direction and written into predetermined divided memories g, h, and i. Writing is performed for each display frame.

First, the decoded I picture of the first GOP is written into all of the divided memories g, h, and i corresponding to the display positions of the upper, middle, and lower portions of the TV monitor screen. It is displayed during the period of the second display frame.

Next, the third I of the decoded third GOP
The picture rewrites the storage content of the first divided memory g, and the upper, middle, and lower parts of the TV monitor screen display the divided images of the third I frame, the first I frame, and the first I frame. It is displayed during the third and fourth display frames.

Similarly, the next fifth I picture rewrites the storage contents of the second divided memory 76b, and the upper, middle and lower portions of the TV monitor screen have the third I frame and the fifth I picture. The divided images of the frame and the first I frame are displayed during the fifth and sixth display frames.

As described above, in the second high-speed search image display example, the image decoded every two I-pictures is
The image is divided, and the upper, middle, and lower images of the TV monitor screen are rewritten and displayed in turn for each two display frames. Therefore, in this example, the MPEG decoding unit 71A-1 uses 2 bits to decode the I picture of the GOP.
It can be applied when the time of the display frame is required. The high-speed search image shown here has the same effect as that shown in FIG.

Here, as a method of displaying a search image accompanied by a more natural movement, a method of vertically dividing the screen into three has been described, but the number of divisions may be four or more.

FIG. 6 shows the configuration of a second embodiment of the MPEG-2 decoder when the number of divisions on the screen is five.
The MPEG-2 decoder 71B has a hard disk 6
1 and supplies the decoded signal to the D / A converter 78.
The decoder 71B is different from a commonly used MPEG decoder 71B-1 in that a write control circuit 71B-2, a frame memory unit 71B-3, and an addition circuit 71B-4.
The frame memory unit 71B-3 has first to fifth divided memories j to n, and these divided memories j to n each include an image of an I picture divided into five in the vertical direction. Are supplied under the control of the write control circuit 71B-2 and are temporarily stored. These temporarily stored images of the divided memories are sequentially called from the top of the screen, and the respective divided image signals are added by the adding circuit 71B-4. A frame signal is obtained by addition and synthesis, and the frame image signal is supplied to the D / A converter 78.

Next, the manner of writing and reading image signals to these divided memories j to n under the control of the control circuit 71B-2 will be described.

FIG. 7 shows and describes a third high-speed search image display example of a high-speed search image using a 5-part memory. In the same figure, the numbers shown in a single box at the top indicate GOP data, and the squares shown at the bottom five columns divide the screen displayed by decoding them into five in the vertical direction. The position is shown on the screen, and the number shown therein indicates the GOP number of the decoded image.

First, the image data of the I picture of the first GOP decoded by the MPEG decoding unit 71B-1 is
The image divided into five by the write control circuit 71B-2 is supplied to the first to fifth divided memories j to n in order from the upper image and temporarily stored, and the temporarily stored divided image data is read out. The control circuit reads the image sequentially from the upper side, and an image according to the image is displayed on the monitor TV 90.

Next, the I-picture of the third GOP is decoded by the MPEG decoding section 71B-1, and the top picture obtained by dividing the decoded picture into five is written into the write control circuit 71B-1.
-2 is supplied to the first divided memory j, only the image stored therein is rewritten, and the other divided memories k to
n is displayed together with the image stored in n. In the next display frame, the decoded fifth GOP I
The image of the frame is rewritten with the image of the second divided memory k, and in the next display frame, the image of the third divided memory 1 is rewritten.

In this way, every other decoded G
The I picture of the OP operates so as to sequentially update the image contents of one of the first to fifth divided memories j to n divided into five. The reproduction speed of the search image obtained at this time is such that every other GOP signal corresponding to a one-second program is 1/30.
Since it is updated every display frame every second, it is displayed as a 30 × speed search image.

FIG. 8 shows a display example of a fourth high-speed search image using the MPEG-2 decoder 71B. In the same figure, I pictures are obtained from every fourth GOP from the bit stream and decoded, and the first to fifth divided memories j to n are sequentially repeated in the same manner as in the method of temporarily storing a 30 × search image. The image content of one of the divided memories is updated, and a 60 × speed search image is displayed.

In the third and fourth high-speed search image display examples, one of the divided images in all the display frames is updated, information on motion is expressed, and the updated image is Since the same content is displayed over five display frames, the image content can be easily recognized.

Here, the display example of three divisions and five divisions has been described. However, it is easy to freely set and operate the number of divisions by controlling the control circuit 71B-2 by CPU control software. In such a case, it is possible to dynamically change the screen configuration of the search image by increasing the number of divisions at a high search speed according to the search speed.

In each of the embodiments described above, the search image is generated using one memory circuit. However, a plurality of frame memory circuits may be used. In this case, a third embodiment for generating a high-speed search image is used. An example will be described.

FIG. 9 shows a third embodiment in that case, an MPEG-2 decoder 71 using a three-frame image memory.
This is the configuration of C. In the figure, the signal of the MPEG-2 bit stream supplied from the hard disk 61 is
The signal is decoded by the ordinary MPEG-2 decoder 71C-1, and the decoded signal is supplied to the write control circuit 71C-2. The write control circuit 71C-2 includes three frame memories p, q, and r in the frame memory 71C-3.
Image data is sequentially supplied to one of them in a predetermined order, and the frame memory supplied with the image data temporarily stores the data.

Each of the frame memories p, q, and r is configured so that image data corresponding to the upper, middle, and lower portions of the display screen can be divided and read out. The digital image data temporarily stored in r is configured so that the image data of the divided portion designated by the read control circuit unit 71C-4 is sequentially read.

The read control circuit 71C-4 includes a read control circuit x and the respective frame memories p, q, and r.
From the top, middle,
First to third readout switches s to u corresponding to respective frame memories for switching and reading out the signal of the image data corresponding to the lower part, and addition for adding and combining the signals from these readout switches s to u And a digital image signal read from each frame memory circuit is supplied to a D / A converter 78.
Here, an analog high-speed search image signal is generated.

FIG. 10 shows and describes the display of a search image having a plurality of memory circuits as described above. In the figure, an incoming bit stream is numbered for each GOP at the top, and a digital image signal obtained by decoding an I picture in these GOPs is controlled by a write control circuit 71C-2. , First, second, third
Are temporarily stored in the frame memories p, q, and r, and the images temporarily stored in these frame memories are referred to as 3 in FIG.
In 7a, 37b, and 37c, display frames are arranged in columns, and the display frames are indicated by the GOP numbers in the order of display frames. The way of writing and reading will be further described.

First, in the digital image data obtained by decoding the I picture in the first GOP, all the signals for one frame are stored in the first frame memory p.
In the first display frame of “a”, the upper, middle, and lower display positions each have a value of “1”. This image is kept stored until it is rewritten to the signal of the fourth GOP in the fourth display frame.

Next, all the upper, middle, and lower signals with respect to the display position of the image data obtained by decoding the I picture of the second GOP are stored in the second frame memory q.
In the second display frame 37b, the upper part, the middle part,
Each is set to 2 for the lower part, and the storage of this image is continued until it is rewritten to the signal of the fifth GOP in the fifth display frame.

All the signals of the data obtained by decoding the I picture of the third GOP after that are stored in the third frame memory r. In the third display frame 37b, the upper part, the middle part, and the lower part of the display position are displayed. 3 is written on the lower part, and the storage is continued until the signal is rewritten to the signal of the sixth GOP in the sixth display frame. In this way, the decoded image data of the I picture is temporarily stored in the frame memory sequentially.

Next, the first to third frame memories p to p
The reading of the image data stored in r will be described.
First, in the case of the first first display frame, of the first to third frame memories p to q, the first frame memory p
, The only data to be displayed is the I picture of the first GOP, and the first image is displayed at any of the upper, middle, and lower portions of the monitor screen.

Next, in the case of the second display frame, the upper image of the second frame memory q is displayed at the upper part of the monitor screen, and the first frame memory p is displayed at the middle and lower part of the monitor screen.
Display the image of. The numbers at the places displayed in the figure are marked with a circle to distinguish them from others.

Next, in the case of the third display frame,
The upper part of the monitor screen displays the upper part of the third frame memory r, the middle part displays the middle part of the second frame memory q, and the lower part displays the lower part of the first frame memory p.
The points are indicated by circles in the same manner as described above.

Thus, after the fourth display frame,
The upper, middle, and lower images are sequentially displayed while switching the frame memory. Such switching of the display unit is performed based on the instruction of the readout control circuit x, and is performed by the first, second, and A third read switch s,
t and u are sequentially switched to obtain an image signal, and the obtained image signal is added and synthesized by an adding circuit w to obtain a digital image signal. The obtained signal is supplied to a D / A converter 78. , A search image converted into an analog signal is obtained, and the obtained image signal is supplied to the monitor TV 90 for display.

FIG. 12 shows the MPEG-data format shown in FIG.
A second high-speed search image display example obtained by the 2 decoder 71C is shown. The example shown in FIG.
The image of the I picture obtained from the G decoding unit 71C-1 is
This is a case where the time is required for one to two display frames, and is shown in the same manner as in FIG.

FIG. 13 shows the search image thus obtained as an image of a display frame on a monitor.
In the figure, the displayed image is updated every two display frames, but the update interval in each area is performed every two GOPs.

A comparison between the display according to the third embodiment performed in this way and the display according to the first embodiment shown in FIG. 5 shows that the same screen is displayed over six frames in FIG. However, in FIG. 13, the same screen is updated every two frames. Therefore, the one shown in FIG. 13 is preferable because a search image with more smooth motion can be obtained.

FIG. 18 shows the trajectory of the head at the time of the search by the analog VTR, and FIG. 19 shows the screen of the display obtained by the analog VTR. Are divided in the vertical direction, and images of different adjacent tracks are displayed above and below the divided area.

The search image used in the analog VTR was accidentally accepted as a natural one for human vision, and is still used today.

The search image shown in FIGS. 11 and 13 is a search image displayed in the same manner as the search image mechanically created by the analog VTR, and is a bit stream encoded by MPEG-2. A digital decoding circuit, a frame memory circuit,
This can be said to be realized by controlling the method of storing and reading the divided images.

Here, an example of mounting each of the above embodiments as a specific circuit configuration will be described.

Conventionally, a dedicated LSI has been developed for the MPEG-2 decoder 71 and used for products to which MPEG-2 is applied. However, writing control, storage to a frame memory, reading, and signal addition to this LSI are performed. By adding such a circuit, it is possible to realize a decoder having functions based on FIGS. 2, 6, and 9 by reducing the number of additional hardware circuits.

The motion compensation circuit of the MPEG-2 decoder 71 is based on the I picture and the P picture.
In order to generate a P picture and a B picture by motion prediction, it has a memory circuit for temporarily storing past and future picture images, and by adding an additional circuit to these frame memory circuits, FIG.
The functions based on FIGS. 6 and 9 can be provided together.

That is, when a search image to be reproduced at a high speed is generated, a two-sided frame memory circuit for generating a bidirectional motion compensation image included in the MPEG-2 decoder LSI is not used. Sometimes,
It is also possible to switch these circuits for the production of a search image and operate them to create the above-described search image.

For example, the search image creation operation of the video signal reproducing device 40 is performed by selecting and operating high-speed reproduction by the remote control 95. For example, an infrared signal modulated according to the selected information is transmitted from the remote control 95. The remote controller interface 85 receives the signal and transmits the received key operation information of the remote controller 95 to the CPU 7.
The CPU 72 controls the reading method of the hard disk 61 according to the supplied information,
This can be realized by designating the reproduction method for the G-2 decoder 71.

In recent years, MPEG-2 decoders that operate using microcode have appeared. Decoders that operate as software using microcode, for example, switch the function of a memory circuit. It is relatively easy to realize such a configuration, and it is possible to switch the reproduction method as described above.

As described above, when the circuit of the frame memory for generating the B picture by the bidirectional prediction of the MPEG-2 decoder 71 is used for generating the above-described search image, the above-described search supplied from the CPU 72 is used. The operation is performed by switching between using the memory circuit for generating a B picture and for generating a search image in accordance with the operation information. In this case, the number of additional circuits can be extremely small. Thus, an economical video signal reproducing apparatus 40 can be configured.

Further, the case where the display frame is treated as a frame image has been described.
Treated as a field signal. Therefore, when a high-speed display screen is obtained, it is of course possible to update the display screen for each field screen displayed in 1/60 second and obtain a fast-moving high-speed search image.

Further, the recording medium used in the video signal reproducing apparatus 40 has been described using the hard disk 61 as an example. However, the medium for recording the compressed video information is not limited to this, and DVDs, magneto-optical disks, etc. The same operation can be performed with a video signal recording medium having excellent accessibility.

As described above, according to the apparatuses of these embodiments, it is possible to create a search image which is easily recognized by human eyes, and the search image is displayed in a form in which the direction of temporal movement can be easily understood. In addition to this, it is possible to provide a configuration for creating these search images at a low cost using a conventional MPEG-2 decoder or the like, and to decode an I-picture without requiring particularly high-speed signal processing. There is an effect that it can be performed by using an ordinary decoder circuit.

In particular, in an apparatus using a plurality of frame memory circuits, there is an effect that a search image with higher temporal continuity can be produced with an economical configuration.

Further, in each of the above embodiments, the MPE
Although an apparatus for generating a high-quality search image from a bit stream coded by the G method has been described, the present invention is not limited to this. Coding is performed using a coding method and a method of performing high-efficiency coding using a relatively large amount of codes such as reducing the amount of information using image correlation between frames. Is used in a reproducing apparatus that obtains a signal encoded in a frame from a bit stream formed by mixing encoded bit streams and generates a search image, and is encoded in a frame that can be decoded as an image. By treating the bit stream in the same way as the I-picture in the GOP described above, the playback apparatus of a bit stream encoded by a method other than the MPEG method can be used. Even the same effects, such as can be obtained a high-quality search image.

[0101]

According to the first aspect of the present invention, an inter-frame encoding process and an intra-frame encoding process are performed in a predetermined block unit. For example, the read I-frame recorded for each GOP is read, the read bit stream is decoded, an image obtained by the decoding is divided in the vertical direction, and the divided image is divided into corresponding divisions on the memory circuit screen. The operation of recording at the designated location is sequentially repeated, and the search image is generated using the I frames of a plurality of GOPs which are repeatedly stored. A video signal playback device that displays a high-speed search image capable of expressing a change, using a conventionally used MPEG decoder,
There is an effect that an economical configuration can be achieved by adding a small number of circuits.

According to the second aspect of the present invention, since the search image is generated by using a plurality of frame memory circuits, for example, all of the I-frame images decoded for the search image are used. Since the search image is generated using the search image, there is an effect that, in addition to the effect of the first aspect, a search image with a smoother motion can be generated and displayed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a video signal reproducing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an MPEG-2 decoder according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a first high-speed search image display example for displaying a 15 × speed search image using a divided memory.

FIG. 4 is a diagram showing a positional relationship where the display frame screen shown in FIG. 3 is displayed on an actual monitor.

FIG. 5 is a diagram showing a second high-speed search image display example for displaying a 15 × speed search image using a divided memory.

FIG. 6 is a diagram illustrating a configuration of an MPEG decoder according to a second embodiment in which the number of divisions of a frame memory is 5;

FIG. 7 shows a third example operating at 30 times speed using a 5-part memory.
FIG. 5 is a diagram showing a display example of a high-speed search image of FIG.

FIG. 8 is a diagram showing a sequence of a fourth high-speed search image display example for displaying a 60 × speed search image.

FIG. 9 is a diagram showing a configuration of a high-speed search image generation circuit according to a third embodiment of the present invention using an image memory of three frames.

FIG. 10 is a diagram illustrating a method of displaying a high-speed search image by a high-speed search image generation circuit using a three-frame image memory.

FIG. 11 is a diagram showing a high-speed search image by a high-speed search image generation circuit using a three-frame image memory in the form of a display frame.

FIG. 12 is a diagram illustrating a method of displaying a second high-speed search image by a high-speed search image generation circuit using a three-frame image memory.

FIG. 13 is a diagram showing a second high-speed search image by a high-speed search image generation circuit using a three-frame image memory in the form of a display frame.

FIG. 14 is a diagram illustrating an example of the configuration of a GOP in a state in which a picture image is encoded by MPEG-2 in units of a picture image.

FIG. 15 is a diagram showing a first search image display example for displaying a decoded signal.

FIG. 16 shows an improved MPEG-2 decoder and a second display for displaying at 15 × speed using a hard disk.
FIG. 6 is a diagram showing an example of a search image display.

FIG. 17 is a diagram illustrating a third search image display example for obtaining a 30 × search image for continuously displaying the same I-picture image over a plurality of frames.

FIG. 18 is a diagram showing a positional relationship of a read track at the time of high-speed reproduction in a conventional analog VTR.

FIG. 19 is a diagram illustrating a display example on a monitor during high-speed reproduction in a conventional analog VTR.

[Description of References] 1 to 24 GOP number 37a Image stored in first frame memory 37b Image stored in second frame memory 37c Image stored in third frame memory 40 Video signal reproducing device 50 Encoder unit 51 TV tuner 52 Video input terminal 53 Video signal changeover switch 54 A / D converter 55 MPEG-2 encoder 61 Hard disk 70 Decoder unit 71 MPEG-2 decoder 71A MPEG-2 decoder 71A-1 MPEG decoding unit 71A-2 Write control circuit 71A-3 Frame memory unit 71B MPEG-2 decoder 71B-1 MPEG decoding unit 71B-2 Write control circuit 71B-3 Frame memory unit 71B-4 Addition circuit 71C MPEG-2 decoder 71C-1 MPEG decoding unit 71C-2 Write control circuit 1C-3 Frame memory unit 71C-4 Read control unit 72 CPU 73 ROM 74 RAM 78 D / A converter 79 On-screen display generation circuit 81 Addition circuit 85 Remote control interface 90 Monitor TV 95 Remote control 110 Analog video tape 111 Track pattern 112 Normal Head trace direction at the time of reproduction 121 Head trace pattern at the time of search 122 Head trace direction at the time of search a to f Track pattern g to i First to third divided memory j to n First to fifth divided memory p to r First To third frame memory s to u selector switch w adder circuit x readout control circuit

Claims (2)

[Claims] An inter-frame encoding process and an intra-frame encoding process are assigned in a predetermined order in a predetermined block unit, and a data-compressed video signal is recorded on a predetermined recording medium. A video signal reproducing apparatus for reproducing a signal, wherein the control means controls a reproducing operation of the predetermined recording medium based on the reproducing speed information selected by the selecting means; and Medium reproducing means for reading a video signal from a recording medium; decoding means for decoding the video signal read from the medium reproducing means; video signal generating means for displaying a signal decoded by the decoding means on a display; The decoding means sequentially obtains the signals subjected to the intra-frame encoding processing from the predetermined recording medium, and obtains the sequentially obtained signals. A decoding unit that obtains digital frame image data by decoding the digital frame image data, a write control unit that divides the decoded digital frame image data into digital image data of a plurality of areas, and the divided digital frame image data. And an image memory for storing in a plurality of areas. 2. A video signal which is allocated in a predetermined order in an inter-frame encoding process and an intra-frame encoding process in a predetermined block unit, and records a data-compressed video signal on a predetermined recording medium. A video signal reproducing apparatus for reproducing a signal, wherein the control means controls a reproducing operation of the predetermined recording medium based on the reproducing speed information selected by the selecting means; and Medium reproducing means for reading a video signal from a recording medium; decoding means for decoding the video signal read from the medium reproducing means; video signal generating means for displaying a signal decoded by the decoding means on a display; Wherein the decoding means sequentially obtains the signals subjected to the intra-frame encoding processing from the predetermined recording medium, and obtains the sequentially obtained signals. A decoding unit that decodes the image data to obtain digital frame image data, a write control unit that sorts the decoded digital frame image data for each image data, and a plurality of images that store the sorted digital image data. A video signal reproducing device comprising a memory.