JP3374128B2 - Image processing method, image processing apparatus capable of using the method, and television receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method, an image processing apparatus and a television receiver which can use the image processing method. The present invention is, for example, an MPEG (Moving Pic).
ture Expert Group) A technique for processing data encoded according to the standard.

[0002]

2. Description of the Related Art Information handled by multimedia is vast and diverse, and it is necessary to process the information at high speed in order to put the multimedia into practical use. In order to process information at high speed, data compression / decompression technology is essential. As such a data compression / decompression technique, there is an “MPEG” method. This MPE
The G method is ISO (International Organization for S)
tandardization) / IEC (International Electro-te
chnical Commission) MPEG committee (ISO / IEC
It is being standardized by JTC1 / SC29 / WG11). MPE
The image processing device using the G system is a movie camera, a still camera, a television, a video CD reproducing device, a DV.
It is incorporated in various image-related devices such as a D playback device.

Video data handled by MPEG relates to a moving image, and the moving image is composed of a plurality of frames, for example, 30 frames per second, that is, still images or frames. As shown in FIG. 1, video data includes a sequence (Sequence) and a GOP (Group Of Pictu).
res), picture (Picture), slice (Slice), macroblock (Macroblock), and block (Block) in this order, having a hierarchical structure of 6 layers. The number of slices forming one picture is not fixed, and the number of macroblocks forming one slice is not fixed. Note that FIG.
Then, the macroblock layer and the block layer are omitted.

In MPEG, there are mainly two systems, MPEG-1 and MPEG-2, mainly depending on the difference in coding rate. In MPEG-1, a frame corresponds to a picture. In MPEG-2, a frame or field can be associated with a picture.
Two fields make up one frame.
A structure in which a frame corresponds to a picture is called a frame structure, and a structure in which a field corresponds to a picture is called a field structure.

In MPEG, a compression technique called interframe prediction is used. Inter-frame prediction compresses data between frames based on temporal correlation. Bi-directional prediction is performed in inter-frame prediction. Bi-directional prediction is a combination of forward prediction that predicts a current reproduced image from a past reproduced image or picture and backward prediction that predicts a current reproduced image from a future reproduced image.

This bidirectional prediction is based on the I picture (Intra-Pi
cture), P picture (Predictive-Picture), and B picture (Bidirectionally predictive-Picture). The I-picture is an image that is independently generated by the intra-frame encoding process, regardless of past and future reproduced images. At least one I picture is required in the GOP for random access. All macroblock types within an I-picture are intra-frame prediction screens (IntraFrame). P-pictures are
It is generated by forward prediction, that is, prediction from a past I picture or P picture. The macroblock type in a P picture includes both an intra-frame prediction screen and a forward prediction screen (Foward Inter Frame).

A B picture is generated by bidirectional prediction by interframe coding processing. In bidirectional prediction, a B picture is generated by any one of the following three predictions. Forward prediction; Predictive backward prediction from past I or P pictures; Predictive bidirectional prediction from future I or P pictures; Macroblocks in predicted B pictures from past and future I or P pictures・ Types are intra-frame prediction screen, forward prediction screen, backward prediction screen (Backward prediction screen
Inter Frame), Interpolative Inte
r Frame).

These I, P and B pictures are encoded respectively. That is, the I picture is generated even if there is no past or future picture. On the other hand, a P picture is not generated without a past picture, and a B picture is not generated without a past or future picture. However, even for P-pictures and B-pictures, if the macroblock type is an interpolative prediction screen, the macroblock is generated even if there are no past or future pictures.

In inter-frame prediction, first, I pictures are periodically generated. Next, a frame several frames ahead of the I picture is generated as a P picture. This P
A picture is generated by unidirectional (forward) prediction from the past to the present. Subsequently, frames located before the I picture and after the P picture are generated as B pictures. When this B picture is generated, the optimum prediction method is selected from the three methods of forward prediction, backward prediction, and bidirectional prediction. In a continuous video, the current image and the images before and after it are generally very similar, and the difference is that
Only a small part of it. Therefore, it is assumed that the previous frame and the next frame are the same, and if there is a change between both frames, only the difference is extracted and compressed. For example,
The difference is extracted as B picture data with the previous frame as an I picture and the next frame as a P picture. Thereby, data between frames can be compressed based on temporal correlation. A data stream or bit stream of video data encoded according to the MPEG video part is called an MPEG video stream.

MPEG-1 is mainly used for video CD (Compac
t Disc) and a storage medium such as a CD-ROM (CD-ReadOnly Memory). MPEG-2 is a video CD, CD-ROM, DVD (Digital Video Dis
k), VTR (Video Tape Recorder) and other storage media, as well as LAN (Local Area Network) and other communication media, terrestrial broadcasting and satellite broadcasting, and CATV (Co
mmunity Antenna Television) is compatible with all transmission media including broadcasting media such as.

The core of the technology used in the MPEG video part is motion compensation prediction (MC).
ated prediction) and discrete cosine transform (DCT; Discr)
eteCosine Transform). A coding technique that uses MC and DCT together is called a hybrid coding technique.
In the MPEG video part, DCT (alias F
DCT (Forward DCT) is used to decompose a video signal of an image into frequency components for processing. And DC at the time of decoding
Inverse transform of T (inverse discrete cosine transform; IDCT; Inverse)
DCT) is used to restore the frequency components back to the video signal of the image.

Although a huge amount of information can be processed at high speed in MPEG, as described above, since a compression technique called interframe prediction is used, it is encoded in time series according to the MPEG video part. When playing back the recorded data sequence in reverse order for picture search, that is, in the reverse direction, it is very difficult to simply play back the recorded data sequence backwards like a normal video tape recorder. Is. Therefore, conventionally, only the I picture assigned to each GOP is played back retroactively on the time axis. As described above, the I picture is an image that has undergone intraframe coding processing, and thus can be displayed independently without referring to the preceding and subsequent pictures.

[0013]

In the conventional example, the number of I pictures assigned to each GOP is extremely small. For example, in MPEG, the I pictures assigned to a GOP are 15 to 30 pictures. One of them is at most one, and when the pictures of every 15 to 30 frames are played in reverse order, it is not possible to obtain a smooth reverse order reproduction screen like a normal video tape recorder, and it is necessary to stop at the desired timing. Was difficult.
The present invention has been made in view of this point, and one of the objects thereof is to provide a technique of image processing capable of obtaining a smooth reverse playback screen.

The present invention seeks to solve this and other objects that will become apparent from the present specification, mainly in the art related to image encoding and decoding processes.

[0015]

One aspect of the present invention relates to an image processing apparatus. This device converts a first coded data string including I-pictures, P-pictures, and B-pictures coded according to MPEG into a second coded data string composed of I-pictures and B-pictures. And a post-decoder for decoding the second coded data sequence generated by the converter in anti-time series, and a controller for controlling the operations of the converter and the post-decoder. The post-decoder corresponds to the above-mentioned second decoder.

This converter includes a predecoder that decodes at least P picture data in the first coded data string, and the data decoded by the predecoder is encoded as an I picture in accordance with MPEG. And a storage unit that stores the second encoded data string. The predecoder corresponds to the aforementioned first decoder.

This apparatus further uses, as the B picture included in the second coded data string, the B picture included in the first coded data string without being processed by the predecoder and the encoder. An allocation control unit for allocating may be provided. In addition to B pictures, I pictures may be the target of this processing.

The first coded data sequence may be data in which the pictures are assigned in a predetermined order in a predetermined group unit and coded, in which case the converter and the post-decoder are used. Each process may be performed in the unit of the predetermined group.

Another aspect of the present invention relates to an image processing method. This method is a process for converting a first coded data string including I-pictures, P-pictures, and B-pictures coded according to MPEG into a second coded data string composed of I-pictures and B-pictures. And a process of decoding the second coded data sequence in anti-time series.

According to this method, data excluding at least a B picture in the first encoded data string is encoded as an I picture in accordance with MPEG, and other data may be directly assigned to the second encoded data string. Good.

The first encoded data sequence may be data in which pictures are assigned in a prescribed order in a prescribed group unit and encoded, and in that case, the conversion processing and the decoding processing are performed in the prescribed manner. May be performed in units of groups. During the execution of the decoding process, the conversion process may be executed based on the encoded data of the next group. It is also possible to provide a television receiver having any one of the image processing devices described above mounted therein, and having the reproduction of images in a time series as a part of the operation specifications.

In any of the above cases, the encoding or decoding, and the processing associated therewith depending on the case, may be executed in a predetermined group unit. Further, any combination of the above arbitrary constituents and processing steps, and the expression of the present invention converted between a method, a device, a system, a computer program, a recording medium, etc. are also effective as an aspect of the present invention. .

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments embodying the present invention will be described. Processing common to some of the embodiments is forward and reverse playback of images. In the following description, "regular order", "reverse order" and their synonyms are used for convenience of description.
This is the order in which the pictures that make up an image are finally displayed. Therefore, unless otherwise specified below, the order of the pictures will be the display state.

As will be described later, even in reverse reproduction, MP
The pictures in each GOP of the EG data stream are first decoded in the forward direction, i.e. in time series. This is re-encoded, and the reverse sequence is realized only at the subsequent re-decoding stage. Therefore, the "reverse order" in the reverse order reproduction is mainly related to the second decoding.

The MPEG bit stream is composed of I, P and B.
Various combinations of picture order are possible
However, for the purpose of the following description,₁B_Two
B_ThreeP_FourB₅B₆P₇B₈B₉… ”, While Pic
The display order of the tea is "B_TwoB_ThreeI ₁B₅B₆P_FourB₈B₉P
₇… ”

Various components appear in the following embodiments. In terms of hardware, these can be realized by a CPU, a memory, other LSIs or combinational circuits, and in terms of software, they can be realized by a program having an image processing function loaded in the memory. Focuses on the functions realized by the collaboration of Therefore, it is understood by those skilled in the art that these functions can be realized in various forms by only hardware, only software, or a combination thereof.

(First Embodiment) FIG. 2 shows a block circuit of an image reproducing apparatus 1 according to the first embodiment. This image reproducing apparatus 1 is a movie camera, a still camera, a television, a video CD reproducing apparatus, a DV which outputs an MPEG video stream from a transmission medium 2 to a display 3.
It is incorporated into a D playback device or the like. In addition, transmission medium 2
Includes storage media (video CD, CD-ROM, DV
D, VTR, etc.), communication media (LAN, etc.), broadcasting media (terrestrial broadcasting, satellite broadcasting, CATV, etc.) and the like. If the data from the storage medium or the broadcast medium is data that is not encoded according to the MPEG video part, the transmission medium also includes an MPEG video encoder for encoding this digital data. When the image reproducing device 1 is incorporated in a movie camera or a still camera, the transmission medium 2 is a CCD.
And the signal processing circuit thereof.

In FIG. 2, the image reproducing apparatus 1 includes a hard disk (HD) 4, an MPEG video decoder 5 (hereinafter also simply referred to as "decoder 5"), an MPEG video encoder 6 (hereinafter simply referred to as "encoder 6"). , A second MPEG video decoder 7 (hereinafter also simply referred to as “second decoder 7”), a switching circuit 8, a display circuit 9, and a control core circuit 10. Image reproduction device 1
The whole or a main part thereof may be mounted on a one-chip LSI, which is the same in other embodiments. The control core circuit 10 controls the operation of each component of the image reproducing device 1, including the decoder 5, the second decoder 7 and the encoder 6. The hard disk 4 is composed of a magnetic disk, and sequentially stores the video streams transferred from the transmission medium 2. A special storage area 4a is provided in the hard disk 4.

The switching circuit 8 switches connection to the first node 8a and second node 8b sides under the control of the control core circuit 10. When the switching circuit 8 is connected to the first node 8a side, the reproduced image data string generated by the decoder 5 is directly input to the display circuit 9 and the normal order reproduction is performed. Second
When connected to the node 8b side, the display circuit 9 is supplied with data from the second decoder 7 for performing reverse reproduction as will be described later.

The display circuit 9 generates a video video signal from the picture data transferred from the decoder 5 or the second decoder 7, and outputs this to the display 3 connected to the image reproducing apparatus 1.

FIG. 3 is a block diagram showing the structure of the decoder 5. In the figure, the decoder 5 comprises a picture header detection circuit 11, a picture skip circuit 12, and a decode core circuit 13, and the decode core circuit 13
Huffman decoding circuit 14, inverse quantization circuit 15, IDCT
(Inverse Discrete Cosine Transform) Circuit 16, M
C (Motion Compensated prediction) circuit 17, RO
It is composed of M (Read Only Memory) 18 and 19. The decoder 5 is an example of the "first decoder" in the present invention.

The picture header detection circuit 11 detects the picture header at the beginning of each picture of the video stream stored in the hard disk 4, and detects the picture type (I, P, B) specified in that portion. To do.

The picture skip circuit 12 has a first node 12a and a second node 1 under the control of the control core circuit 10.
The connection to the 2b side is switched. When the picture skip circuit 12 is connected to the first node 12a side,
The picture read from the hard disk 4 is directly transferred to the decoding core circuit 13. When connected to the second node 12b side, the picture read from the hard disk 4 is skipped without being transferred to the decode core circuit 13. As a result, the pictures transferred to the decode core circuit 13 are thinned out in picture units.

However, in this embodiment, the picture skip circuit 12 is fixed in a state of being connected to the first node 12a. Therefore, the picture header detection circuit 11 and the picture skip circuit 12 can be appropriately omitted in implementing the image reproducing device 1 of the present embodiment.

The Huffman decoding circuit 14 performs variable length decoding on the picture read from the hard disk 4 based on the Huffman code stored in the Huffman table stored in the ROM 18. Inverse quantization circuit 15
Is a ROM for the decoding result of the Huffman decoding circuit 14.
Inverse quantization is performed based on the quantization threshold value stored in the quantization table stored in the DCT (Discrete Cos.
ine Transform) Calculate the coefficient. The IDCT circuit 16 is
IDCT for the DCT coefficient obtained by the inverse quantization circuit 15
I do. The MC circuit 17 performs MC (Motion Compensated prediction) on the processing result of the IDCT circuit 16.

In this way, the decoder 5 receives the input MP
The EG video stream is decoded to generate a reproduction image data string that is continuous in time series. The MPEG video stream is an example of the "first encoded data string" in the present invention.

FIG. 4 is a block diagram showing the configuration of the encoder 6. In the encoder 6, all the reproduced image data strings generated by the decoder 5 are I-pictures in screen units,
That is, it is encoded as an intra-frame encoded image. Figure 4
In, the encoder 6 includes an MC circuit 20, a DCT circuit 21, a quantization circuit 22, a Huffman encoding circuit 23, and an RO.
It is composed of M24 and M25. The encoder 6
Is an example of the "encoder" of the present invention.

The MC circuit 20 originally performs MC on the reproduced image data decoded by the decoder 5, but the encoder 6 in this embodiment encodes all the input reproduced image data in the frame. I by processing
Since it is generated as a picture, the MC circuit 20 does not perform processing. Therefore, the MC circuit 20 can be omitted as appropriate.

The DCT circuit 21 takes in the reproduced image data input from the decoder 5 in block units and performs a two-dimensional discrete cosine transform to generate DCT coefficients. The quantization circuit 22 quantizes the DCT coefficient with reference to the quantization threshold stored in the quantization table stored in the ROM 24. The ROM 24 may also serve as the ROM 19.

The Huffman coding circuit 23 performs variable-length coding on the quantized DCT coefficients with reference to the Huffman code stored in the Huffman table stored in the ROM 25, thereby compressing the image data. Generate in screen units. The ROM 25 may also serve as the ROM 18.

The reproduced image data sequence generated by the decoder 5 is encoded by the encoder 6 into I pictures on a screen-by-screen basis, and then stored in the storage area 4a allocated in the hard disk 4. The storage area 4a has a capacity of 1 GO of the input MPEG video stream.
P is enough. The storage area 4a is an example of the "storage unit" in the present invention.

FIG. 5 is a block diagram showing the configuration of the second decoder 7. In the figure, the second decoder 7 includes a Huffman decoding circuit 26, an inverse quantization circuit 27, and an IDCT circuit 2.
8, an MC circuit 29, and ROMs 30 and 31. In addition, the second decoder 7 is the "decoder" and the "second decoder" of the present invention.
Decoder ”.

The configuration of the second decoder 7 is the decoder 5
The same as the decode core circuit 13 in FIG. Therefore, the Huffman decoding circuit 26, the Huffman decoding circuit 14,
The inverse quantization circuit 27 is the inverse quantization circuit 15, the IDCT circuit 28 is the IDCT circuit 16, and the MC circuit 29 is the MC circuit 1.
7 has the same circuit configuration. However, as will be described later, since all the image data strings input to the second decoder 7 are data encoded in I pictures, M
The C circuit 29 does not perform processing. Therefore, the MC circuit 2
9 can be omitted as appropriate. The ROM 30 is
The other ROM 18, ROM 25, and ROM 31 are R
The OM 19 and the ROM 24 may be used in combination. The reproduced image data string decoded by the second decoder 7 is
It is input to the display circuit 9 from the second node 8b of the switching circuit 8.

Based on the above configuration, the reverse reproduction operation in the image reproducing apparatus 1 of this embodiment will be described with reference to the flowchart shown in FIG. The operation of the image reproducing device 1 is executed under the control of the control core circuit 10. Here, the MPEG video stream has i GOPs (GOP
_{0 to} GOP _i-1 ).

In the reverse order reproduction, each GOP is processed sequentially from GOP _i-1 by tracing back to the time axis. However, the pictures in each GOP are decoded in the forward direction, that is, in time series by the decoder 5. When the reverse reproduction is instructed, the switching circuit 8 is connected to the second node 8b (S1), the MPEG video stream corresponding to GOP _i-1 is read from the hard disk 4 in picture units and input to the decoder 5. Reproduced image data for each screen is sequentially generated in time series and input to the encoder 6 (S2). Encoder 6
Then, all the reproduced image data strings of 1 GOP input from the decoder 5 are re-encoded into I pictures (S
3). The re-encoded data string of 1 GOP from the encoder 6 is overwritten in the storage area 4a of the hard disk 4 (S4).

When the writing to the storage area 4a is completed,
The second decoder 7 reads the re-encoded data sequence stored in the storage area 4 a in anti-time series, that is, retroactively traces back to the time axis, sequentially decodes it, and outputs it to the display circuit 9. When the writing to the storage area 4a is completed, a writing end signal is sent, the MPEG video stream corresponding to the next GOP _i-2 is input to the encoder 5, and the processing from S2 is performed (S5). That is, in S5, when the second decoder 7 is decoding one GOP data string, the decoder 5 is decoding the next 1 GOP data string. Reproduction image data is input to the display circuit 9 from the second decoder 7 in anti-time series, and a reverse reproduction screen is displayed on the display 3.

Next, the operation for normal order reproduction will be described with reference to the flowchart shown in FIG. In forward playback, processing is performed sequentially from GOP ₀ according to the time axis. The picture in each GOP is naturally decoded in the decoder 5 in the forward direction. When the forward reproduction is instructed, the switching circuit 8 is set to the first
Connected to the node 8a (S11), the MPEG video stream corresponding to GOP ₀ is read from the hard disk 4 in picture units and input to the decoder 5, reproduced image data is sequentially generated in screen units in time series, and the encoder 6 Is input in parallel to the display circuit 9 (S12). The display circuit 9 generates a video signal based on the input reproduction image data in screen units and outputs it to the display 3 (S1).
3) As a result, the normal reproduction screen is displayed on the display 3 (S14).

On the other hand, in parallel with the processing of the display circuit 9, the encoder 6 re-encodes 1 GOP worth of reproduced image data string input from the decoder 5 into I pictures (S).
15). The re-encoded data string is overwritten in the storage area 4a of the hard disk 4 (S16). When the processing of GOP ₀ is completed, the processing returns to S12 and the processing of the next GOP ₁ is performed. That is, during the normal-order reproduction, the encoder 6 concurrently re-encodes the same image data sequence into I pictures in GOP units.

The image reproducing apparatus 1 has the following operational effects. (1) The encoder 6 converts all the reproduced image data strings generated by the decoder 5 into I-pictures,
Since the decoder 7 reproduces images in the reverse order, a smooth reverse order reproduction screen can be obtained. As a result, the image reproducing apparatus 1
It is possible to improve the screen search function of devices equipped with. (2) Since the storage area 4a is allocated in the hard disk 4 for storing the MPEG video stream from the transmission medium 2 and the re-encoded data string from the encoder 6 is stored, as compared with the case where a separate storage element is provided. Cost reduction can be realized. (3) Since one GOP worth of re-encoded data strings are sequentially overwritten in the storage area 4a, an increase in the capacity thereof can be suppressed and an increase in the capacity of the entire hard disk 4 can also be suppressed. (4) When the second decoder 7 is decoding 1 GOP worth of data strings, the decoder 5 is decoding the next 1 GOP worth of data strings, so that 1 GOP worth of pictures can be reproduced in reverse order. Immediately after the end, it is possible to shift to the reverse reproduction of the next GOP picture, and a smooth reverse reproduction screen can be obtained. (5) While the normal order reproduction is being performed, the encoder 6 parallelly re-encodes the same image data sequence into I pictures in GOP units. Therefore, even when the reverse reproduction is instructed during the normal reproduction, the screen switching is smoothly performed.

(Second Embodiment) The second embodiment is different from the image reproducing apparatus 1 of the first embodiment in that the decoder 5 enables the picture skip circuit 12 to perform high-speed forward reproduction and reverse reproduction. There is a point to realize.

MPE read from hard disk 4
Since the frame rate of the G video stream increases according to the reproduction speed, it is necessary to increase the processing speed of the decoder 5 when decoding all pictures in high speed reproduction.
However, for that purpose, it is necessary to increase the operating frequency, parallelize the arithmetic circuit, and improve the performance of the memory, that is, the capacity and the operating speed. As a result, the circuit scale increases and the power consumption increases. At the same time, the cost may increase.

In the present embodiment, in consideration of such a problem,
For example, when double-speed high-speed normal order reproduction or high-speed reverse order reproduction is instructed, the control core circuit 10 directly decodes the decode core circuit if the picture type detected by the picture header detection circuit 11 is an I picture or a P picture. Thirteen
If it is a B picture, the picture skip circuit 12 is connected to the second node 12b side and skipped.
As a result, the pictures transferred to the decoding core circuit 13 are thinned out in picture units by the skipped amount.
B pictures are not used for decoding other pictures, so
Its importance is lower than that of I and P pictures. Therefore, by preferentially skipping B pictures,
The effect of dropped frames occurring in a moving image reproduced on the display 9 is extremely small as compared with skipping I-pictures and P-pictures. Therefore, it is possible to obtain smooth high-speed forward reproduction and high-speed reverse reproduction screens without increasing the processing speed of the decoder 5. In this embodiment, the basic reverse playback operation follows the flow shown in FIG. 6, and the forward playback operation follows the flow shown in FIG.

(Third Embodiment) FIG. 8 shows a block circuit of an image reproducing apparatus 51 according to the third embodiment. The same components as those of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. One feature of this embodiment is that the first picture data decoder composed of a plurality of pictures and the second picture data decoding composed of a plurality of pictures and appearing in a processing stage different from that of the first picture data are decoded. This is in common with the vessels. In the first embodiment, the configuration of the second decoder 7 is the same as that of the decode core circuit 13 in the decoder 5, but this embodiment pays attention to this point and makes the decoder 5 and the second decoder 7 common. There is.
In FIG. 8, the image reproducing device 51 includes a hard disk 4, a switching circuit 52, a shared decoder 53, an encoder 6,
The second switching circuit 54, the display circuit 9, and the control core circuit 10 are included. The configuration of the shared decoder 53 is the same as that of the decoder 5.

The MPEG video stream from the hard disk 4 or the re-encoded data string from the storage area 4a is input to the shared decoder 53 via the switching circuit 52, and the output thereof is displayed on the display circuit 9 via the second switching circuit 54. Alternatively, it is input to the encoder 6.

The connection of the switching circuit 52 to the first node 52a and the second node 52b side is switched under the control of the control core circuit 10. The switching circuit 52 is the first node 52a.
Side, the MPEG video stream from the hard disk 4 is input to the shared decoder 53, and when connected to the second node 52b side, the re-encoded data string from the storage area 4a is input to the shared decoder 53. It

The connection of the second switching circuit 54 to the first node 54a and the second node 54b side is switched under the control of the control core circuit 10. When the second switching circuit 54 is connected to the first node 54a side, the reproduced image data string from the shared decoder 53 is input to the display circuit 8 and the second node 5 is connected.
When connected to the 4b side, the reproduced image data string from the shared decoder 53 is input to the MPEG encoder 6.

With the above configuration, the switching circuit 52 is connected to the first node 52a and the second switching circuit 54 is connected during the forward reproduction.
Is connected to the first node 54a. Therefore, the MPEG video stream from the hard disk 4 is decoded by the common decoder 53 and is directly displayed on the display circuit 9.
Entered in.

On the other hand, during reverse reproduction, the control core circuit 10 first connects the switching circuit 52 to the first node 52a and then the second node 52a.
With the switching circuit 54 connected to the second node 54b, one picture worth of image data is read from the hard disk 4. The image data is input to the shared decoder 53 through the first node 52a and decoded. Then, one picture worth of reproduced image data from the shared decoder 53 is input to the MPEG encoder 6 through the second node 54b and re-encoded as an I picture.

The control core circuit 10 connects the switching circuit 52 to the second connection immediately after the reproduction picture data for one picture is sent from the common decoder 53 to the MPEG encoder 6.
The node 52b is switched to, the connection of the second switching circuit 54 is switched to the first node 54a, and one picture worth of re-encoded data for reverse reproduction is read from the storage area 4a.
The re-encoded data is input to and decoded by the shared decoder 53 via the second node 52b, and one picture worth of reproduced image data is input to the display circuit 8 via the first node 54a and displayed on the display 3. It Control core circuit 10
As soon as the reproduced image data for one picture is sent from the shared decoder 53 to the display circuit 8, the switching circuit 52
To the first node 52a, and the second switching circuit 5
The connection of No. 4 is switched to the second node 54b, and one picture worth of image data is read from the hard disk 4.

Similarly, the control core circuit 10 switches the connection state of the nodes of the switching circuits 52 and 54 each time the reproduction image data is output from the common decoder 53. The shared decoder 53 performs the processing of the decoder 5 and the processing of the second decoder 7 in the first embodiment in a time division manner. Also in this embodiment, the basic reverse reproduction operation follows the flow shown in FIG. 6, and the normal reproduction operation follows the flow shown in FIG. However,
In FIG. 6, the operations of the decoder 5 and the second decoder 7 are replaced by the operations of the shared decoder 53.

As described in the first embodiment, in the decoder 5, the picture skip circuit 12 is fixed while being connected to the first node 12a.
Even if the decoder 5 and the second decoder 7 are shared by adding the picture header detection circuit 11 and the picture skip circuit 12 to the decoder 7, that is, the shared decoder 53.
Even if it is configured, no problem will occur. In this embodiment,
In addition to the effects of the first embodiment, the effect of reducing the circuit area and the resulting cost reduction are realized, and it becomes easier to further increase the commercial value.

(Fourth Embodiment) The fourth embodiment is different from the image reproducing apparatus 51 of the third embodiment in that the common decoder 53 enables the picture skip circuit 12,
The point is to realize high-speed forward playback and reverse playback. The skip operation in the picture skip circuit 12 is the second operation.
It is similar to the embodiment. In this case, all the data strings generated by the MPEG encoder 6 are I-pictures, so even if this data string is input to the shared decoder 53 again, it is not skipped. Also in this embodiment, the basic reverse reproduction operation follows the flow shown in FIG. 6, and the normal reproduction operation follows the flow shown in FIG.

(Fifth Embodiment) In the fifth embodiment, low-speed normal reproduction and reverse reproduction are realized in the image reproducing apparatus 1 of the first embodiment. In FIG. 9, the control core circuit 1
When 0, the MPEG bit stream is read from the hard disk 4 into the decoder 5, and the same picture of the reproduced image data is repeatedly output. For example, when the MPEG bit streams are arranged in the order of I ₁ B ₂ B ₃ P ₄ B ₅ ..., The reproduced image data sequence output from the decoder 5 is I ₁ I ₁ B ₂ B ₂ B ₃ B _{3 P 4 P 4 B 5 B 5} ... become. By inputting this reproduced image data string to the display circuit 9, the speed of the screen on the display 3 is halved.

The decoder 5 has a buffer memory (not shown) built therein. The decoded picture data is temporarily stored in this buffer memory and the data is repeatedly output a predetermined number of times (hereinafter referred to as "repetitive output"). The buffer memory may be shared by the hard disk 4 and other memories. The predetermined number of times may be determined based on a user's instruction, may be set to a predetermined default value in the device, or may be determined according to any design guideline. This policy is valid thereafter.

When the reverse reproduction is instructed, the switching circuit 8 is connected to the second node 8b, and the encoder 6 becomes the decoder 5
The reproduced image data string input from the first reproduction image is re-encoded into an I picture. However, in the present embodiment, the reproduction image data from the decoder 5 is the same data input twice as described above. Only the data is re-encoded into an I picture. That is, 1 GOP composed of m pictures is decoded by the decoder 5 into 2m pictures, which are encoded into _m I pictures (I _{1 to} Im) by the encoder 6. The second decoder 7 includes m I-pictures (I ₁ to I _1- ) stored in the storage area 4a.
I _m ) is read back in sequence from I _m to the time axis and sequentially decoded, and at this time also, the control core circuit 10 repeatedly outputs the decoded data once. Then, the data sequence decoded by the second decoder 7 is I _m I _m I _m-1 I.
_m−1 I _m−2 I _m−2 ... I ₁ I ₁ and by inputting this reproduced image data string to the display circuit 9, a reverse reproduction screen is displayed on the display 3 at 1/2 speed. You can

The second decoder 7 also has a buffer memory (not shown) built therein, and the decoded picture data is temporarily stored and repeatedly output. The buffer memory may also be shared by the hard disk 4 and other memories. Also in this embodiment, the basic reverse reproduction operation follows the flow shown in FIG. 6, and the normal reproduction operation follows the flow shown in FIG.

As a modification of the fifth embodiment, in the image reproducing device 51 of the third embodiment shown in FIG. 8, the shared decoder 53 may be configured to repeatedly output the same picture. By doing so, it is possible to enjoy the same effects as those of the third embodiment. This embodiment has the following effects in addition to the above-described embodiment. (6) Low speed reverse reproduction can be performed, and the search function is further improved. (7) Since the encoder 6 encodes the data sequence decoded into 2m pictures by the decoder 5 into m I-pictures, the capacity of the storage area 4a does not increase as compared with the first embodiment. A slow reverse smooth playback function can be added without increasing the cost.

(Sixth Embodiment) FIG. 10 shows a block circuit of an image reproducing apparatus 1 of the sixth embodiment. In the first embodiment, the encoders 6 all generate I-pictures for reverse playback, but the present embodiment aims to improve the efficiency of the processing. 10, the same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be appropriately omitted. The new configuration in FIG. 10 is two switching circuits 100 and 200, which will be referred to as a second switching circuit 100 and a third switching circuit 200, respectively, in order to distinguish them from the switching circuit 8 shown in FIG.

The second switching circuit 100 includes the control core circuit 10
According to the control of the first node 100a, the second node 100
The connection to the b side is switched. When the second switching circuit 100 is connected to the first node 100a side, the reproduced image data generated by the decoder 5 is directly input to the switching circuit 8 and when it is connected to the second node 100b side, the decoder 5 is connected.
The reproduced image data generated by is input to the encoder 6.

The third switching circuit 200 includes the control core circuit 10
According to the control of the first node 200a, the second node 200
The connection to the b side is switched. When the third switching circuit 200 is connected to the first node 200a side, predetermined data in the MPEG video stream is stored in the storage area 4a assigned to the hard disk 4, and the second node 200 is stored.
When connected to the b side, the data generated by the encoder 6 is stored in the storage area 4a.

FIG. 11 is a block diagram showing the structure of the decoder 5. Unlike FIG. 3, the picture skip circuit 12 is replaced with a picture switching circuit 112. The picture switching circuit 112 switches connections to the first node 112a, the second node 112b, and the third node 112c side under the control of the control core circuit 10. The picture type detected by the picture header detection circuit 11 is I.
If it is a picture, the second node 1 that conducts in both directions
12b is connected to the decode core circuit 13 and the third
If it is transferred to the switching circuit 200 and the picture type is a P picture, it is connected to the first node 112a side and transferred to the decode core circuit 13, and if the picture type is a B picture, the third node 112c. And is transferred to the third switching circuit 200. The picture switching circuit 112 and the third switching circuit 200 are examples of the “assignment processing unit” in the present invention.

The internal configurations of the encoder 6 and the decoder 5 in this embodiment may be the same as those in FIGS. 4 and 5, respectively. Therefore, the MPEG video stream is first converted into a predetermined encoded data string by the decoder 5 and the encoder 6, and then, is converted via the third switching circuit 200.
It is stored in the storage area 4a allocated in the hard disk 4.

The reverse playback operation with the above configuration is shown in the flowchart of FIG. When reverse playback is instructed,
The switching circuit 8 is connected to the second node 8b (S1). MPEG equivalent to GOP _i-1 from the hard disk 4
The video stream is read out in picture units and input to the decoder 5. The picture header detection circuit 11 determines whether the type of each picture is I, P, B, and the picture switching circuit 112. , The I picture and P picture data are decoded by the decoding core circuit 13, and the I picture and B picture data are transferred to the third switching circuit 200 (S2).

Of the data decoded by the decode core circuit 13, the data obtained by decoding the P picture data is
It is input to the encoder 6 via the second node 100b of the second switching circuit 100 (S3). The data obtained by decoding the I picture data is the first node 10 of the second switching circuit 100.
Although it is input to the switching circuit 8 via 0a, the data is discarded as it is because the switching circuit 8 is connected to the second node 8b at this time. That is, this data is P
It is used for decoding picture data. The encoder 6 follows the instruction of the control core circuit 10 to include the data input from the decoder 5, including the case of the P picture,
All are re-encoded into I pictures (S4).

The third switching circuit 200 includes the control core circuit 10
Under the control of 1., the I-picture and B-picture data transferred from the picture switching circuit 112 and the re-encoded data from the encoder 6, here, the I-picture data are input to the storage area 4a of the hard disk 4 in time series. . The data of 1 GOP input to the storage area 4a is
The old data is overwritten (S5). in this way,
The encoded data string input from the third switching circuit 200 to the storage area 4a includes only I pictures and B pictures,
This encoded data string is an example of the "second encoded data string" in the present invention.

When the writing to the storage area 4a is completed,
The second decoder 7 reads the re-encoded data stored in the storage area 4a in anti-time series and sequentially decodes it.
It is output to the display circuit 9 (S6). 1 from encoder 6
The re-encoded data string of GOP includes the I picture and the B picture as described above. Therefore, in order to read the re-encoded data sequence stored in the storage area 4a retroactively on the time axis and sequentially decode it, when decoding a B picture, the forward reference area and the backward reference area of the stream input order are read. Perform the process of replacing the reference area,
Decrypt it after a while.

When the writing to the storage area 4a is completed in S5, a write end signal is sent out,
The MPEG video stream corresponding to the next GOP _i-2 is input to the encoder 5 and the processing from S2 is performed. That is, in S6, while the second decoder 7 is decoding 1 GOP worth of data, the decoder 5 is decoding the next 1 GOP worth of data.

As described above, the image reproducing apparatus 1 of the present embodiment has the following effects in addition to the above-mentioned embodiments. (8) Since data corresponding to I pictures and B pictures in the MPEG video stream is not transferred to the encoder 6, the transfer amount of data from the decoder 5 to the encoder 6 is reduced and the processing load of the encoder 6 is reduced. It
As a result, the encoder 6 having low power consumption and a small circuit area can be used. (9) Since the B picture in the MPEG video stream is stored as it is in the storage area 4a as B picture data, the capacity of the storage area 4a can be further reduced as compared with the first embodiment, and the image reproducing apparatus 1 can be miniaturized. And it can contribute to cost reduction.

(Seventh Embodiment) The seventh embodiment is a more compact design of the sixth embodiment, and their relationship is the same as the relationship between the second embodiment and the first embodiment.
Hereinafter, the same components as those in the sixth embodiment will be designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 13 shows an image reproducing apparatus 51 of this embodiment.
The block circuit of is shown. As shown in the figure, the decode core circuit 13 of the decoder 5 and the second decoder 7 are commonly used. The image reproducing device 51 includes a hard disk 4, a switching circuit 52, a shared decoder 53, an encoder 6, a second switching circuit 100, a third switching circuit 200, a display circuit 9, and a control core circuit 10. The configuration of the shared decoder 53 is the same as that of the decoder 5.

In the image reproducing device 51, the MPEG video stream from the hard disk 4 or the re-encoded data from the storage area 4a is input to the common decoder 53 via the switching circuit 52, and the output thereof is output from the second switching circuit 5.
It is input to the display circuit 9 or the encoder 6 via 4.

When the switching circuit 52 is connected to the first node 52a side, the MPEG video stream from the hard disk 4 is input to the common decoder 53, and the second node 52 is connected.
When connected to the b side, the re-encoded data from the storage area 4a is input to the shared decoder 53. When the switching circuit 52 is connected to the second node 52b side, the picture switching circuit 112 is connected to the first node 112a regardless of the type of picture.

Based on the above configuration, the switching circuit 52 is connected to the first node 52a and the second switching circuit 1 is connected during the normal reproduction.
00 is connected to the first node 100a. Therefore,
The MPEG video stream from the hard disk 4 is decoded by the shared decoder 53 and input to the display circuit 9 as it is.

On the other hand, during reverse reproduction, the control core circuit 10
First, with the switching circuit 52 connected to the first node 52a and the second switching circuit 100 connected to the second node 100b, one picture worth of image data is read from the hard disk 4. The image data is input to the switching circuit 12 of the shared decoder 53 through the first node 52a, and depending on the type of picture, the decoding core circuit 13 or the third
It is input to the switching circuit 200.

The control core circuit 10 transfers from the shared decoder 53 to the third switching circuit 200 or the MPEG encoder 6.
As soon as the picture-like playback image data is sent,
The connection of the switching circuit 52 is switched to the second node 52b, the connection of the second switching circuit 100 is switched to the first node 100a, and one picture worth of re-encoded data for reverse playback is read from the storage area 4a. The re-encoded data is
It is input to the shared decoder 53 through the second node 52b and decoded. The decrypted data is the first node 100
It is input to the display circuit 9 through a and displayed on the display 3.

The control core circuit 10 connects the switching circuit 52 to the first node 52 as soon as the reproduction image data for one picture is sent from the shared decoder 53 to the display circuit 9.
a, the connection of the second switching circuit 100 is switched to the second node 100b, and one picture worth of image data is read from the hard disk 4.

Similarly, the control core circuit 10 switches the connection state of the nodes of the switching circuits 52 and 100 each time the reproduction image data is output from the shared decoder 53.
By doing so, the shared decoder 53 performs the processing of the decoder 5 and the processing of the second decoder 7 in the sixth embodiment in a time division manner.

The basic reverse playback operation according to this embodiment follows the flow shown in FIG. However, in FIG.
The operations of the decoder 5 and the second decoder 7 are common decoders 53.
Replaces the behavior of. In the present embodiment, in addition to the effects of the sixth embodiment, the circuit area can be reduced by sharing the decoder 5 and the second decoder 7.

(Eighth Embodiment) FIG. 14 shows a block circuit of an image reproducing apparatus 1 according to an eighth embodiment. In the figure, the same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be appropriately omitted. The new configuration in FIG. 14 is a data amount reduction circuit 300 and a data amount restoration circuit 400. The former is provided on the path from the decoder 5 to the encoder 6, and the latter is provided on the path from the second decoder 7 to the switching circuit 8.

FIG. 15 is a block diagram showing the structure of the data amount reduction circuit 300. The data amount reduction circuit 300
It is composed of a digital filter unit 300a, a ROM 300b, and a timing control unit 300c. The digital filter unit 300c is composed of an FIR filter, and
6, n delay devices 300d for delaying the n-bit input signal input via the second node 8b of the switching circuit 8 for each sampling cycle, and n + 1 multipliers 300e. , And an adder 300f for convolving the signals from the multipliers 300e.
Each coefficient α _n , α _n−1, ... α ₂ , of the multiplier 300 e.
α ₁ is a coefficient that determines the characteristics of the filter, and is R in advance.
It is written in the OM 300b. The coefficient stored in the ROM 300b is set to an appropriate value in advance by simulation in the manufacturing stage.

In this embodiment, in order to reduce the number of pixels of each screen generated by the decoder 5, for example, original image data of vertical 1080 × horizontal 1920, linear interpolation or the like is used, and each screen A good low resolution image is obtained by changing the value of the coefficient.

As an example, consider a case where the number of pixels in the horizontal direction is set to 2/3. Now, assume that _three pixels p _{1 to} p ₃ are horizontally arranged in the original image. These pixels are converted into _two pixels q ₁ and q ₂ by the data amount reduction processing. For this purpose, q ₁ and q ₂ are respectively p ₁ ,
It is expressed by a linear linear sum of p ₂ and p ₃ . That is, the amount of data can be reduced by setting the ratio of the number of pixels to be reduced and then determining each coefficient of the linear sum through experiments or the like.
As one application in MPEG, the number of pixels on each screen may be reduced to, for example, 480 vertical × 720 horizontal.

FIG. 17 is a block diagram showing the structure of the data amount restoration circuit 400. The data amount restoration circuit 400
It is composed of a digital filter section 400a, a ROM 400b, and a timing control section 400c. Like the digital filter unit 300c, the digital filter unit 400c is configured by an FIR filter, and as shown in FIG. 18, n units for delaying the n-bit input signal generated by the second decoder 7 for each sampling cycle. Of delay units 400d, n + 1 multipliers 400e, and an adder 400f for convolving the signals from the multipliers 400e. The coefficients β _n , β _n−1 , ... β ₂ , β ₁ of the multiplier 400 e ... Are coefficients that determine the characteristics of the filter and are written in the ROM 400 b in advance. The coefficient stored in the ROM 400b is preset to an appropriate value by simulation in the manufacturing stage.

The data amount restoration circuit 400 converts the number of pixels of image data of each screen generated by the second decoder 7, for example, vertical 480 × horizontal 720 to the original screen of each screen generated by the decoder 5, for example, vertical 1080 × horizontal 1920. In order to restore the number of pixels of the image data, the value of each coefficient is changed for each sampling period, and the process corresponding to the inverse conversion of the above-described data amount reduction process is performed.

The reverse reproduction operation based on the above configuration is shown in FIG.
9. Follow the flowchart in 9. When reverse playback is instructed,
The switching circuit 8 is connected to the second node 8b (S1). MPEG equivalent to GOP _i-1 from the hard disk 4
The video stream is read in picture units and input to the decoder 5, reproduced image data of each screen is sequentially generated in time series, and input to the data amount reduction circuit 300 (S
2). The data amount reduction circuit 300 reduces the number of pixels of the original image data of each screen to 480 (vertical) × 720 (horizontal), and then inputs the data to the encoder 6 (S3). The encoder 6 outputs all the reproduced image data of 1 GOP input from the decoder 5 as I
The picture is re-encoded (S4). 1 GOP worth of re-encoded data from the encoder 6 is overwritten in the storage area 4a of the hard disk 4 (S5).

When the writing to the storage area 4a is completed,
The second decoder 7 reads the re-encoded data stored in the storage area 4a in anti-time series and sequentially decodes it.
Output to the data amount restoration circuit 400. When the writing to the storage area 4a is completed, a writing end signal is sent out, the MPEG video stream corresponding to the next GOP _i-2 is input to the encoder 5, and the processing from S2 is performed (S6). . That is, in S6, while the second decoder 7 is decoding 1 GOP worth of data, the decoder 5 is decoding the next 1 GOP worth of data.

The data amount restoration circuit 400 uses the number of pixels of the image data of each screen generated by the second decoder 7 as the vertical 10
After being restored to 80 × horizontal 1920, the switching circuit 8 inputs this to the display circuit 9 via the second node 8b (S7).
In this way, the reverse playback screen is displayed on the display 3.

The image reproducing apparatus 1 of the present embodiment has the following operational effects in addition to the above-mentioned embodiments. (10) Due to the operation of the data amount reduction circuit 300, MPE
The capacity of the storage area 4a can be reduced as compared with the case where all the G video streams are converted into I pictures by the encoder 6 and stored, which contributes to downsizing and cost reduction of the image reproducing apparatus 1. (11) The data amount restoration circuit 40 reduces the number of pixels once reduced.
Since it is restored by 0 and transferred to the display circuit 9,
The display image quality can be almost maintained. Note that, of course, a skip operation may be added to the present embodiment, just as the picture skip operation is added to the first embodiment in the second embodiment. Further, in this embodiment, the data amount is thinned out in units of pictures or frames, but this may be in units of fields. In the case of interlaced driving, even or odd field unit thinning is also effective.

(Ninth Embodiment) FIG. 20 shows a block circuit of an image reproducing apparatus 51 of the ninth embodiment. However, the same components as those of the eighth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. 20 is different from FIG. 14 in that the data amount reduction circuit 300 and the data amount restoration circuit 40 are different.
In addition of 0. The configuration of the shared decoder 53 is the decoder 5
Is the same as

The connection of the second switching circuit 54 to the first node 54a and the second node 54b side is switched under the control of the control core circuit 10. Then, when the second switching circuit 54 is connected to the first node 54a side, the shared decoder 53
When the reproduced image data from the shared decoder 53 is input to the data amount restoration circuit 400 and connected to the second node 54b side, the reproduced image data from the shared decoder 53 is reduced to the data amount reduction circuit 300.
Entered in.

Based on the above configuration, the switching circuit 52 is connected to the first node 52a and the second switching circuit 5 is connected during the forward reproduction.
4 is connected to the first node 54a. Therefore, the MPEG video stream from the hard disk 4 is decoded by the common decoder 53 and input to the display circuit 9 as it is. In normal-order reproduction, the data amount restoration circuit 4
00 does not operate, and the image data from the shared decoder 53 is directly transmitted to the display circuit 9.

On the other hand, during reverse reproduction, the control core circuit 10
First, with the switching circuit 52 connected to the first node 52a and the second switching circuit 54 connected to the second node 54b,
Image data for one picture is read from the hard disk 4. The image data is input to the shared decoder 53 through the first node 52a and decoded. The decoded data passes through the second node 54b and the data amount reduction circuit 3
After being processed at 00, it is input to the MPEG encoder 6 and re-encoded as an I picture.

The control core circuit 10 switches the connection of the switching circuit 52 to the second circuit immediately after the reproduction picture data of one picture is sent from the common decoder 53 to the MPEG encoder 6.
The node 52b is switched to, the connection of the second switching circuit 54 is switched to the first node 54a, and one picture worth of re-encoded data for reverse reproduction is read from the storage area 4a.
The re-encoded data is input to the shared decoder 53 through the second node 52b and decoded. The decrypted data passes through the first node 54a and the data amount restoration circuit 400
After being restored by (3), it is input to the display circuit 9 and displayed on the display 3. The control core circuit 10 switches the connection of the switching circuit 52 to the first node 52a and the connection of the second switching circuit 54 as soon as the reproduction image data for one picture is sent from the shared decoder 53 to the display circuit 8. Switching to the second node 54b, the image data of one picture is read from the hard disk 4.

Hereinafter, the processing, action, and effect are the same as those in the third embodiment. In this embodiment, the effect of the data amount reduction processing is further added. It should be noted that, in the present embodiment as well, the picture skip operation can be added as in the fourth embodiment.

(Tenth Embodiment) In the tenth embodiment, low-speed normal reproduction and reverse reproduction are realized in the image reproducing device 1 of the eighth embodiment. That is, in the configuration of FIG. 14, as described in the fifth embodiment, when the reproduced image data is output from the decoder 5, the same picture is repeatedly output once. Therefore, the present embodiment can have the effect of the eighth embodiment and the effect of reducing the amount of data.

As a modified example of the present embodiment, in the image reproducing device 51 of the ninth embodiment, the shared decoder 53 may be configured to repeatedly output the same picture. As a result, the same effect as that of the ninth embodiment can be obtained.

(Eleventh Embodiment) The eleventh embodiment relates to an example in which the image reproducing apparatus or the image processing apparatus according to any one of the above embodiments is incorporated in a television receiver. FIG. 23 is a configuration diagram thereof. Television receiver 5
At 00, broadcast wave 570 is provided to tuner 514 via antenna 512. The tuner 514 selects the transponder containing the channel selected by the user,
Perform SK demodulation. The stream including a plurality of transport pockets obtained by demodulation is sent to the packet separation unit 516. The packet separation unit 516 is a demultiplexer, and separates the packet corresponding to the desired channel and outputs it to the image / audio decoder 518.

The image / audio decoder 518 is an MPEG decoder, and incorporates the image reproducing device or the image processing device mentioned in any of the embodiments for its image processing. The image / audio decoder 518 decodes the input packet, and outputs audio data to the audio signal output unit 522 and image data to the display device 526, respectively. The voice signal output unit 522 performs a predetermined process on the input voice data, and finally the voice is output to the speaker 524.

The main control section 536 is composed of the control core circuit 10 and other CPUs and the like, and controls each section centrally in accordance with a user's instruction. The user's instruction is input, for example, via the remote controller light receiving unit 548 that receives a signal from a remote controller (not shown). The media I / F circuit 550 reads multimedia data and programs from an unillustrated IC card, MO, CD-ROM, DVD-ROM, or other recording medium into the main control unit 536. With the above configuration, image reproduction processing including normal-order reproduction and reverse-order reproduction is realized in accordance with a user's instruction. At that time, it is possible to enjoy the effects described above.

(General Consideration Regarding Embodiments) As will be understood by those skilled in the art, any combination of the embodiments not described above is possible. For example, in any case, a skip processing unit that thins out the input first encoded data string in picture units, for example, the picture skip circuit 12 may be provided. In this case, the first decoder decodes the thinned-out data string to generate a time-series continuous image data string. A discrimination unit that discriminates the type of the picture included in the input first encoded data string, for example, the picture header detection unit 11 may be further provided. In this case, the skip processing unit may preferentially thin out B pictures. Furthermore, the following consideration or modification is possible.

(A) In some embodiments, encoder 6 does not require MC circuit 20. In that case,
Since a still image compression algorithm can be applied, JPEG (Joint Photographic Coding) is used instead of the encoder 6.
Expert Group) encoder is used. The image data encoded by this JPEG encoder is also an intra-frame encoded image. In addition to JPEG, compression technology that uses still image data compression, such as differential YUV based on differential processing, block-based Hadamard transform, slant transform (Slant) transform, and Haar transform method. May be used. When the still image compression technique described above is used for the encoder 6, it is necessary to use the same still image expansion technique for the second decoder 7.

(B) Similarly, in some embodiments, the second decoder 7 does not require the MC circuit 29.
Therefore, as in (a), a JPEG decoder is used.
For decoding the intra-frame coded image, the above-mentioned difference YU
A method such as V or Hadamard transform may be used.

(C) As the hard disk 4, a magneto-optical disk, an optical disk or the like is used instead of the magnetic disk. (D) As the hard disk 4, a rewritable semiconductor memory, for example, an SDRAM (Synchronous Dynamic RA)
M), DRAM, Rambus DRAM, etc. are used. (E) The hard disk 4 and the storage area 4a are provided independently. In this case, a rewritable semiconductor memory is desirable for the storage area 4a. (F) The picture skip circuit 12 of the decoder 5 is omitted when the demand for reducing the circuit area is emphasized. In this case, the picture header detection circuit 11 may be omitted.

(G) 1G from MPEG video stream
The data string is taken out in the following units instead of OP. GOP
The following units, including, are included in the concept of group units.・
Instead of making the unit starting from the I picture a GOP, for example,
A unit starting from a P picture is a GOP. -Given the concept of GOP, group several pictures into groups. -The number of pictures can be changed arbitrarily for each group.

(H) ROM 18, 19, 24, 25, 3
A RAM (Random Access Memory) is used in place of 0 and 31. (I) As a modified example of the fifth embodiment, the processing of the decoder 5 and the encoder 6 at the time of reverse reproduction is kept the same as that of the first embodiment, and the same picture is repeatedly output only in the second decoder 7. By doing this, the decoder 5
Power consumption can be reduced. (J) In the fifth embodiment and the above (i), the number of repeated output of the same picture in the decoder 5 and the second decoder 7 is set to 2 or more. By doing so, a slower reverse playback screen can be obtained.

(K) In the fifth embodiment, the decoder 5 and the second decoder 7 are configured to repeatedly output the decoded data. However, if there is a merit in the circuit control or the timing control, they are the same. The picture may be repeatedly decoded and output. (L) In each embodiment, at the time of reverse reproduction, the I picture data in the MPEG video stream stored in the hard disk 4 is transferred to the storage area 4a without being processed by the decoder 5 and the encoder 6. By doing so, the power consumption of the decoder 5 and the encoder 6 can be reduced.

(M) In addition to (l) above, during reverse playback, B
The picture data is directly transferred to the storage area 4a without being processed by the decoder 5 and the encoder 6. By doing so, the power consumption of the decoder 5 and the encoder 6 can be reduced. In addition, all data are I
Since the picture is not re-encoded, the capacity of the storage area 4a can be reduced. However, in this case, in the second decoder 7, the forward reference area and the backward reference area of the B picture read from the storage area 4a are switched in the order of the stream for decoding. (N) The low-speed reverse order reproduction function described in the fifth embodiment, the normal reverse order reproduction function described in the first and third embodiments, and the high-speed reverse order reproduction function described in the second and fourth embodiments are installed in one image reproduction device. However, operation keys for selecting these functions are provided. (O) Playback in reverse order one frame at a time according to key operation.

(P) In addition to the above embodiments, there are the following forms as an application having two encoding or decoding functions in one device. Therefore, in the above-described third embodiment, an example in which the decoder 5 and the second decoder 7 are shared as the shared decoder 53 has been described, but in the case of having two encoders, these encoders may be shared. . (I) In the case where a movie camera simultaneously shoots subjects from different viewpoints and compresses / decompresses the data by the MPEG method. (Ii) In the case of simultaneously decoding a plurality of programs on a television and displaying them on two screens. (Iii) In the case of simultaneously decoding a plurality of programs on a television and performing channel switching seamlessly. MP
In broadcasting using EG, once decoding is interrupted due to channel switching, etc., it takes some time to restart the next 0.5 to 2 seconds until a new sequence header is detected. Freezing or blacking out, (iii) is effective in solving this problem. (Iv) In a television connected to a DVD, a digital still camera or the like, the broadcast and the DVD or the digital still camera are simultaneously reproduced. (V) When a program or other program is recorded as a movie or still image while the program is being played, and the recorded movie or still image and the program being broadcast are played back simultaneously. (Vi) A case where a reproduced image is encoded by the JPEG method at regular time intervals and fetched in a ring buffer, which is used as an index for jumping to a close scene in reverse search.

(Q) The data amount reduction circuit 300 may be configured to thin out frames instead of reducing the number of pixels. In this case, as shown in FIG. 21A, the data amount reduction circuit 300 switches the original image data of each screen generated by the decoder 5 or the shared decoder 53 in units of frame by switching the node of the data amount reduction circuit 300. Skip with. For example, by switching this node alternately for each frame, the number of frames can be reduced to 1 /
The number of frames can be reduced to 2, and by skipping 2 out of 3 frames, the number of frames can be reduced to 1/3. When the data amount reduction circuit 300 is configured as shown in FIG. 21A, the data amount restoration circuit 400 operates as shown in FIG.
As shown in (b), it is composed of a buffer memory 201 for accumulating image data of each screen generated by the second decoder 7 or the common decoder 53 and a control core circuit 10 for controlling the same, and is skipped by the data amount reduction circuit 300. Probably, the same image data is repeatedly output from the buffer memory 201. In this case, the data amount restoration circuit 40
The data amount of the image data generated by 0 is not the same as the data amount of the image data before being reduced by the data amount reduction circuit 300, but as described above, each screen generated by the second decoder 7 or the shared decoder 53 is generated. It is also possible to make the data amount of the image data of (1) close to or more than the data amount of the image data before reduction be “substantially restored”.

(R) It was necessary to store the entire image data for 1 GOP in the storage area 4a for the reverse reproduction. This is because inside the GOP, data is read out only in the forward direction, so that a picture cannot be generated during reverse playback unless all the data for 1 GOP is left. For this reason, the storage area 4a is required to have a capacity enough to record one GOP of image data. On the contrary, by effectively utilizing such a configuration, in the first embodiment and the like, the encoder 6 is allowed to run in the free run even during the forward playback, and the 1 G is always used.
It is decided to generate and store the OP data for reverse order reproduction. This was intended to smooth the switching from the normal order to the reverse order.

However, with this method, although a smoother reproduction direction change is realized as compared with the case where the free run is not performed, a time lag does not necessarily occur at the time of switching. This is because, when the reverse reproduction is performed on GOP _n, the _{GOP n-1} of the previous, it is necessary to the decoder 5 decodes reads the encoded data of 1GOP fraction, a series of processes GOP _n This is because there is a possibility that it will not be completed by the completion of reverse playback of. If it does not end, reverse playback will stop there for a moment.

As a measure against this, the storage of the image data for 1 GOP described in the first embodiment and the like is expanded to a maximum of 2 GOP.
By storing about a minute of image data, it is possible to completely eliminate the time lag when switching from the forward reproduction to the reverse reproduction. Therefore, if such specifications are required, this measure should be taken.

At this time, of course, it is necessary to increase the memory capacity. When all I pictures are re-encoded by the encoder 6, in order to suppress the memory capacity for accumulating these I pictures, I pictures are randomly generated every few pictures or the number of pixels is reduced. Or various types of intraframe compression processing can be added.

First, in the case of generating and accumulating I pictures discretely, for skipped pictures, the I picture reproduced before that may be displayed again. For example, when skipping every other image, by displaying each I picture twice, the reverse playback speed can be kept the same as the forward playback speed.
On the contrary, conversely, if the I pictures accumulated every other frame are reproduced as they are, the double speed reverse reproduction can be automatically performed, which can be naturally regarded as part of the product specifications.

In the case of reducing the number of pixels, the IDCT processing in the decoder 7 may be performed in advance by decoding in the down conversion format. That is, where normally the IDCT should be performed on a square block of 8 × 8 pixels, it may be performed on a block of 1/2 size of 8 × 4 pixels. In that case, since the capacity of the image data to be stored in the frame memory at the time of image reproduction is halved, as a result, 2 GOP's worth of I pictures can be stored in the empty area. It should be noted that when this down conversion is performed, 1960 × 10
An image of 80 pixels becomes 980 × 1080 pixels. Therefore, at the time of reproduction, resolution reproduction processing is performed, such as displaying each pixel twice in the horizontal direction.

(S) The above-mentioned time lag at the time of switching should be taken into consideration also when shifting from the reverse reproduction to the normal reproduction. At this time, the same measure as described above can be dealt with, that is, the read picture data can be accumulated by about 1 to 2 GOP. If the n-th GOP _n is currently being read for reverse reproduction, the data of the picture of this GOP _n is read by GOP _n for reverse reproduction two GOPs before that.
Hold until _n-2 is reached. That is, a GO
By holding the data of P until the reading of the data of the GOP just before that, the continuous reproduction is realized even when the switching to the normal reproduction is performed.

Since switching from the reverse order reproduction to the normal order reproduction can be dealt with only by the processing of the decoder 5, the time lag is originally small as compared with the case of (r). Therefore, 2 GOPs are used here, but in reality, at most 1 GOP seems to be sufficient. However, since this value depends on the implementation of the device, it is desirable to determine it by experimentation for each model.

(T) FIG. 22 shows the cache of an I picture.
The speeding up of the reverse playback by placing the memory will be described. I
Focusing on the fact that the picture is a "reusable picture"
It In the figure, a picture of 1 GOP is shown for the sake of simplicity.
6 sheets, GOP₁~ GOP_ThreeIn 3 GOPs
GOP₁Is I₁~ B₆, GOP _Two
Is I₇~ B₁₂, GOP_ThreeIs I_Thirteen~ B₁₈Is represented by
It

Now GOP_ThreeRequesting reverse playback from
Then, as mentioned above, GOP_ThreeReading, GOP_Twoof
Read, GOP₁Are read in this order. here
GOP_TwoIf attention is paid to the processing of, the last picture B
₁₂To play the GOP _ThreeFirst picture I
_ThirteenIs being read. However, this picture I
_ThirteenIs a GOP_ThreeWhen playing in reverse order, read already
It can be seen that it has been issued and decrypted. From this,
The decoded data of the first I picture of each GOP is encoded by the MPEG data.
Until the processing of the previous GOP on the data stream ends.
Caching in storage area 4a or other memory
If so, the picture can be read again and decoded.
You can save time. According to this caching,
The processing efficiency can be improved.

(U) In some embodiments, an I picture is generated by re-encoding by the encoder 6, and in some cases, the I picture and the B picture are combined to form encoded data for reverse reproduction. However, it is not limited to this,
The encoder 6 may implement other forms selected by those skilled in the art at the implementation stage, such as generating more I-pictures than the original I-pictures included in the original MPEG video stream. From a different point of view, the encoder 6 may encode the image data into a sequence of pictures of a type that refers to other pictures within the limit of one picture at least for the same prediction direction. The “prediction direction” is a forward direction or a backward direction, and is prediction from the past and prediction from the future, respectively. Therefore, here, a picture that refers to only 0 or 1 picture is recognized in both the forward direction and the backward direction.

In current MPEG, I picture and B
A picture meets this condition, but the essence of the problem of what kind of picture should be generated by re-encoding is that the structure originally required for normal-direction reproduction, especially that the reverse-direction reproduction can be realized while keeping the memory capacity. is there. In MPEG,
Although a P picture may refer to a plurality of pictures that are considerably distant from each other in the forward direction, in the case of normal-order reproduction, decoded pictures are sequentially output or displayed, so that a large number of pictures are retained. There is no need to continue. Conversely, since it is the normal order reproduction, the P picture can be reproduced without trouble in a relatively small frame buffer.
In the case of reverse order reproduction, many pictures must be stored for a considerable period in order to reproduce P pictures. Therefore,
In reality, for the same prediction direction, pictures that refer to two or more pictures require a relatively large memory capacity only because they are in reverse order, which is disadvantageous in terms of cost, mounting area, and the like. Therefore, it is considered necessary and sufficient to solve the problem by allowing I, B and other pictures in the same prediction direction up to one picture.

[0132]

According to the present invention, it is possible to provide an image processing technique capable of performing smooth reverse reproduction.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a hierarchical structure of an MPEG video stream.

FIG. 2 is a block circuit diagram of the image reproducing device in the first embodiment.

FIG. 3 is a block diagram showing an outline of a decoder in the first embodiment.

FIG. 4 is a block diagram showing an outline of an encoder in the first embodiment.

FIG. 5 is a block diagram showing an outline of a decoder in the first embodiment.

FIG. 6 is a flowchart showing a reverse order reproduction operation of the image reproducing apparatus in the first embodiment.

FIG. 7 is a flowchart showing a normal order reproduction operation of the image reproduction apparatus in the first embodiment.

FIG. 8 is a block circuit diagram of an image reproducing device according to a third embodiment.

FIG. 9 is an explanatory diagram illustrating a reverse-order reproduction operation of the image reproduction device in the fifth embodiment.

FIG. 10 is a block circuit diagram of an image reproducing device according to a sixth embodiment.

FIG. 11 is a block diagram showing an outline of a decoder in the sixth embodiment.

FIG. 12 is a flowchart showing a reverse reproduction operation of the image reproduction device in the sixth embodiment.

FIG. 13 is a block circuit diagram of an image reproducing device in a seventh embodiment.

FIG. 14 is a block circuit diagram of an image reproducing device according to an eighth embodiment.

FIG. 15 is a block diagram showing an outline of a data amount reduction circuit in an eighth embodiment.

16 is a circuit diagram showing an outline of the digital filter unit shown in FIG.

FIG. 17 is a block diagram showing an outline of a data amount restoration circuit in an eighth embodiment.

18 is a circuit diagram showing an outline of the digital filter unit shown in FIG.

FIG. 19 is a flowchart showing a reverse order reproduction operation of the image reproducing apparatus in the eighth embodiment.

FIG. 20 is a block circuit diagram of an image reproducing device according to a ninth embodiment.

21A and 21B are diagrams showing other circuit configuration examples of a data amount reduction circuit and a data amount restoration circuit, respectively.

[Fig. 22] Fig. 22 is a diagram for describing speeding up of reverse playback by caching I-pictures.

[Fig. 23] Fig. 23 is a configuration diagram of a television receiver in an eleventh embodiment in which any image reproducing device or image processing device according to the embodiment is incorporated.

[Explanation of symbols]

1,51 Image playback device 2 Transmission media 3 display 4 hard disk 4a storage area 5,7,53 MPEG Video Decoder 6 MPEG video encoder 8,52,54 switching circuit 9 Display circuit 10 Control core circuit 11 Picture header detection circuit 12 picture skip circuit 13 Decode core circuit 14,26 Huffman decoding circuit 15,27 Dequantization circuit 16, 28 IDCT circuit 17, 20, 29 MC circuit 18, 19, 24, 25, 30, 31 ROM 100 Second switching circuit 112 picture switching circuit 200 Third switching circuit 300 Data reduction circuit 400 data amount restoration circuit 500 television receiver

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-11-252507 (JP, A) JP-A-9-55946 (JP, A) JP-A-11-205739 (JP, A) JP-A-8- 242426 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N ^7/ 24-7/68 G11B 20/10-20/12

Claims (12)

(57) [Claims] 1. A first coded data string including an I picture, a P picture and a B picture coded according to MPEG is converted into a second coded data string composed of an I picture and a B picture. A converter, a post-decoder for decoding the second coded data sequence generated by the converter in anti-time series, and a control unit for controlling the operations of the converter and the post-decoder. An image processing apparatus comprising: 2. The pre-decoder for decoding at least P picture data in the first coded data string, and the MPEG data for decoding the pre-decoder.
The image processing apparatus according to claim 1, further comprising: an encoder that encodes as an I picture in conformity with the above, and a storage unit that stores the second encoded data string. 3. Under the control of the control unit, the B picture included in the first encoded data string is used as the B picture included in the second encoded data string by the predecoder and the encoder. The image processing apparatus according to claim 2, further comprising an allocation control unit that allocates the processing without performing processing. 4. Under the control of the control unit, the predecoder includes an I picture and a P picture in the first encoded data sequence.
4. The image processing apparatus according to claim 2, wherein the picture data is decoded, and the data obtained by decoding the P picture is sent to the encoder. 5. Under the control of the control unit, the I-picture and the B-picture included in the first encoded data sequence are pre-decoded as the I-picture and the B-picture included in the second encoded data sequence. The image processing apparatus according to claim 2, further comprising: an allocation control unit that directly allocates the data without performing processing by the encoder and the encoder. 6. The first encoded data sequence is data in which the pictures are assigned in a predetermined order in a predetermined group unit and encoded, and each process by the converter and the post-decoder is performed. The image processing apparatus according to any one of claims 1 to 5, wherein is performed in units of the predetermined group. 7. The image processing apparatus according to claim 6, wherein the encoded data of the next group is processed by the converter during the processing of the post-decoder. 8. A first coded data string including an I picture, a P picture, and a B picture coded according to MPEG is converted into a second coded data string including an I picture and a B picture. An image processing method comprising: a process; and a process of decoding the second coded data sequence in anti-time series. 9. The data other than at least a B picture in the first coded data string is coded as an I picture in accordance with MPEG, and the other data is directly assigned to the second coded data string. The image processing method according to claim 8, which is characterized. 10. The first encoded data sequence is data in which the pictures are assigned and encoded in a predetermined order in a predetermined group unit, and the conversion processing and the decoding processing are performed by the predetermined processing. The image processing method according to claim 8 or 9, wherein the image processing method is performed for each group. 11. The image processing method according to claim 10, wherein the conversion processing is executed based on the encoded data of the next group during the execution of the decoding processing. 12. A television receiver equipped with the image processing apparatus according to claim 1, and having an anti-time series reproduction of an image as a part of operation specifications.