JP2001069414A - Digital broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital broadcast receiver that reduces a time caused at channel switching during which an image signal cannot be restored so as to smoothly switch channels. SOLUTION: This digital broadcast receiver uses a group of picture header detection circuit 20, a period detection circuit 21, a reference signal generating circuit 22, and a phase detection circuit 23 to obtain phase information 203 to detect a group of picture header from a compressed signal 103 for each program and a memory 30 stores the values of them. In the case of switching channels, the phase information stored in the memory 30 as to a succeeding program is fed to a program number delay circuit 24. The program number delay circuit 24 delays a set program number 113 according to the received phase information 205 and gives the delayed number to a program extract separation circuit 12. Thus, an AV decoder 13 starts decoding the compressed signal 103 at a point of time when the group of picture header is detected in the compressed signal 103 of the next program.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiver, and more particularly, to a digital broadcast receiver that performs smooth channel switching.

[0002]

2. Description of the Related Art Digital broadcasting and DSM (Digital St.) have been developed using digital compression technology developed in recent years.
In fields such as image media, various devices using a digitally compressed image restoration device have begun to be put into practical use.

FIG. 14 is a block diagram showing a configuration of a standard digital satellite broadcast receiver which is an example of a digital broadcast receiver. In the digital broadcast receiver shown in FIG. 14, a tuner 10 is an LNB (Low) for BS, CS,
Noise Block down convert
A desired physical channel is selected from the intermediate frequency 100 output from r), and the selected intermediate frequency 101 is output. The transmission path decoding circuit 11 reproduces a multiplexed signal 102 including a plurality of programs from the selected intermediate frequency 101. The program extraction / separation circuit 12 selects a program having a program number 113 specified by a microcomputer 15 from the multiplexed signal 102 and outputs a compressed signal 103 of the specified program. The compressed signal 103 is MPEG
PES (Packed Ele) specified by the standard
mental stream) or ES (Elem)
entry stream or the like.

[0004] The AV decoder 13 restores an image signal 104 and an audio signal 105 from the compressed signal 103. On-screen data 114 specified by the microcomputer 15 is combined with the image signal 104 as necessary. The digital video encoder 14 converts the image signal 104 into NT
Baseband signal 106 such as SC format or PAL format
Convert to Baseband signal 106 and audio signal 105
Is output to a television monitor (not shown) connected to the digital broadcast receiver.

[0005] The microcomputer 15 controls the entire digital broadcast receiver. The timer 16 supplies time information 110 to the microcomputer 15. The program number setting circuit 17 outputs an IR (Infrared) code 1 output from a remote controller or the like.
11 and outputs the program number 112 to the microcomputer 15. At the time of channel switching, the microcomputer 15 receives the next program number 112 from the program number setting circuit 17,
The same number is used as the program number 113 as the program extraction / separation circuit 12.
Output to

With the above configuration, the designated program is reproduced on a television monitor (not shown) connected to the digital broadcast receiver.

FIG. 15 is a diagram for explaining the operation of a conventional digital broadcast receiver when a program is switched from program 1 to program 2. However, the compressed signal 10
3 is in ES format. Hereinafter, with reference to FIG.
A channel switching operation in a conventional digital broadcast receiver will be described.

As shown in FIG. 15, a compressed signal 103 is
GOP (Group Of) defined by the MPEG standard
(Picture) as a unit. At the beginning of each GOP, a GOP header (Group O
f Picture Header (hereinafter abbreviated as GH). At the beginning of each GH and the compressed signal 103 following each GH, each GOP such as the screen size
The information necessary for restoring is stored. Therefore, when restoring the compressed signal 103, the AV decoder 13 first detects GH from the compressed signal 103, extracts information necessary for restoring the GOP, and then restores the GOP following the GH. Start. The GH is added to the compression signal at a constant cycle for each application device. For example, in digital satellite broadcasting, GH is added to a compressed signal at intervals of about 0.5 seconds in consideration of responsiveness at the time of channel switching.

[0009] In FIG.
Is instructed to switch to program 2 in the middle of. In the conventional digital broadcast receiver, when receiving the next program number 112 from the program number setting circuit 17, the microcomputer 15 outputs the same number as the program number 113 to the program extraction / separation circuit 12. Upon receiving the next program number 113, the program extraction / separation circuit 12 immediately receives the compressed signal 103 of the program 2.
Start outputting. However, the AV decoder 13
When receiving the compressed signal of program 2, GH is first detected from the compressed signal, and then the restoration of the compressed signal is started. For this reason, the AV decoder 13 cannot restore the compressed signal 103 during the period from when the program switching instruction is given to when GH is detected in the compressed signal of the program 2.

[0010]

As described above, according to the conventional digital broadcast receiver, the period from when the channel switching is instructed to when the GH is detected in the compressed signal 103 of the program after the switching, The AV decoder 13 cannot restore the compressed signal 103. For this reason, the conventional digital broadcast receiver outputs a still screen indicating that the program is being switched using the on-screen data 114 without reproducing either the program 1 or the program 2 during this period. As described above, the conventional digital broadcast receiver has a problem that responsiveness at the time of channel switching is poor.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a digital broadcast receiver capable of shortening the time during which an image generated during channel switching cannot be restored and performing smooth channel switching.

[0012]

A first aspect of the present invention is a digital broadcast receiver for restoring a video and audio signal of a set program from a multiplexed signal in which a plurality of programs are multiplexed. Program number setting means for setting a program number, program extraction / separation means for extracting a compressed signal of the set program number from the multiplexed signal, and video / audio for restoring a video / audio signal from the extracted compressed signal. Decompression means, group of picture header detection means for detecting a group of picture header included in the compressed signal of each program number from the multiplexed signal and generating a detection signal, and cycle detection for detecting the cycle of the detection signal Means, reference signal generation means for generating a reference signal pulse for each cycle detected by the cycle detection means, and the detection signal for the reference signal pulse. Phase detection means for detecting the phase of, a memory means for holding the phase detected by the phase detection means for each program number as phase information, when the program number set by the program number setting means changes, Obtain a predicted phase based on the phase information held in the memory for the program number after the change, until the phase with respect to the reference signal pulse matches the predicted phase,
Program number delay means for delaying the changed program number and supplying it to the program extraction / separation means.

According to the first aspect, at the time of channel switching, the timing at which the group of picture header is detected in the compressed signal of the next program is predicted using the phase information detected in the past for the program. Then, switching to the next program is performed at the predicted timing. For this reason, it is possible to shorten the time during which the image signal generated until the group of picture header is detected in the compressed signal of the next program cannot be restored, and to perform smooth channel switching.

In a second aspect based on the first aspect, the group of picture header detecting means detects a group of picture header included in a compressed signal of a program number set by the program number setting means. Features.

According to the second aspect, the group of picture header included in the compressed signal of the program number set by the program number setting means can be detected from the compressed signal extracted by the program extraction / separation means. In addition, the group of picture header detection circuit can be configured with a small circuit amount.

In a third aspect based on the first aspect, the group of picture header detecting means sequentially generates a program number and detects a group of picture header included in a compressed signal of the generated program number. It is characterized by the following.

According to the third aspect, the phase information for each program is obtained independently of the program to be restored. Therefore, even when the next program is not restored from the initial state at the time of channel switching, the time during which the image signal generated until GH is detected in the compressed signal of the next program cannot be restored. Shorter and smoother channel switching can be performed.

In a fourth aspect based on the first aspect, the predicted phase obtained by the program number delay means is equal to the phase information held in the memory for the changed program number. And

According to the fourth aspect, there is no need for an arithmetic circuit for obtaining the predicted phase.

In a fifth aspect based on the first aspect, the predicted phase obtained by the program number delay means is obtained by subtracting a predetermined value from the phase information held in the memory for the changed program number. Characterized in that

According to the fifth aspect of the invention, the program extraction / separation means transmits the changed program to the program extraction / separation means a predetermined time before the time at which the group of picture header is detected in the compressed signal of the changed program number. The number is supplied. For this reason, the video and audio restoration unit can more reliably detect the group of picture header included in the head of the compressed signal of the changed program number.

In a sixth aspect based on the first aspect, the apparatus further comprises a time detecting means for detecting a time at which the detection signal is generated, wherein the memory means stores the phase detected by the phase detecting means, The time detected by the detection means, as the phase information and time information, respectively,
Holding at least two sets, the program number delay means,
Correction coefficient calculation means for obtaining a correction coefficient based on the phase information and the time information held in the memory means,
A phase shift correcting unit for obtaining the predicted phase based on the phase information and the time information held in the memory unit and the correction coefficient obtained by the correction coefficient calculating unit is provided.

According to the sixth aspect, at the time of channel switching, the timing at which the group of picture header is detected in the compressed signal of the next program is determined based on two or more phase information detected in the past for the program. And time information, and switching to the next program is performed at the predicted timing. For this reason, it is possible to shorten the time during which the image signal generated until the group of picture header is detected in the compressed signal of the next program cannot be restored, and to perform smooth channel switching.

Further, a correction coefficient for correcting a phase shift is obtained by using two or more pieces of phase information and time information detected in the past, and a group of picture header is generated in a compressed signal of the next program using the obtained correction coefficient. Is predicted, the cycle of the reference signal pulse and the cycle of the detection signal of the group of picture header do not completely match, and a shift that increases at a certain rate at the time when two signals occur is generated. Even in this case, the shift can be corrected and the timing at which the group of picture header is detected in the compressed signal of the next program can be obtained. For this reason, even when the cycle of the reference signal pulse does not completely match the cycle of the detection signal of the group of picture header, the image signal generated until the group of picture header is detected in the compressed signal of the next program cannot be restored. The time can be reduced and the channel can be switched smoothly.

In a seventh aspect based on the sixth aspect, the phase shift correcting means includes a subtractor for obtaining a difference between a current time and the time information obtained immediately before, and an output of the subtractor and the correction. A multiplier for obtaining a product of the correction coefficient obtained by the coefficient calculating means, an adder for obtaining a sum of the output of the multiplier and the phase information obtained immediately before, and a period detection for the output of the adder. And a remainder calculator for calculating a remainder modulo the period detected by the means.

According to the seventh aspect, the period of the reference signal pulse and the period of the detection signal of the group of picture header are obtained by using the phase information and time information obtained immediately before, the correction coefficient, and the current time. Is not completely matched, the timing at which the group of picture header is detected in the compressed signal of the next program can be obtained.

In an eighth aspect based on the first aspect, the period detecting means comprises two registers for holding the time at which the detection signal is generated twice, and a time count for the time held by the two registers. A subtractor for obtaining a difference, wherein the phase detecting means includes a counting means initialized by the reference signal pulse, and a register for taking in a count value by the counting means when the detection signal is generated, wherein the program The number delay means includes delay means for delaying the reference signal pulse by the time of the predicted phase, and a register for receiving the changed program number when the delayed reference signal pulse is generated. .

According to the eighth aspect, the period detecting means can determine the period of the detection signal of the group of picture header, and the phase detecting means can determine the phase of the detection signal of the group of picture header with respect to the reference signal pulse. Can be detected, and the program number delay means can delay the set program number until the phase with respect to the reference signal pulse matches the supplied phase information.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiver according to the first embodiment of the present invention. This digital broadcast receiver has a GH detection circuit 20, a cycle detection circuit 21, a reference signal generation circuit 22, a phase detection circuit 23, a program number delay circuit in addition to the components of the conventional digital broadcast receiver shown in FIG. 24, and a memory 30. 2, 3, and 4 illustrate a cycle detection circuit 21, a phase detection circuit 23, and a program number delay circuit 2, respectively.
4 is a circuit diagram showing the configuration of FIG. 4 in more detail. Among the components of the present embodiment, the same components as those of the conventional digital broadcast receiver shown in FIG. 14 are denoted by the same reference numerals, and description thereof is omitted.

The GH detection circuit 20 detects a GH included in the compressed signal 103, and outputs a GH detection signal 200 when detecting the GH. The cycle detection circuit 21 includes a switch 40, a first register 41, a second register 42, and a subtractor 43, as shown in FIG. Switch 40
Allows the GH detection signal 200 to pass while the microcomputer 15 outputs the cycle detection instruction signal 210. The first register 41 captures the time information 110 in accordance with the GH detection signal after passing through the switch 40, and stores the value as GH.
Output as the detection time 300. Second register 42
Captures the output of the first register 41 according to the GH detection signal after passing through the switch 40, and outputs the GH detection time obtained two times before. The subtractor 43 calculates a GH period 20 which is a difference between the GH detection times held in the two registers.
Find 1 As described above, the cycle detection circuit 21 determines the cycle of GH included in the compressed signal 103.

The reference signal generation circuit 22 includes the cycle detection circuit 2
1 and receives the supply of the GH cycle 201, and generates a reference signal pulse 202 having this value as the cycle. The phase detection circuit 23 includes a counter 50 and a register 51, as shown in FIG. The counter 50 is initialized by the reference signal pulse 202 and counts a system clock. The register 51 sets the count value of the counter 50 to G
At the time when the H detection signal 200 is generated, it is captured and its value is output as phase information 203. As described above, the phase detection circuit 23 uses the GH based on the reference signal pulse 202 as a reference.
The phase of the detection signal 200 is obtained.

The phase information 203 obtained by the phase detection circuit 23 is stored in the memory 30. FIG.
It is a figure showing an example of the storage contents of 0. As shown in FIG. 5, the memory 30 stores phase information obtained for each program.

The program number delay circuit 24 is provided between the microcomputer 15 and the program extraction / separation circuit 12,
Has a function of delaying the program number 113 output from. The program number delay circuit 24, as shown in FIG.
A delay circuit 60 and a register 61 are provided. Delay circuit 60
Delays the reference signal pulse 202 by the phase information 205 output from the microcomputer 15. Register 61
Is the program number 11 output from the microcomputer 15 when the reference signal pulse after passing through the delay circuit 60 is generated.
3 and outputs the value as a delayed program number 206. As described above, the program number delay circuit 24 has a function of delaying the program number 113 until the phase based on the reference signal pulse 202 matches the phase information 205. Delayed program number 20 output by program number delay circuit 24
Reference numeral 6 is used for program selection in the program extraction / separation circuit 12.

The operation of the digital broadcast receiver according to the present embodiment when switching channels from program 1 to program 2 will be described. First, an operation before channel switching will be described with reference to a signal waveform diagram shown in FIG.

While the program 1 is being decompressed, the compressed signal 103 output from the program extraction / separation circuit 12
Consists of OP. The GH detection circuit 20 detects the GH from the compressed signal 103, and when detecting the GH, the GH detection signal 2
00 is output. The microcomputer 15 outputs the cycle detection instruction signal 210 for a period of two cycles of GH. The period detection circuit 21 calculates the period of the GH detection signal 200 during the period when the period detection instruction signal 210 is being output, and outputs the value as the GH period 201. The GH cycle 201 is supplied to the reference signal generation circuit 22.

The reference signal generation circuit 22 generates a reference signal pulse 202 whose cycle is equal to the GH cycle 201. The reference signal pulse 202 is supplied to the phase detection circuit 23 and the program number delay circuit 24. The phase detection circuit 23 outputs the GH detection signal 200 based on the reference signal pulse 202.
And the value is output as phase information 203.

The microcomputer 15 outputs the same program number as the program number 112 input from the program number setting circuit 17 as the memory data 204 and stores it in the memory 30. When the program number setting circuit 17 outputs the next program number 112, the microcomputer 15 outputs a channel switching instruction signal 211. Channel switching instruction signal 21
When 1 is output, the phase information 203 obtained by the phase detection circuit 23 is stored in the memory 30 as phase information for the program number stored immediately before by the microcomputer 15. Thus, every time a program is switched, the program number and the phase information of the program selected immediately before the switching are stored in the memory 30.

Next, referring to the signal waveform diagram shown in FIG.
The operation after channel switching will be described.

The program number setting circuit 17 sets the next program number 11
When the microcomputer 15 outputs “2”, the microcomputer 15
Is read out as the memory data 204 for the next program stored in. This phase information is a value obtained by calculating the phase of GH included in the compressed signal 103 of the next program with reference to the reference signal pulse 202, and corresponds to a period B in FIG.

Next, the microcomputer 15 outputs the next program number and its phase information as a program number 113 and phase information 205, respectively, and at the same time, outputs a channel switching instruction signal 211. The program number 113 is supplied to the AV decoder 13 and the program number delay circuit 24. Upon receiving the program number 113, the AV decoder 13 regards the data as on-screen data, combines data indicating that the channel is being switched with the image signal 104, and outputs the image signal 104. As a result, a message indicating that the channel is being changed is displayed on a television monitor (not shown) connected to the digital broadcast receiver.

The program number delay circuit 24 delays the program number 113 output from the microcomputer 15 until the phase based on the reference signal pulse 202 matches the phase information 205, and outputs the result as a delayed program number 206. . The program extraction / separation circuit 12 selects a program according to the delayed program number 206 and outputs a compressed signal 103 of the selected program.

FIG. 8 is a diagram for explaining the effect of the digital broadcast receiver according to the present embodiment. GH is added to the compressed signal 103 of each program at a constant cycle (about 0.5 seconds). Therefore, regardless of which program is being reproduced, the G obtained by the cycle detection circuit 21
The H cycle 201 has a constant value. The phase information obtained for each program has a constant value for each program. FIG. 8 shows that the phase information for the program 1 and the program 2 is a value A and a value B, respectively, and indicates that both are constant for each program. As can be seen from FIG. 8, in order to reduce the time during which the image signal cannot be restored when switching from the program 1 to the program 2, when the phase with respect to the reference signal pulse 202 becomes the value B,
The compressed signal 103 may be switched from program 1 to program 2.

In the digital broadcast receiver according to the present embodiment, at the time of channel switching, the microcomputer 15
The memory 3 stores the phase information previously obtained for the next program number.
It reads from 0 and outputs the value to the program number delay circuit 24 as phase information 205. The program number delay circuit 24
The phase based on the reference signal pulse 202 is the phase information 20.
The program number 113 is delayed until it matches 5. Therefore, the delayed program number 206 is the compressed signal 103 of the program 2
Changes to a new program number when GH is detected. Therefore, immediately after the delay program number 206 changes, GH is detected in the compressed signal 103 of the program 2. Therefore, the AV decoder 13 can immediately start restoring the program 2.

As described above, according to the present embodiment,
At the time of channel switching, it is possible to reduce the time during which an image signal generated before GH is detected in a compressed signal of a new program cannot be restored, and to realize a digital broadcast receiver capable of performing smooth channel switching.

In the above description, it has been assumed that GH is added to the compressed signal 103 of each program at regular intervals. However, there is a slight error in the frequency of a clock used when a broadcast station creates a compressed signal for each program. For this reason, a slight error occurs in the cycle in which GH is detected in the compressed signal 103 of each program for each program. To eliminate the effects of this error,
The microcomputer 15 calculates a value obtained by subtracting a predetermined value from the phase information stored in the memory 30 for the next program,
05 may be output to the program number delay circuit 24. By using such a value as the phase information 205,
The delay program number 206 is switched to the next program number a predetermined time before the time when GH is detected in the compressed signal of the next program. Therefore, the AV decoder 13
Is G included in the head of the compressed signal 103 of the next program.
H can be detected more reliably.

The phase information 2 output by the microcomputer 15
05 is not limited to this. Microcomputer 15
Predicts the phase at which GH is detected in the compressed signal 103 of the next program by another method based on the phase information stored in the memory 30 for the next program, and uses the predicted phase as phase information 205 as the program information. It can be output to the number delay circuit 24.

<Second Embodiment> Hereinafter, FIGS. 9 to 12 will be described.
The second embodiment of the present invention will be described with reference to FIGS.

FIG. 9 is a block diagram showing a configuration of a digital broadcast receiver according to the second embodiment of the present invention. This embodiment is different from the first embodiment in that the content stored in the memory 30 and the period detection circuit 21
And the point that the phase shift correction circuit 25 is newly provided. Among the components of the present embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 10 shows a memory 30 according to the present embodiment.
FIG. 4 is a diagram showing an example of the stored contents of the above. In the memory 30 in the first embodiment, phase information for each program is stored. In contrast, as shown in FIG. 10, the memory 30 in the present embodiment stores a GH cycle, phase information and detection times for the past two times for each program, and a correction coefficient. The GH cycle is the GH cycle 201 obtained by the cycle detection circuit 21. The phase information is the phase information 203 obtained by the phase detection circuit 23. The detection time is the GH detection time 3 obtained by the cycle detection circuit 21.
00. The correction coefficient is a value indicating a deviation of the phase information per unit time obtained by the following equation (1).

ΑX = (Xc−Xp) / (tXc−tXp) (1) where Xc and tXc are the phase information and the detection time obtained immediately before, respectively, and Xp and tXp are respectively obtained two times before. Phase information and the detection time.

The operation of the digital broadcast receiver according to the present embodiment when the channel is switched from program 1 to program 2 will be described. First, an operation before switching channels will be described.

In the digital broadcast receiver according to the present embodiment, the GH detection circuit 20, cycle detection circuit 21, reference signal generation circuit 22, and phase detection circuit 23 operate in the same manner as in the first embodiment. However, the cycle detection circuit 21
In addition to the GH period 201, a GH detection time 300 output from the first register 41 is output. By the operation of these circuits, similarly to the first embodiment, each time a program is switched, the GH cycle obtained immediately before, the program number, the phase information, and the detection time of the program selected immediately before the switch are performed. Are stored in the memory 30. In the memory 30,
The phase information and time information obtained in this way are
It is stored in batches. The microcomputer 15 reads out these values stored in the memory 30 as memory data 204,
The correction coefficient α is obtained using the equation (1), and the value is stored in the memory 30 again.

Next, the operation after channel switching will be described. When the microcomputer 15 receives the next program number 112 from the program number setting circuit 17, first, the G
The H cycle, the phase information and the time information obtained immediately before the next program, and the correction coefficient are read from the memory 30 as the memory data 204. Next, microcomputer 1
5, according to the channel switching instruction signal 211,
These values are output to the phase shift correction circuit 25 as the phase time information 301.

FIG. 11 is a circuit diagram showing a more detailed configuration of the phase shift correction circuit 25. This phase shift correction circuit 2
5, a channel switching instruction signal 211 and phase time information 301 output from the microcomputer 15 and time information 110 output from the timer 16 are input. FIG.
Xc, tXc, and αX in 1 are the phase information obtained immediately before the next program, the detection time obtained immediately before, and the correction coefficient, respectively, and T is the GH cycle obtained immediately before. . All of these values are included in the phase time information 301 output by the microcomputer 15. Also,
The phase shift correction circuit 25 includes a first register 70, a second register 71, a third register 72, a fourth register 73, a subtractor 74, a multiplier 75, an adder 76, and a remainder calculator 77. Prepare. The first register 70, the second register 71, the third register 72, and the fourth register 73 respectively include a correction coefficient αX and a correction coefficient αX when the microcomputer 15 outputs the channel switching instruction signal 211.
The detection time tXc, the time information 110, and the phase information Xc, obtained immediately before, are acquired.

The subtractor 74 calculates the difference between the time information 110 and the detection time tXc obtained immediately before. The multiplier 75
The product of the output of the subtractor 74 and the correction coefficient αX is obtained. The adder 76 calculates the sum of the output of the multiplier 75 and the phase information Xc obtained immediately before. The remainder calculator 77 performs a remainder calculation on the output of the adder 76 by modulating the GH cycle obtained immediately before, and outputs the result as corrected phase information 302. That is, the phase shift correction circuit 25 outputs correction phase information Xm obtained by the following equation (2).

Xm = ｛(t−tXc) × αX + Xc｝ modT (2) where Xm, t, tXc, αX, Xc, and T are correction phase information, time information, and the detection time obtained immediately before. , A correction coefficient, phase information obtained immediately before, and a GH cycle obtained immediately before.

The correction phase information 302 output from the phase shift correction circuit 25 is supplied to the program number delay circuit 24. As in the first embodiment, the program number delay circuit 24 delays the program number 113 until the phase based on the reference signal pulse 202 coincides with the set correction phase information 302, and compares the result with the delayed program number. Output as 206. The program extraction / separation circuit 12 selects a program according to the delayed program number 206 and outputs a compressed signal 103 of the selected program.

FIG. 12 is a diagram for explaining the effect of the digital broadcast receiver according to the present embodiment. In FIG. 12, it is assumed that the cycle of the reference signal pulse 202 does not coincide with the cycle in which GH is detected in the compressed signal 103 of the program 2. FIG. 12 shows that GH is detected at time tBi (i is an integer) in the compressed signal 103 of Program 2, and that the phase information at that time is a value Bi (i is an integer).

In the digital broadcast receiver according to the present embodiment, the difference between the phase information is considered to be proportional to the difference between the time information,
By extrapolation using equations (1) and (2), the corrected phase information 302 is obtained using the previously obtained two pieces of phase information and time information and the current time information. Therefore, according to the present embodiment, the cycle of the reference signal pulse 202 does not completely match the cycle of the GH detection signal 200,
Even when a shift that increases at a fixed rate occurs at the time when two signals occur, the shift can be corrected and the timing at which GH is detected in the compressed signal of the next program can be obtained. Therefore, even when the cycle of the reference signal pulse and the cycle of the GH detection signal do not completely coincide with each other, the time during which the image signal generated until the GH is detected in the compressed signal of the next program can not be restored is reduced, and the smoothness is reduced. Channel switching can be performed.

The correction phase information 302 output from the phase shift correction circuit 25 is not limited to this. In the microcomputer 15 and the phase shift correction circuit 25, based on the phase information and the time information stored in the memory 30 for the next program, the GH in the compressed signal 103 of the next program is used.
Is detected by another method, and the predicted phase is used as the corrected phase information 302 as the program number delay circuit 24.
Can be output to

<Third Embodiment> Hereinafter, a third embodiment of the present invention will be described with reference to FIG.

FIG. 13 is a block diagram showing a configuration of a digital broadcast receiver according to the third embodiment of the present invention. This embodiment is different from the first embodiment in that a second tuner 80, a second transmission line decoding circuit 81, a second program extraction / separation circuit 82, and a GH detection control circuit 83 are newly provided. In the first embodiment, the detection of the GH phase is controlled by the microcomputer 15, whereas in the present embodiment, the GH phase is detected.
The phase detection is controlled by the GH detection control circuit 83. Among the components of the present embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The GH detection control circuit 83 sequentially switches and outputs the program number 130 independently of the program number 112 of the restored program. For example, the GH detection control circuit 83 sequentially switches and outputs all possible program numbers every time the phase information 203 is detected by the phase detection circuit 23. Second tuner 80, second transmission line decoding circuit 81, and second program extraction / separation circuit 82
Selects a program having the program number 130 specified by the GH detection control circuit 83 from the intermediate frequency 100, and outputs a compressed signal 123 of the program number 130. Compressed signal 123
Is input to the GH detection circuit 20.

The GH detection circuit 20, period detection circuit 21, reference signal generation circuit 22, and phase detection circuit 23
Operates in the same manner as in the first embodiment, and obtains the phase information 203 for the program with the program number 130. However, in the first embodiment, the cycle detection instruction signal 210 input to the cycle detection circuit 21 is omitted in the present embodiment because it always takes a value indicating the detection of the cycle. When the GH detection control circuit 83 outputs the phase information write signal 131, the program number 130 output by the GH detection control circuit 83
And phase information 203 detected by the phase detection circuit 23
Is written into the memory 30. As a result, the phase information of all the programs is stored in the memory 30 independently of the restored program. The operations of the microcomputer 15 and the program number delay circuit 24 when switching channels are as follows.
This is the same as in the first embodiment.

In the present embodiment, the phase information for all programs is obtained independently of the restored program. Therefore, even when the next program is not restored from the initial state at the time of channel switching, the time during which the image signal generated until GH is detected in the compressed signal of the next program cannot be restored. Shorter and smoother channel switching can be performed.

Note that, in the first to third embodiments, the configuration examples using hardware have been described, but a part of these functions can be realized by software of the microcomputer 15.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital broadcast receiver according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a cycle detection circuit in the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a phase detection circuit in the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a program number delay circuit in the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of contents stored in a memory in the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 6 is a signal waveform diagram for explaining an operation before channel switching of the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 7 is a signal waveform diagram for explaining an operation after channel switching of the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 8 is a diagram for explaining an effect of the digital broadcast receiver according to the first embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a digital broadcast receiver according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of storage contents of a memory in a digital broadcast receiver according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram of a phase shift circuit in a digital broadcast receiver according to a second embodiment of the present invention.

FIG. 12 is a diagram for explaining an effect of the digital broadcast receiver according to the second embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a digital broadcast receiver according to a third embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional digital broadcast receiver.

FIG. 15 is a diagram for explaining a channel switching operation of a conventional digital broadcast receiver.

[Explanation of symbols]

 12, 82 program extraction / separation circuit 13 AV decoder 15 microcomputer 17 program number setting circuit 20 GH detection circuit 21 period detection circuit 22 reference signal generation circuit 23 phase detection circuit 24 program number delay circuit 25 Phase shift correction circuit 30 Memory 41 First register 42 Second register 43, 74 Subtractor 50 Counter 51, 61 Register 60 Delay circuit 75 Multiplier 76 Adder 77 Remainder calculator 83 GH detection control circuit 102, 122 multiplexed signal 103, 123 compressed signal 104 image signal 105 audio signal 112, 113, 130 program number 200 GH detection signal 201 GH cycle 202 reference signal pulse 203 , 205: phase information 206: delayed program number 300: GH detection time 301: phase time information 302 Correction phase information

Claims (8)

[Claims] 1. A digital broadcast receiver for restoring a video and audio signal of a set program from a multiplexed signal in which a plurality of programs are multiplexed, comprising: a program number setting means for setting a program number; Program extraction / separation means for extracting a compressed signal of the set program number from the multiplexed signal; image / audio restoration means for restoring an image / audio signal from the extracted compressed signal; and compression of each program number from the multiplexed signal. A group of picture header detecting means for detecting a group of picture header included in the signal and generating a detection signal; a cycle detecting means for detecting a cycle of the detection signal; and for each cycle detected by the cycle detecting means. Reference signal generation means for generating a reference signal pulse; phase detection means for detecting the phase of the detection signal with respect to the reference signal pulse; Memory means for holding the phase detected by the phase detecting means as phase information with respect to the program number, and when the program number set by the program number setting means changes, the program number after the change is held in the memory. Calculating a predicted phase based on the phase information, and delaying the changed program number until the phase with respect to the reference signal pulse matches the predicted phase, and supplying the program number to the program extraction / separation means. Equipped with a digital broadcast receiver. 2. The apparatus according to claim 1, wherein said group of picture header detecting means detects a group of picture header included in a compressed signal of a program number set by said program number setting means. Digital broadcast receiver. 3. The apparatus according to claim 1, wherein said group of picture header detecting means sequentially generates a program number and detects a group of picture header included in a compressed signal of said generated program number. Digital broadcast receiver as described. 4. The method according to claim 1, wherein the predicted phase obtained by the program number delay unit is equal to the phase information held in the memory for the changed program number.
The digital broadcast receiver according to claim 1. 5. The method according to claim 1, wherein the predicted phase obtained by the program number delay unit is a value obtained by subtracting a predetermined value from the phase information held in the memory for the changed program number. The digital broadcast receiver according to claim 1. 6. A time detecting means for detecting a time at which the detection signal is generated, wherein the memory means detects a phase detected by the phase detecting means and a time detected by the time detecting means, respectively. Holding at least two sets as phase information and time information; the program number delaying means; a correction coefficient calculating means for obtaining a correction coefficient based on the phase information and the time information held in the memory means; 2. The apparatus according to claim 1, further comprising a phase shift correction unit that calculates the predicted phase based on the phase information and the time information held by the unit and a correction coefficient obtained by the correction coefficient calculation unit. Digital broadcast receiver. 7. A phase shift correcting means, comprising: a subtractor for obtaining a difference between a current time and the time information obtained immediately before; and an output of the subtractor and a correction coefficient obtained by the correction coefficient calculating means. A multiplier that calculates the sum of the output of the multiplier and the phase information obtained immediately before; a multiplier that calculates a cycle of the output of the adder detected by the cycle detector. The digital broadcast receiver according to claim 6, further comprising: a remainder calculator for calculating a remainder. 8. The cycle detecting means includes: two registers for holding the time at which the detection signal is generated twice, and a subtractor for obtaining a difference between the times held in the two registers. The phase detecting means includes a counting means initialized by the reference signal pulse, and a register for taking in a count value by the counting means when the detection signal is generated, wherein the program number delaying means detects the reference signal pulse. The digital broadcast reception according to claim 1, further comprising: a delay unit that delays by the time of the predicted phase; and a register that captures the changed program number when the delayed reference signal pulse is generated. Machine.