JPH11252543A - Decoding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a decoding circuit with a simplified system design processing a plurality of signals with only one clock without the need for two clocks. SOLUTION: A decoding circuit consists of 1st and 2nd video decoders each receiving a video stream with program clock reference(PCR) to decode information. In this arrangement, the processing circuit is provided with a clock generating circuit 27 in common to the 1st and 2nd video decoders, while PCR detection circuits 14A, 24 detect each PCR included in two video streams and a count by a system time clock STC counter 25 is compared with an output from the PCR detection circuit 24 and a clock frequency of the clock generating circuit 27 is corrected based on the comparison result, the count obtained by counting a clock from the clock generating circuit 27 at the STC counter 15 is corrected by an instruction from the PCR detection circuit 14A and MPEG decoders 12, 22 apply decoding synchronously to the two video streams according to two counter output values based on one clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Industrial applications]

[0002]

2. Description of the Related Art In general, a system for transmitting moving images and sounds, such as a television broadcast, a video conference system, and a video telephone, and a method for recording signals such as moving images and sounds on a magnetic disk, an optical disk, and a magnetic tape. In a system for reproducing a recorded signal, a method of performing high-efficiency encoding to increase transmission efficiency is used to effectively use a transmission path and a recording medium.

[0003] A typical method of this high efficiency coding is MPE.
G (Moving Picture Expert Group) 2. MPE
G2 stands for ISO (International Organization for Stand)
ardization) and IEC (International Electrotechica)
l Commission) Joint Technical Committe (JTC)
This is an encoding standard that has been standardized as ISO / IEC 13818 in e).

[0004] In MPEG2, not only the coding standard, but also a method for multiplexing a video stream such as video and audio is specified by the standard so that the encoded data stream such as video and audio can be used for a wide range of purposes. Have been. This standard is an MPEG2 system (MPEG2
Systems), depending on the usage of the data stream, a transport stream (TS: Transport Stream) intended for application to broadcasting and communication,
Program stream (PS:
Program Stream).

The transport stream has been considered to transmit a plurality of programs in one stream, and is expected to be used in many broadcasting and communication applications in the future.

On the other hand, DSP (Digital Signal Processo)
By using r), it is also possible to perform decoding of a video signal compressed using the MPEG method. The processing power of the hardware in the DSP has been improved,
Since the operation speed of the IC has also been improved, it is possible to decode a plurality of video signals and a plurality of audio signals included in the MPEG stream.

In the digital broadcasting system, the transmission side multiplexes a plurality of image data (TS packets), each of which is encoded by the MPEG method, into one transport stream, and this stream is generated similarly. Each stream is transmitted together with a transport stream of a different frequency to a repeater such as a satellite on a carrier of a different frequency, and a plurality of transport streams transmitted on a carrier of a different frequency are transmitted on the receiving side.
Reception and demodulation are performed by separate demodulation means (including a tuner) for each frequency, one video data is selected from each demodulated transport stream, and the
A plurality of video signals decoded by the EG method are displayed on a screen of a display device such as a cathode ray tube (CRT) on a multi-screen, or a plurality of video signals obtained by the MPEG decoding process are separately separated. Can be displayed on a display device.

FIG. 14 is a block diagram of a conventional MPEG decoding circuit for processing a plurality of video data. Here, a case will be described in which two pieces of video data, one selected from each of two transport streams, are input to the first and second video decoders 10 and 20 as two input bit streams. 2
One input bit stream is provided to input terminals 11 and 21 of the first and second video decoders. The video bit streams supplied to the input terminals 11 and 21 are respectively
Are supplied to the MPEG decoders 12 and 22 in the video decoder of FIG.

The MPEG decoders 12 and 22 are supplied with clock count values from STC counters 15 and 25 (STC is an abbreviation for System Time Clock, which is a reference synchronization signal), and are supplied from synchronization generation circuits 18 and 28. A synchronization signal based on the clock count value is supplied.

In the PCR detection circuits 14 and 24, the input terminals 11 and
From each input bit stream supplied to 21, a PCR (Program Clock Refere
nce: program time reference value). Each of the video decoders 10 and 20 has an independent clock generation circuit 17 and 27, respectively. The PCR is included in each input bit stream at a predetermined cycle (for example, a cycle of 100 ms), and the values of the STC counters 15 and 25 are intentionally determined on the MPEG encoder side by periodically comparing and referring to the PCR. Used to set and calibrate to the specified value.

The clock generated by the clock generation circuit 17 in the first video decoder 10 is counted by the STC counter 15. The comparator (difference circuit) 16 includes a PCR detection circuit.
PCR extracted from the first input bit stream at 14
The value is compared with the count output value of the STC counter 15,
If the difference between the two is large, the value of the PCR
The clock is loaded into the counter 15, and when the difference between the two is small, a frequency shift of the clock is detected from the difference information, and the clock generation circuit 17 corrects the frequency.

The clock generated by the clock generation circuit 27 in the second video decoder 20 is counted by the STC counter 25. In the comparator (difference circuit) 26, a PCR detection circuit
PC extracted from the second input bit and stream at 24
The R value is compared with the count output value of the STC counter 25,
If the difference between the two is large, the value of the PCR
The clock is loaded into the counter 25, and when the difference between the two is small, a frequency shift of the clock is detected from the difference information, and the clock generation circuit 27 corrects the frequency.

Therefore, the clock generation circuits 17 and 27
In order to oscillate at a frequency dependent on two input video bit streams, the above-described MPEG decoding processing system operates on two clocks.

In the above-described MPEG decoding circuit, when performing video signal processing with a DSP, it is possible to process two video data with one DSP if it is a high-speed DSP. Is difficult to process because it operates with one clock. Also, 2
In a circuit system that operates with a clock, it is difficult to design a control system in particular because the entire system does not operate with one clock, and a system that lacks flexibility because the distribution of clocks is fixed for each circuit unit at the time of design. There are disadvantages.

[0015]

As described above, conventionally,
It has been difficult to decode two video data based on different transport streams with one clock.

In view of the above problems, the present invention provides a decoding circuit capable of performing a plurality of decoding processes with one clock without using two or more clocks and simplifying system design. It is intended to provide.

[0017]

SUMMARY OF THE INVENTION The present invention relates to a decoding processing circuit for receiving and decoding a stream obtained by encoding video data sent together with reference time information in accordance with the MPEG system, and comprising: Reference time information detecting means for detecting time information, clock generating means for generating a clock having a frequency not locked to the transmission side clock of the stream, and counting the clock from the clock generating means, the output value of Is corrected by an instruction from the reference time information detection means, synchronization generation means for generating a synchronization signal based on the output value of the counter means, and decoding processing of the stream according to the output value of the counter means And decoding means for performing the decoding.

According to the present invention, when, for example, two video data each having reference time information are decoded by the first and second two video decoders, at least the first video decoder includes With the use of the decoding processing circuit, it is possible to perform the decoding processing by using one clock from the clock generating means in common by the first and second video decoders. This is because while the clock from the clock generation means is used as the clock for the second video decoder, the clock from the clock generation means is counted and used by the counter means of the first video decoder. This is because the value can be used after being corrected by the detection value from the reference time information detecting means in the first video decoder. In other words, it is possible to realize a system capable of asynchronously decoding a plurality of video decoders even with one clock.

[0019]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a decode processing circuit according to a first embodiment of the present invention, and FIG. 2 is a block diagram for realizing basic processing in the decode processing circuit of FIG. Therefore, FIG. 1 shows an embodiment in which decoding processing of a plurality of input video data is realized using the configuration of FIG. 2 as a basic processing circuit. FIG. 3 is a diagram illustrating the operation of FIG. FIG. 4 is a block diagram showing the overall configuration of the digital broadcasting system according to the present invention.

First, the overall configuration of the digital broadcasting system will be described with reference to FIG. In a digital broadcasting system, a plurality of imaging devices 51 to 57
A plurality of image data obtained from
The data is input to the G encoders 61 to 67, and each of the encoders 61 to 67 encodes the data by the MPEG method to generate a transport packet (hereinafter, a TS packet). In FIG.
The MPEG encoders 61 to 67 are divided into three transport groups, and a plurality (three in FIG.
The G encoders 61 to 63 operate with a clock from one clock generator 71. Multiple (two in the figure) MPE
The G encoders 64 and 65 operate with a clock from one clock generator 72. Similarly, multiple (two in the figure)
MPEG encoders 66 and 67 have one clock generator 73
It operates with the clock from. And multiple MPs
A plurality of Ts respectively output from the EG encoders 61 to 63
The S packet is multiplexed by the multiplexing circuit 81 to form one transport stream, and the carrier is modulated by the modulation circuit 91 and transmitted to the satellite 100 from the antenna. Similarly, multiple MPs
The plurality of Ts output from the EG encoders 64 and 65, respectively.
The S packet is multiplexed by the multiplexing circuit 82 to form one transport stream, and the carrier is modulated by the modulation circuit 92 and transmitted to the satellite 100 from the antenna. Similarly, multiple MPs
A plurality of Ts output from the EG encoders 66 and 67, respectively.
The S packet is multiplexed by the multiplexing circuit 83 to form one transport stream, and the carrier is modulated by the modulation circuit 93 and transmitted from the antenna to the satellite 100. In the satellite 100, a plurality of (three) transport streams transmitted from the three transport groups are amplified and retransmitted by separate repeaters (transponders) 101 to 103, respectively. On the receiving side, the carrier waves based on the plurality of transport streams are received by the antenna and supplied to the digital broadcast receiving apparatus 200. Here, it is assumed that the digital broadcast receiving apparatus 200 has a circuit configuration capable of simultaneously receiving two transport streams.

The digital broadcast receiving apparatus 200 receives and demodulates a plurality of transport streams transmitted by carrier waves of different frequencies by separate demodulation circuits (including tuners) 211 and 212 for respective frequencies. The respective transport streams are respectively supplied to two demultiplexing circuits 221 and 222, one video data is selected (separated) from each transport, and each video data is separated into first and second two The video decoders (each including an MPEG decoder) 231 and 232 perform decoding processing in the MPEG system, and the two video signals subjected to the MPEG decoding processing are used as main and sub-signals on the screen of a display device 241 such as a cathode ray tube (CRT). Display on two screens or MPE
The two video signals subjected to the G decoding process can be displayed on separate display devices 241 and 242, respectively.

FIG. 5 shows the data structure of an MPEG2 transport packet. MPEG2 system layer (MP
EG2 System Layer) defines a method of packetizing a plurality of video streams and multiplexing them into one transport stream. Here, packets of each video bit stream multiplexed into one transport stream are transport packets (TS packets for short).
It is called. The TS packet has a 4-byte header portion, and the PID (packet ID) in the TS packet indicates what the packet is. In the decoding of the system layer in the demultiplexing circuits 221 and 222, the PID is extracted and the value is determined to determine what packet it is. If the packet is video data to be decoded, the packet is extracted. Transfer to the video decoders 231 and 232. PC
R is provided in an optional field in an adaptation field of a transport packet that is a video bit stream. The number of video streams that can be multiplexed into one transport stream is determined by, for example, setting the bit rate of the transport stream to 40 Mb / s.
Assuming that the bit rate of the video bit stream is 6 Mb / s, six video signals can be transmitted. Furthermore, when transmitting many video streams, a plurality of transport streams are used. In order to decode a plurality of video streams in different transport streams, a digital broadcast receiving apparatus capable of receiving a plurality of transport streams as described with reference to FIG. 4 is required.

FIG. 1 relates to a first embodiment of the present invention, and includes first and second two video decoders in FIG.
A decoding processing circuit corresponding to 231 and 232 is shown.
In FIG. 1, the basic processing circuit shown in FIG.
The decoding processing of the first and second video decoders can be performed asynchronously by one clock generation circuit.

The decoding processing circuit 1 shown in FIG. 1 is composed of first and second video decoders for inputting and decoding two video bit streams obtained separately from two transport streams. . FIG.
The same functional parts as in FIG. In this embodiment, the clock generation circuit 17 in FIG. 14 is deleted, and only one clock generation circuit 27 is provided.

The first video decoder includes a video bit stream input terminal 11, an MPEG decoder 12 as decoding means, a video signal output terminal 13, a PCR detection circuit 14A as reference time information detection means, a counter, STC counter 15 as means, and a synchronization generation circuit as synchronization generation means
18 and a synchronizing signal output terminal 19.
Of the video bit stream input terminal 21
An MPEG decoder 22 serving as a decoding means, an output terminal 23 for a video signal, and a PCR serving as a reference time information detecting means.
A detection circuit 24 and an STC counter 25 as counter means;
, A comparison circuit (difference circuit) 26, a clock generation circuit 27 as a clock generation means, a synchronization generation circuit 28 as a synchronization generation means, and an output terminal 29 for a synchronization signal.

The two video bit streams are supplied to terminals 11 and 21.
Given to. The PCR, which is the reference time information included in the video bit stream supplied to the terminal 11, is detected by the PCR detection circuit 14A. In addition, PCR which is reference time information contained in the video bit stream given to the terminal 21
Is detected by the PCR detection circuit 24. STC counter 25
Is compared with the PCR value by the comparison circuit 26, and the oscillation frequency of the clock generation circuit 27 is controlled so as to reduce the difference value. The clock generated by the clock generation circuit 27 has the same frequency as the clock on the transmission side of the video bit stream supplied to the terminal 21, but generally, the frequency of the transmission side clock of the video bit stream supplied to the terminal 11 Does not match. Input terminal 11, PCR
Detection circuit 14, STC counter 15, MPEG decoder 12,
Synchronous signal generation circuit 18, output terminal 13, synchronous signal output terminal 19
Constitutes the basic processing circuit described in FIG. MP
The EG decoder 12 performs a decoding process based on the count value of the STC counter 15 (a value indicating the reference time of the video bit stream applied to the terminal 11). Thus, the terminal
Two video signals are output to 13 and 23, and
Synchronization signals synchronized with the video signals output to the terminals 13 and 23 are output to 9 and 29, respectively.

FIG. 2 is a block diagram for realizing the basic processing in the decoding processing circuit of FIG. 1, and FIG. 3 is a diagram for explaining the operation.

The basic processing circuit shown in FIG. 2 corresponds to the first video decoder (11, 12, 13, 14A, 15, 18,
19) and a clock generation circuit 27 of the second video decoder.

In FIG. 2, the PCR calculates a value obtained by counting the transmission clock of 27 MHz by the transmission counter at a predetermined period (PCR arrives at a period of, for example, 100 ms. Therefore, if one vertical period is 16.7 ms, it is almost equal to 16.7 ms). (It will arrive once every 6 vertical periods). The receiving side is provided with a 27 MHz clock generation circuit 27, and generates a 27 MHz clock while referring to the incoming PCR. The STC counter 15 receives the 27 from the clock generation circuit 27.
The clock output of MHz is counted. When the PCR arrives from the terminal 11 together with the video bit stream, the PCR detection circuit 14A compares the PCR with the value of the STC counter 15 and stores the difference data. The PCR detection circuit 14A adds (or subtracts) the difference value and the output from the STC counter 15 at the timing when the vertical synchronization signal V from the synchronization generation circuit 18 is generated, thereby obtaining the value to be taken by the STC counter 15 ( Hereinafter, the correction value is obtained, and the correction value is loaded into the STC counter 15. In FIG.
The signal line returning to the detection circuit 14A is for supplying the vertical synchronization signal VD from the synchronization generation circuit 18 to the PCR detection circuit 14A, and after the timing of the vertical synchronization signal V is given, the PCR detection circuit 14A Loads the STC counter 15 with a correction value based on the difference value calculated when the PCR arrives. The loading of the correction value is performed every time the PCR value arrives and after the timing of generating the vertical synchronizing signal V, and the value of the STC counter 15 is calibrated (corrected) each time by this loading. Therefore, ST
After the correction value is loaded into the C counter 15, if the frequency of the clock generated by the clock generation circuit 27 and the frequency of the clock on the transmission side completely match, the incoming PCR value and the STC counter 15 Will always match.
However, actually, since the clock frequency of the clock generation circuit 27 does not always match the clock frequency of the transmission side, a difference occurs between the next incoming PCR value and the STC counter 15 value.

FIG. 3 shows the time t on the horizontal axis and the STC on the vertical axis.
It shows the transition of the value of the STC counter 15 over time by taking the value of the counter 15. It is assumed that the value of the STC counter 15 is 0 at time 0. The count value of the STC counter 15 increases with time. Synchronous generation circuit
18 generates a horizontal synchronizing signal H and a vertical synchronizing signal V according to the value of the STC counter 15, and outputs them to a terminal 19. In FIG.
The timing at which the horizontal synchronization signal H is output and the timing at which the vertical synchronization signal V is generated are conceptually represented by H and V. The synchronization generation circuit 18 is actually 5 in the case of the NTSC system.
Although the vertical synchronization signal V is generated at 25H (about 16.7 ms), FIG. 3 shows the vertical synchronization signal V generated at 4H for simplification. Actually, every time the value of the STC counter 15 that counts 27 MHz increases by 858 × 2 = 1716, the synchronization signal H of 15.734 KHz is generated. Also, every time the signal rises by 858 × 525 = 450450, the vertical synchronizing signal V of 59.94 Hz is output. In FIG.
There is a discontinuity in the rise of the value of the STC counter 15 after the second V position by the synchronization generation circuit 18. This is because a difference value calculated based on this PCR is received when the PCR arrives, and the difference value is added to the value of the STC counter 15 at the point of time Vp after the position of V to obtain a correction value b as P.
This shows that the CR detection circuit 14A has loaded the STC counter 15. In this case, the value of the STC counter 15 is higher than the value of the incoming PCR. This means that the clock frequency of the synchronization generation circuit 27 of the receiver is slightly higher than the clock on the transmission side. Since the load timing Vp of the correction value b to the STC counter 15 is after the timing of the vertical synchronizing signal V from the synchronizing circuit 18, the timing at which the next horizontal synchronizing signal H is generated is slightly shifted. . That is, the time interval between the timing of the vertical synchronizing signal V and the timing of the next horizontal synchronizing signal H sandwiching the loading timing Vp is longer than the normal horizontal cycle (1H). However, the subsequent horizontal synchronizing signal H is output at a constant interval (horizontal cycle 1H). Thus, the clock signal frequency of the clock generation circuit 27 is not locked to the transmitting stream input to the terminal 11, but the average frequency of the horizontal synchronizing signal H and the vertical synchronizing signal V reproduced as the receiving device is equal to the transmission frequency. It can be completely matched with the horizontal and vertical average frequency of the side. As a result, the moving image can be reproduced without any frame loss. The period between the timing of the vertical synchronizing signal V and the timing of the next horizontal synchronizing signal H sandwiching the load timing Vp is a period corresponding to the upper or lower part of the screen (that is, a period corresponding to overscan). Therefore, even if the horizontal scanning period of this period becomes slightly longer, it does not affect the display screen actually viewed by the user.

FIG. 6 is a block diagram showing a decoding processing circuit according to the second embodiment of the present invention. In the embodiment of FIG. 1, the STC counter is provided for each of the first and second video decoders corresponding to two input video bit streams. In the second embodiment, the STC counter is provided. The configuration is such that there is one STC counter.

In FIG. 6, a first video decoder includes an input terminal 11 for a video bit stream, an MPEG decoder 12 as decoding means, an output terminal 13 for video signals, and a PCR detection circuit as reference time information detecting means. 14, a synchronization generation circuit 18 as a synchronization generation means, and an output terminal 19 for a synchronization signal.
, Comparison circuit (difference circuit) 31, STC difference value register
32, and an adder 33. The second video decoder includes an input terminal 21 for a video bit stream, an MPEG decoder 22 as decoding means, and an output terminal for a video signal.
23 and a PCR detection circuit 24 serving as a reference time information detecting means.
, A STC counter 25 as a counter means, a comparison circuit (difference circuit) 26, a clock generation circuit 27 as a clock generation means, a synchronization generation circuit 28 as a synchronization generation means, and an output terminal 29 for a synchronization signal. It is configured. Note that the comparison circuit (difference circuit) 31 and S
The TC difference value register 32 and the adder 33 constitute reference time generating means for supplying a reference time to the MPEG decoder 12.

The PCR which is the reference time information is extracted from the video bit stream applied to the terminal 21 by the PCR detection circuit 24. The STC counter 25 counts the clock generated by the clock generation circuit 27. The output value of the STC counter 25 and the value of the PCR arriving at the terminal 21 (PCR detection circuit
24 is compared with a comparison circuit (difference circuit) 26 and the frequency of the clock generated by the clock generation circuit 27 is controlled based on the comparison result. The frequency of the clock generated by the clock generation circuit 27 matches the clock frequency on the transmission side of the video bit stream supplied to the terminal 21. The PCR is removed from the video bit stream supplied to the terminal 11 by the PCR detection circuit 14, and the PCR is performed.
The difference between the value and the output value of the STC counter 25 is obtained by a comparison circuit (difference circuit) 31 and stored in an STC difference value register 32. An output value from the STC counter 25 and an output value from the STC difference value register 32 are added by an adder 33 to obtain a value (count value) indicating a reference time of the video bit stream applied to the terminal 11. The MPEG decoder 12 performs a decoding process based on this value, and the synchronization generation circuit 18 generates a synchronization signal synchronized with the video signal output to the terminal 13.

In FIG. 6, the STC counter 25 outputs a value (count value) indicating the reference time of the video bit stream input to the terminal 21. The reference time required for decoding the terminal 11 is obtained by adding the difference value from the STC difference value register 32 to the count value of the STC counter 25. However, if the reference time information (PCR) of the video bit stream supplied to the terminal 21 changes, the value of the STC counter 25 changes, and the STC counter 25 outputs
The value obtained by adding the difference value from the difference value register 32 by the adder 33 indicates a reference time required for decoding the video bit stream provided to the terminal 11, and this is the STC counter 25
It changes at the same time as the value of changes. That is, ST
When the value of the C counter 25 changes, the reference time given to the MPEG decoder 12 changes. Therefore, the comparison circuit
At 31, an STC difference value register corresponding to a change value of the STC counter 25 caused by a change in the PCR value of the terminal 21 is provided.
Processing to shift the 32 output contents is required. FIG. 7 shown below
In the embodiment, the value of the STC counter 25 is
An embodiment is shown which is not affected by a change in R value.

FIG. 7 is a block diagram of a decoding circuit according to the third embodiment of the present invention. In FIG. 7, the first
Of the video bit stream input terminal 11
An MPEG decoder 12 as decoding means, an output terminal 13 for video signals, and a PCR as reference time information detecting means.
A detection circuit 14, a synchronization generation circuit 18 as synchronization generation means,
A synchronization signal output terminal 19, a comparison circuit (difference circuit) 31,
The second video decoder includes an STC difference value register 32 and an adder 33. The second video decoder includes an input terminal 21 for a video bit stream, and an MPEG decoder 22 as decoding means.
, A video signal output terminal 23, a PCR detection circuit 24 as reference time information detection means, an STC counter 25 as counter means, a comparison circuit (difference circuit) 26, and a clock generation circuit 27 as clock generation means. A synchronization generation circuit 28 as a synchronization generation means, a synchronization signal output terminal 29, a comparison circuit (difference circuit) 41, an STC difference value register 42, an adder
And 43. In the first video decoder,
Comparison circuit (difference circuit) 31 and STC difference value register 32
And the adder 33 constitute a first reference time generating means. The comparison circuit (difference circuit) 41, the STC difference value register 42, and the adder 43 in the second video decoder are
This constitutes a second reference time generating means.

Also in this configuration, there is one STC counter. The PCR detection circuit 24 extracts the PCR from the video bit stream applied to the terminal 21. The STC counter 25 counts the clock generated by the clock generation circuit 27. A comparison circuit (difference circuit) 41 compares the output value of the STC counter 25 with the value of the PCR arriving at the terminal 21 (detection value of the PCR detection circuit 24), and stores the difference value in the STC difference value register 42. STC is added to the output value of STC counter 25
The result obtained by adding the output value of the difference value register 42 by the adder 43 is supplied to the MPEC decoder 22 as a reference time to decode the video bit stream at the terminal 21. The output value of the adder 43 and the PCR from the PCR detection circuit 24 are compared by a comparison circuit (difference circuit) 26, and the oscillation frequency of the clock generation circuit 27 is controlled based on the comparison result. Thereby, the clock oscillation frequency of the clock generation circuit 27 is synchronized with the clock on the transmission side of the video bit stream supplied to the terminal 21. Here, since the PCR detected by the PCR detection circuit 24 is not loaded into the STC counter 25 as shown in FIG. 6, the value of the STC counter 25 is hardly affected by a change in the PCR value of the terminal 21.

The PCR detection circuit 14 extracts the PCR from the video bit stream applied to the terminal 11. The STC counter 25 counts the clock generated by the clock generation circuit 27. A comparison circuit (difference circuit) 31 compares the output value of the STC counter 25 with the value of the PCR arriving at the terminal 11, and stores the difference value in the STC difference value register 32. ST
The MPEC is used as a reference time based on the result obtained by adding the output value of the STC difference value register 32 to the output value of the C counter 25 by the adder 33.
It is supplied to the decoder 12 to decode the video bit stream at the terminal 11.

Here, if it is desired to synchronize the clock oscillation frequency of the clock generation circuit 27 with the clock on the transmission side of the video bit stream supplied to the terminal 21, the adder is used.
The output value of 33 and the PCR value from the PCR detection circuit 14 are compared by a comparator 26, and based on the comparison result, a clock generation circuit 27
May be controlled.

STC counter in embodiment of FIG.
The value 25 does not suddenly change due to the PCR included in the video bit stream input. Therefore, even when the video bit streams applied to the terminals 11 and 21 are switched, mutual interference does not occur.

FIG. 8 shows a connection to the output of the decode processing circuit shown in the embodiment of FIG. 1, FIG. 6, or FIG.
1 shows a configuration for displaying two images on one screen. Terminals 11 and 21 are supplied with a video bit stream, respectively. The video signal output from terminal 13 is
Write control circuit 65 in accordance with the synchronization signal given from
Is written to the memory 61. The synchronization signal output from the terminal 29 is generally asynchronous with the synchronization signal output from the terminal 19. The video data read from the memory 61 by the read control circuit 62 in accordance with the synchronization signal output from the terminal 29 is synchronized with the video signal obtained from the terminal 23. Further, in this case, processing such as enlargement / reduction can be performed by controlling the read address. The video data read from the memory 61 is supplied to the synthesizing circuit 63, is synthesized with the video signal obtained from the terminal 23, and the synthesized video signal is output to the terminal 64. This signal is supplied to a display device (not shown) (corresponding to reference numeral 241 in FIG. 4) to perform display.

FIG. 9 is a block diagram showing a decoding circuit according to the fourth embodiment of the present invention. In the present embodiment, the synchronization generator 18 shown in FIG. 1 is not used, and the MPEG decoders 12 and 22 use the synchronization signal generated by one synchronization generator 28.

In FIG. 9, a first video decoder includes an input terminal 11 for a video bit stream, an MPEG decoder 12 as decoding means, an output terminal 13 for video signals, and a PCR detection circuit as reference time information detecting means. 14A and an STC counter 15 as a counter means.
The second video decoder has an input terminal 21 for a video bit stream, an MPEG decoder 22 as a decoding means, an output terminal 23 for a video signal, and a P time as a reference time information detecting means.
CR detection circuit 24 and STC counter as counter means
25, a comparison circuit (difference circuit) 26, a clock generation circuit 27 as a clock generation means, a synchronization generation circuit 28 as a synchronization generation means, and an output terminal 29 for a synchronization signal.

The horizontal synchronizing signal H and the vertical synchronizing signal V supplied from the synchronizing circuit 28 are generally asynchronous with the synchronizing signal on the transmitting side of the video bit stream supplied from the terminal 11. Therefore, the synchronization signal of the synchronization generation circuit 28 is also asynchronous with each video frame included in the video bit stream supplied to the terminal 11.

FIG. 10 is a diagram for explaining the operation when the video frame from the terminal 11 is decoded asynchronously with the synchronization signal of the synchronization generation circuit 28. FIG. 10A shows a video frame included in the video bit stream supplied to the terminal 11. The arrow (→) indicates the STC counter 15 of each video frame.
Indicates the decoding state based on the output value of, and the tip of the arrowhead indicates that the decoding of the video frame has been completed.
FIG. 10 (b) shows the synchronization generator 28 to the MPEG decoder 12,
The timing of the vertical synchronizing signal given to 22 is shown. FIG.
0 (c) indicates a video frame to be displayed. The video frame input to the MPEG decoder 12 at the timing of reference numeral 71 and decoded is completed by the timing of reference numeral 72, and is output to the output terminal 13 after waiting for the timing of the vertical synchronization signal of reference numeral 73 to perform the display operation. Start.

Since the video frame at the terminal 11 and the synchronization signal of the synchronization generation circuit 28 are asynchronous, there is a vertical gap between the video frame arriving up to the timing of reference numeral 74 and the video frame arriving at the timing of reference numeral 76. There is a period during which no synchronization signal exists. The video frame arriving and decoding by the timing of the code 74 is decoded without the vertical synchronization signal giving the display timing, so that the next arriving video frame is decoded by the timing of the code 76 without being displayed, and immediately thereafter. The display is made at the timing of the incoming vertical synchronizing signal. As described above, when the frequency of the vertical synchronization signal used for display is lower than the frequency of the video frame of the video bit stream, synchronization can be achieved by dropping the transmitted video frame. Also,
If the frequency of the vertical synchronizing signal used for display is higher than the frequency of the video frame of the video bit stream, the transmitted video frame can be synchronized by displaying the same video frame a plurality of times.

FIG. 11 shows a decoding circuit according to a fifth embodiment of the present invention. In FIG. 11, a first video decoder has an input terminal 11 for a video bit stream.
An MPEG decoder 12 as decoding means, an output terminal 13 for video signals, and a PCR as reference time information detecting means.
The second video decoder comprises a detection circuit 14, a comparison circuit (difference circuit) 31, an STC difference value register 32, and an adder 33.
An MPEG decoder 22 serving as a decoding means, an output terminal 23 for a video signal, and a PCR serving as a reference time information detecting means.
A detection circuit 24 and an STC counter 25 as counter means;
, A comparison circuit (difference circuit) 26, a clock generation circuit 27 as a clock generation means, a synchronization generation circuit 28 as a synchronization generation means, and an output terminal 29 for a synchronization signal.
Comparison circuit (difference circuit) 31 in first video decoding
, STC difference value register 32, and adder 33 constitute reference time generating means.

In the embodiment shown in FIG. 11, two STC counters 15 and 25 are provided in the embodiment shown in FIG. 9. However, similar to the configuration shown in FIG. As shown in FIG. 11, the comparison circuit (difference circuit) 31,
By replacing the STC difference value register 32 and the adder 33, the operation is performed by one STC counter 25.

FIG. 12 is a block diagram showing a decoding circuit according to the sixth embodiment of the present invention. In FIG. 12, a first video decoder includes a video bit stream input terminal 11, an MPEG decoder 12, a video signal output terminal 13, a PCR detection circuit 14, and a comparison circuit (difference circuit) 31.
, An STC difference value register 32, and an adder 33. The second video decoder includes an input terminal 21 for a video bit stream, an MPEG decoder 22, an output terminal 23 for a video signal, Circuit 24 and STC counter 25
, A comparison circuit (difference circuit) 26, and a clock generation circuit 27
, A synchronization generation circuit 28, a synchronization signal output terminal 29, a comparison circuit (difference circuit) 41, an STC difference value register 42, and an adder 43.

The embodiment of FIG. 12 is an embodiment of FIG. 11 in which the number of STC counters is one.
The configuration for solving the problem of the change (update) of the output value of the TC counter 25 is shown. This configuration has the problem of the change (update) of the output value of the STC counter 25 due to the change of the PCR value in the configuration of FIG. 6 described above, and similarly to the configuration of FIG. Can be solved. That is, the PCR detected by the PCR detection circuit 24 as shown in FIG.
Is not loaded, the value of the STC counter 25 is hardly affected by a change in the PCR value of the video bit stream input to the terminal 21.

FIG. 13 is a flow chart of FIG. 9, FIG.
The configuration for connecting to the output of the decoding processing circuit shown in the second embodiment and displaying two images on one screen is shown. Two video bit streams on terminals 11 and 21
And decoded by the MPBG decoder 1.
From the terminal 13, a video signal obtained by decoding the video bit stream given to the terminal 11 is obtained, and the write control circuit 65
Performs writing to the memory 61 based on the synchronization signal obtained from the terminal 29. The synchronization signal obtained at the terminal 29 is a synchronization signal synchronized with the video signal of the video bit stream supplied to the terminal 21. The read control circuit 62 is connected to the terminal from the memory 61
The video data is read according to the synchronization signal obtained from 29. In this case, processing such as enlargement / reduction can be performed by controlling the read address. Synthesis circuit
63 combines the video data read from the memory 61 by the read control circuit 62 with the data obtained from the terminal 23, and outputs a composite video signal to the terminal 64. This signal is supplied to a display device (not shown) (corresponding to reference numeral 241 in FIG. 4) to perform display.

In the embodiment described above, the decoding processing circuit including the first and second two video decoders has been described. However, the decoding processing circuit including n (n ≧ 2, n is an integer) video decoders is described. It can also be applied to processing circuits.

That is, n sent together with the reference time information
(N ≧ 2, n is an integer) In a decoding processing circuit having n decoding means for receiving and decoding n streams in which video data is encoded by the MPEG method, among the n decoding means, At least one is Figure 2
The basic processing circuit (decoding processing circuit) shown in FIG.

Referring to FIGS. 8 and 13, at least one of the n video signals obtained from the n decoding means is stored in the memory based on the synchronization signal of the one video signal. By storing and reading out based on a synchronization signal of at least one of the n video signals, at least two video signals of the n video signals can be synchronized.

Further, in connection with the embodiment of FIG. 1, n (n ≧ 2, n is an integer) sent together with the reference time information
A decoding processing circuit that receives and decodes n streams in which n pieces of video data are encoded by the MPEG system, n reference time information detecting means for detecting reference time information included in the n streams, At most n-1 clock generating means for generating a clock having a frequency not locked to the transmitting clock of at least one of the n streams, and counting the clocks from the clock generating means. The output value of which is corrected by an instruction from the reference time information detecting means, at most n-1 counter means, and counts the clock from the clock generating means. The output of the clock generator is compared with at least one output value of the detector. At least one counter means capable of correcting a clock frequency, n synchronization generation means for generating a synchronization signal based on output values of the n counter means, and output values of the n counter means. And n decoding means for decoding the n streams according to the following.

In connection with the embodiment shown in FIG. 6, n (n ≧ 2, n is an integer) video data sent together with the reference time information are encoded by the MPEG system, and the n streams are received. A decoding processing circuit for detecting the reference time information included in the n streams, and locking to a transmission clock of at least one of the n streams. At most n-1 clock generating means for generating a clock of a frequency not performed, and counting clocks from the clock generating means, and outputting the output value to at least one output value of the reference time information detecting means. And at least one counter means capable of correcting the clock frequency of the clock generation means based on the comparison result. At most n-1 reference time generating means for generating a reference time based on the output value of the reference time information detecting means and the output value of the counter means, and the output value of the at least one counter means or at least n synchronization generation means for generating a synchronization signal based on output values of n-1 reference time generation means, and the n streams according to an output value of the reference time generation means or an output value of the counter means And n decoding means for decoding the data.

In connection with the embodiment of FIG. 7, n (n ≧ 2, n is an integer) video data sent together with the reference time information are encoded by the MPEG system, and the n streams are received. A decoding processing circuit for detecting the reference time information contained in the n streams, and transmitting n-1 streams of the n streams. Clock generating means for generating a clock having a frequency not locked to the side clock; counter means for counting clocks from the clock generating means; output values of the n reference time information detecting means and outputs of the counter means N reference time generating means for generating a reference time based on the value;
N synchronization generation means for generating a synchronization signal based on output values of the reference time generation means, and n synchronization generation means for decoding the n streams in accordance with the output values of the n reference time generation means And decoding means.

Further, in relation to the embodiment of FIG.
N (n ≧ 2, n is an integer) video data sent together with the reference time information encoded by the MPEG method
A decoding processing circuit for receiving and decoding the n streams, n reference time information detecting means for detecting reference time information included in the n streams, and at least one stream among the n streams At most n-1 clock generating means for generating a clock having a frequency not locked to the transmitting side clock, and counting the clocks from the clock generating means, the output value of which is the reference time information detecting means. The counter counts at most n-1 counter means and a clock from the clock generation means, and compares the output value with at least one output value of the reference time information detection means. At least one of which is capable of correcting the clock frequency of the clock generation means based on the comparison result Counter means, at least one synchronization generation means for generating a synchronization signal based on the output value of the at least one counter means, and n for decoding the n streams according to the output values of the n counter means Decoding means, wherein the n decoding means thins out a video frame when the output of the counter means and the timing of a synchronization signal from the synchronization generating means for giving a display timing are inconsistent. Or by outputting the same video frame a plurality of times, and outputting n synchronized video signals synchronized with the timing of the synchronization signal.

In connection with the embodiment of FIG. 11, n (n ≧ 2, n is an integer) pieces of video data sent together with the reference time information are encoded by the MPEG system, and the n streams are received. A decoding processing circuit for detecting the reference time information included in the n streams, and locking to a transmission clock of at least one of the n streams. At most n-1 clock generating means for generating a clock of a frequency not performed, and counting clocks from the clock generating means, and outputting the output value to at least one output value of the reference time information detecting means. And at least one counter hand capable of correcting the clock frequency of the clock generation means based on the comparison result. When the most (n-1) reference time generating means for generating a reference time based on the output value of the output value and the counter means of said reference time information detecting means, wherein n
At least one synchronization generating means for generating a synchronization signal based on at least one output value of the counter means; and the n streams according to an output value of the reference time generating means or an output value of the counter means. N decoding means, and at least one of the n decoding means comprises:
When the timing of the output of the reference time generation unit and the synchronization signal from the synchronization generation unit that gives the display timing are inconsistent, the synchronization is performed by thinning out the video frame or outputting the same video frame a plurality of times. And n decoding means for outputting a video signal synchronized with the signal timing.

In connection with the embodiment shown in FIG. 12, n (n ≧ 2, n is an integer) video data sent together with the reference time information are encoded by the MPEG system and the n streams are received. A decoding processing circuit for performing decoding; n reference time information detecting means for detecting reference time information included in the n streams; and transmitting clocks for n-1 streams among the n streams. A clock generating means for generating a clock of a frequency not locked to the counter, a counter means for counting clocks from the clock generating means, an output value of the n reference time information detecting means and an output value of the counter means. N reference time generating means for generating a reference time based on
Synchronization generation means for generating a synchronization signal based on an output value of one of the reference time generation means; and n synchronization processing means for decoding the n streams in accordance with the output values of the n reference time generation means. Decoding means, wherein the n
The n-1 decoding units of the decoding units thin out video frames when the output of the reference time generation unit and the synchronization signal from the synchronization generation unit that gives display timing are inconsistent. Or by outputting the same video frame multiple times,
It may be configured to include n decoding means for outputting a video signal synchronized with the timing of the synchronization signal.

[0060]

As described above, according to the present invention, a plurality of decoding processes can be performed with one clock without using two or more clocks, and a single synchronization signal is required for decoding output. It is possible to simplify the system design and improve the flexibility of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a decode processing circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a basic processing circuit used in FIG. 1;

FIG. 3 is a view for explaining the operation of FIG. 2;

FIG. 4 is a block diagram showing the overall configuration of a digital broadcasting system according to the present invention.

FIG. 5 is a diagram showing a data structure of an MPEG2 transport packet.

FIG. 6 is a block diagram showing a decode processing circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a decode processing circuit according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration for displaying two images on one screen by connecting to the output of the decoding processing circuit of the embodiment of FIG. 1, FIG. 6, or FIG.

FIG. 9 is a block diagram showing a decode processing circuit according to a fourth embodiment of the present invention.

FIG. 10 is a view for explaining the operation of FIG. 9;

FIG. 11 is a block diagram showing a decode processing circuit according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a decode processing circuit according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration for displaying two images on one screen by connecting to the output of the decoding processing circuit of the embodiment of FIG. 9, FIG. 11, or FIG.

FIG. 14 is a block diagram showing a conventional decode processing circuit.

[Explanation of symbols]

11, 21, ... video data input terminals, 12, 22, ... MPE
G decoder, 14, 14A, 24 ... PCR detection circuit, 1
5, 25 ... STC counter, 18, 28 ... synchronization generation circuit, 27 ... clock generation circuit, 31, 42 ... comparison circuit (difference circuit), 32, 42 ... STC difference value register, 3
3, 43 ... Adder.

Claims (11)

[Claims] 1. A decoding processing circuit for receiving and decoding a stream in which video data transmitted together with reference time information is encoded by an MPEG system, wherein the reference time information detects reference time information included in the stream. Detecting means, a clock generating means for generating a clock having a frequency not locked to the transmission side clock of the stream, and counting the clock from the clock generating means, the output value of which is output from the reference time information detecting means. Counter means modified by the instruction of the above, synchronization generating means for generating a synchronization signal based on the output value of the counter means, and decoding means for decoding the stream according to the output value of the counter means. A decode processing circuit characterized by the above-mentioned. 2. The decoding process according to claim 1, wherein the timing at which the output value of said counter means is corrected by an instruction from said reference time information detecting means follows a synchronization signal generated by said synchronization generating means. circuit. 3. n (n) sent together with the reference time information
A decoding processing circuit for receiving and decoding n streams obtained by encoding ≧ 2, n is an integer) video data by the MPEG system, wherein the decoding processing circuit decodes n streams to decode the n streams 3. A decoding processing circuit comprising: means for decoding, wherein at least one of the n decoding means is the decoding processing circuit according to claim 1 or 2. 4. An n obtained from said n decoding means.
At least one video signal among the plurality of video signals is stored in a memory based on a synchronization signal of the one video signal,
Means for synchronizing at least two of the n video signals by reading out based on a synchronization signal of at least one of the n video signals. The decode processing circuit according to claim 3. 5. n (n ≧ n) sent together with reference time information
A decoding processing circuit for receiving and decoding n streams in which MPEG data has been encoded by (2, n is an integer), and detecting n reference time information included in the n streams. Reference time information detecting means, at most n-1 clock generating means for generating a clock having a frequency which is not locked to the transmitting clock of at least one of the n streams, and the clock generating means Counting at most n-1 counter means whose output value is corrected by an instruction from the reference time information detecting means, and counting clocks from the clock generating means. The output value is compared with at least one output value of the reference time information detecting means, and based on the comparison result, At least one counter capable of correcting the clock frequency of the clock generator; n synchronization generators for generating a synchronization signal based on output values of the n counters; and n counters. And n decoding means for decoding the n streams according to output values of the means. 6. n (n) sent together with the reference time information
A decoding processing circuit for receiving and decoding n streams obtained by encoding ≧ 2, n is an integer) video data according to the MPEG system, and detecting reference time information included in the n streams. Reference time information detecting means, at most n-1 clock generating means for generating a clock having a frequency which is not locked to the transmitting clock of at least one of the n streams, Means for counting the clock from the means, comparing the output value with at least one output value of the reference time information detecting means, and correcting the clock frequency of the clock generating means based on the comparison result. A counter time based on an output value of the reference time information detecting means and an output value of the counter means. At least n-1 reference time generating means for generating a synchronization signal, and generating a synchronization signal based on an output value of the at least one counter means or an output value of the at most n-1 reference time generating means. a decoding device comprising: n synchronization generating means; and n decoding means for decoding the n streams in accordance with an output value of the reference time generating means or an output value of the counter means. Processing circuit. 7. n (n) sent together with the reference time information
A decoding processing circuit for receiving and decoding n streams obtained by encoding ≧ 2, n is an integer) video data according to the MPEG system, and detecting reference time information included in the n streams. Reference time information detecting means, clock generating means for generating a clock having a frequency which is not locked to the transmitting clock of n-1 streams of the n streams, and a clock from the clock generating means. Counter means for counting; n reference time generating means for generating a reference time based on an output value of the n reference time information detecting means and an output value of the counter means; N synchronization generating means for generating a synchronization signal based on an output value; and n streams according to output values of the n reference time generating means. Decoding circuit, characterized by comprising an n number of decoding means for decoding, the a. 8. n (n) sent together with the reference time information
A decoding processing circuit for receiving and decoding n streams obtained by encoding ≧ 2, n is an integer) video data according to the MPEG system, and detecting reference time information included in the n streams. Reference time information detecting means, at most n-1 clock generating means for generating a clock having a frequency which is not locked to the transmitting clock of at least one of the n streams, Means for counting clocks from the means, at most n-1 counter means whose output value is corrected by an instruction from the reference time information detecting means, and counting clocks from the clock generating means. And comparing the output value with at least one output value of the reference time information detecting means, and based on the comparison result, At least one counter means capable of correcting the clock frequency of the clock generation means, at least one synchronization generation means for generating a synchronization signal based on an output value of the at least one counter means, N decoding means for decoding the n streams in accordance with the output value of the counter means, wherein the n decoding means outputs an output of the counter means and a synchronizing signal from the synchronization generating means for giving a display timing. When the timing with the signal is inconsistent, n decoding means for outputting a video signal synchronized with the timing of the synchronization signal by thinning out the video frame or outputting the same video frame a plurality of times; A decoding processing circuit, comprising: 9. n (n) sent together with reference time information
A decoding processing circuit for receiving and decoding n streams obtained by encoding ≧ 2, n is an integer) video data according to the MPEG system, and detecting reference time information included in the n streams. Reference time information detecting means, at most n-1 clock generating means for generating a clock having a frequency which is not locked to the transmitting clock of at least one of the n streams, Means for counting the clock from the means, comparing the output value with at least one output value of the reference time information detecting means, and correcting the clock frequency of the clock generating means based on the comparison result. A counter time based on an output value of the reference time information detecting means and an output value of the counter means. At most n-1 reference time generating means for generating a time interval; at least one synchronization generating means for generating a synchronization signal based on an output value of at least one of the n counter means; N decoding means for decoding the n streams in accordance with an output value of the generating means or an output value of the counter means, wherein at least one of the n decoding means has the reference time When the timing of the output of the generating means and the synchronizing signal from the synchronizing means giving the display timing are inconsistent, the timing of the synchronizing signal is reduced by thinning out the video frame or outputting the same video frame a plurality of times. To output a video signal synchronized with
A decoding processing circuit, comprising: decoding means; 10. n sent together with reference time information
A decoding processing circuit that receives and decodes n streams in which (n ≧ 2, n is an integer) encoded video data by the MPEG method, and detects reference time information included in the n streams N reference time information detecting means, a clock generating means for generating a clock having a frequency which is not locked to a transmitting clock of n-1 streams among the n streams, Counter means for counting clocks; n reference time generating means for generating a reference time based on an output value of the n reference time information detecting means and an output value of the counter means; and n reference time generation means A synchronization generating means for generating a synchronization signal based on an output value of one of the means; And n decoding means for decoding the stream, wherein n-1 decoding means of the n decoding means are synchronized with the output of the reference time generating means and the synchronization from the synchronization generating means for giving a display timing. When the timing with the signal is inconsistent, n decoding means for outputting a video signal synchronized with the timing of the synchronization signal by thinning out the video frame or outputting the same video frame a plurality of times; A decoding processing circuit, comprising: 11. The decoding process according to claim 4, wherein at least one of said n decoding means performs a decoding process using a value obtained by adding an offset value to an output value of said counter means as a reference time. , 7, 9 or 10.