JP2001069180A - Transmission rate detecting circuit and digital transmitter receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To specify a digital transmission rate through simple constitution by providing a circuit which generates a detected voltage corresponding to a transmission rate and a comparing circuit which compares the detected voltage with a reference voltage and outputs a switching signal for a clock. SOLUTION: The integrated voltages of two capacitors 6-4a and 6-4b are larger and larger as the transmission rate of a digital signal inputted to an inverter is higher and higher, so when the integrated voltages are supplied to an operational amplifying circuit 605 to generate the difference voltage between both integrated voltages, the detected voltage becomes lower and lower as the transmission rate is higher and higher. For the purpose, a comparing circuit 6-6 compares the detected voltage with the reference voltage and then outputs a signal of logical level '1' when the transmission rate is low and a signal of logical level '0' when high. Through this operation, whether the transmission is high or lower can be specified from digital signals of the two transmission rates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission rate detection circuit and a digital transmission receiver, and more particularly to a transmission rate capable of specifying a digital transmission rate with a simple configuration even if the digital transmission rate is unknown in advance. The present invention relates to a detection circuit and a digital transmission receiver that reproduces a digital signal using a clock that matches the transmission rate specified by the transmission rate detection circuit using the transmission rate detection circuit.

[0002] In Japan, a digital transmission system which was put into practical use in about 1965 is about 1980.
After the year, it became the main transmission method to make up the trunk line instead of the analog transmission method.

[0003] At the same time that the digital transmission system has secured its position as the main transmission system in the trunk line, the optical digital transmission system began to be put into practical use. Has become the dominant transmission system for trunk lines.

[0004] At present, the optical digital transmission system has begun to be introduced to a line such as a subscriber line, which has a small line bundle or is located at the end of a communication line. Almost at the same time, the Internet has rapidly spread, and it has become necessary for the optical digital transmission system to handle the transmission of a large amount of information by the Internet protocol.

In such an optical digital transmission system,
Because the required line capacity increases more than planned when the optical transmission line was first laid, the receivers and repeaters that make up the optical digital transmission system flexibly respond to higher transmission speeds than when they were first installed. It is becoming more and more desirable.

FIG. 31 shows an example of the configuration of an optical digital transmission receiver.

In FIG. 31, 1 is a photodiode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage to the identification circuit 4 for comparison. Is a flip-flop as a reproducing circuit, 7
Is a clock generation circuit.

In the configuration shown in FIG. 31, a received optical signal is converted into an electric signal by a photodiode 1, an output current of the photodiode 1 is converted into a voltage by a preamplifier circuit 2, and The output is amplified to a required amplitude by the main amplifier circuit 3.

The output of the main amplification circuit 3 is supplied to the other input terminal of the discrimination circuit 4 which receives a reference voltage from the power supply 4-1 at one input terminal, and outputs the reference voltage and the output amplitude of the main amplification circuit 3. The signal is identified according to the magnitude, and is converted into a digital signal of logical levels “0” and “1” (this may be described as “identification data”).

The output of the discriminating circuit 4 is supplied to the data terminal of the flip-flop 5 (indicated as "D" in the figure, and similarly in the following figures), and the clock generating circuit 7 Supplied to

The clock generation circuit 7 reproduces a clock from the digital signal output from the discrimination circuit 4, and the clock terminal of the flip-flop 5 is indicated by "C" in the figure. )).

The flip-flop 5 reproduces a digital signal output from the discriminating circuit 4 using the output signal of the clock generating circuit 7 as a clock, and outputs the digital signal as an output terminal (referred to as "Q" in FIG. To be output.)

As a result, the phase of the signal whose amplitude has been identified by the identification circuit 4 can be determined, and a digital signal having the correct phase can be reproduced from the signal obtained by electrically converting the received optical signal.

The clock output from the clock generation circuit 7 is supplied to a subsequent digital processing circuit as a clock matched to the transmission speed.

In the configuration shown in FIG. 31, an example is shown in which an identification circuit 4 receiving a reference voltage at one input terminal is used to identify the output of the main amplifier circuit 3, but the logic level is "0". Alternatively, a limiter amplifier circuit that limits the amplitude at the level of “1” may be used. The same goes for all optical digital transmission receivers, optical digital transmission repeaters, digital transmission receivers, and optical digital transmission repeaters described below.

FIG. 32 shows an example of the configuration of a digital transmission receiver.

In FIG. 32, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, 4-1 is a power supply for supplying a reference voltage for voltage comparison to the identification circuit 4, and 5 is a reproducing circuit. Is a clock generation circuit.

In the configuration shown in FIG. 32, the received electric signal is equalized in waveform deterioration due to the frequency characteristic of the cable by the preamplifier circuit 2 and is amplified with low noise. The output of the preamplifier circuit 2 is 3 to the required amplitude.

The output of the main amplification circuit 3 is supplied to the other input terminal of the discrimination circuit 4 which receives the reference voltage from the power supply 4-1 at one input terminal, and outputs the reference voltage and the output amplitude of the main amplification circuit 3. The digital signal is identified according to the magnitude, and is converted into digital signals of logical levels “0” and “1”.

The output of the discrimination circuit 4 is supplied to the data terminal of the flip-flop 5 and to the clock generation circuit 7.

The clock generation circuit 7 reproduces a clock from the output signal of the identification circuit 4 and supplies the clock to the clock terminal of the flip-flop 5.

The flip-flop 5 uses the output signal of the clock generation circuit 7 as a clock, reproduces the digital signal output by the identification circuit 4, and outputs the digital signal from the output terminal.

As a result, the phase of the signal whose amplitude has been identified by the identification circuit 4 can be determined, and a digital signal having the correct phase can be reproduced from the received signal.

The clock output from the clock generation circuit 7 is supplied to a subsequent digital processing circuit as a clock matched to the transmission speed.

FIG. 33 shows an example of the configuration of an optical digital transmission repeater.

In FIG. 33, 1 is a photo diode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage to the identification circuit 4 for voltage comparison. Reference numeral 5 denotes a flip-flop as a reproduction circuit, 7 denotes a clock generation circuit, and 10 denotes an electro-optical conversion circuit.

In the configuration shown in FIG. 33, the received optical signal is converted into an electric signal by the photodiode 1, and the output current of the photodiode 1 is converted into a voltage by the preamplifier circuit 2 and amplified with low noise. The output of the preamplifier 2 is amplified by the main amplifier 3 to a required amplitude.

The output of the main amplifying circuit 3 is supplied to the other input terminal of the discriminating circuit 4 which receives a reference voltage from the power supply 4-1 at one input terminal. The digital signal is identified according to the magnitude, and is converted into digital signals of logical levels “0” and “1”.

The output of the discrimination circuit 4 is supplied to the data terminal of the flip-flop 5 and to the clock generation circuit 7.

The clock generation circuit 7 extracts a clock component from the output signal of the identification circuit 4 to reproduce a clock, and supplies the clock to the clock terminal of the flip-flop 5.

The flip-flop 5 uses the output signal of the clock generation circuit 7 as a clock, reproduces the digital signal output by the identification circuit 4, and outputs the digital signal from the output terminal.

Thus, the phase of the signal whose amplitude has been identified by the identification circuit 4 can be determined, and a digital signal having the correct phase can be reproduced from the signal obtained by electrically converting the received optical signal.

Then, the signal reproduced by the flip-flop 5 is converted into an optical signal by the electro-optical conversion circuit 10 and transmitted to the optical transmission line.

By the way, in the configuration of FIGS. 31 to 33,
In order to reproduce digital signals corresponding to different transmission speeds, the transmission speed is detected from the digital signal output from the identification circuit 4, a clock matching the transmission speed of the digital signal is selected and supplied to the flip-flop 5. There is a need to.

The clock generation circuit includes a type using a phase-locked loop (a so-called PLL) and a type using a band-pass filter to extract a clock component and amplify the clock component by a timing amplification circuit. However, the former requires a configuration for switching the oscillation frequency of a voltage-controlled oscillation circuit (a so-called VCO) applied to a phase-locked loop or the frequency division ratio of a frequency-divided circuit applied to a phase-locked loop. In the latter case, a configuration for selecting the outputs of a plurality of timing amplifier circuits for amplifying each of the outputs of the plurality of band-pass filters having different pass bands is required.

However, performing the above switching or selection in order to adjust the clock signal to the speed of the digital signal is as follows.
Depending on the waveform or code format of the output signal of the identification circuit for identifying the input signal, there are cases where it can be easily performed and cases where it is difficult.

FIG. 34 shows the spectrum intensities of various signal waveforms.

FIG. 34A shows the spectrum intensity of a sine wave.

In this case, assuming that the period of the sine wave is T, the spectrum intensity is not zero when the frequency is only 1 / T.

FIG. 34B shows the spectrum intensity of the square wave.

In this case, assuming that the period of the square wave is T, the spectrum intensity is a non-zero spectrum at an odd multiple of 1 / T.

Therefore, in the case of a sine wave or a square wave, a band-pass filter whose passing frequency matches the frequency at which the output of the band-pass filter for detecting the clock component is maximized may be selected. .

In practice, the output of the discriminating circuit does not become a sine wave or a square wave, but in the case of an RZ signal, it always has a clock component. Can be.

FIG. 34C shows the spectrum intensity of the NRZ signal.

In this case, since the continuation of the code “0” and the code “1” is allowed, the spectrum does not become a line spectrum, and when the width of the shortest code is T, the frequency is an integral multiple of 1 / T. At which the spectrum intensity becomes zero. Therefore, the transmission speed cannot be specified by the above simple means.

In any case, there is a problem that an adjustment operation is required to detect a clock component.

In the above description, the optical digital transmission receiver and the optical digital transmission repeater are treated as if they were different. However, the difference between the two is only in the presence or absence of the electro-optical conversion circuit, and the optical digital transmission receiver and the optical digital transmission repeater are the same in terms of reproducing the input signal.

[0048] Further, only digital transmission receivers are shown for handling electric signals, and digital transmission repeaters are not shown. This is because the function of reproducing the input signal is the same in the digital transmission receiver and the digital transmission repeater. That is, the digital transmission receiver and the digital transmission repeater are essentially the same.

Furthermore, the optical digital transmission system and the digital transmission system differ only in whether the transmission medium is optical or electric, and there is no change in the function of reproducing the input signal.

Therefore, the technology dealt with in the present specification is conceptually applied to all digital transmission receivers. However, in view of the current situation in which the optical digital transmission system is the main system, the optical digital transmission receiver will be described as an example when a specific example is described below.

[0051]

2. Description of the Related Art FIG. 29 shows an example of the configuration of an optical digital transmission receiver using a conventional transmission rate detection circuit, taking an example of an optical digital transmission receiver using a transmission rate detection circuit capable of supporting two transmission rates. Is shown.

In FIG. 29, 1 is a photodiode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage to the identification circuit 4 for voltage comparison. Numeral 5 denotes a flip-flop as a reproducing circuit, 6b denotes a conventional transmission speed detecting circuit, 7 denotes a first clock generating circuit, 8 denotes a first frequency dividing circuit, and 9 denotes a first selecting circuit.

In the configuration shown in FIG. 29, the received optical signal is converted into an electric signal by the photodiode 1, the output current of the photodiode is converted into a voltage by the preamplifier circuit 2, and is amplified with low noise. The output of the preamplifier circuit 2 is amplified by the main amplifier circuit 3 to a required amplitude.

The output of the main amplifying circuit 3 is supplied to the other input terminal of the discriminating circuit 4 which receives the reference voltage from the power supply 4-1 at one input terminal. The digital signal is identified according to the magnitude, and is converted into a digital signal whose logic level is "0" or "1".

The output of the discriminating circuit 4 is supplied to the data terminal of the flip-flop 5 and also to the first clock generating circuit 7 and the conventional transmission speed detecting circuit 6b.

The first clock generation circuit 7 includes a phase comparison circuit 7-1 and a low-pass filter (indicated as "LPF" in the figure, and similarly in the figures hereinafter).
2 and a voltage-controlled oscillation circuit (indicated as “VCO” in the figure, and similarly in the figures hereinafter) 7-3, and outputs an output to one input terminal of the first selection circuit 9. And the first frequency dividing circuit 8.

The conventional transmission rate detecting circuit 6b is composed of a counter 6-10 and a comparing circuit 6-11. The counter 6-10 outputs the output pulse of the discriminating circuit 4 to a clock terminal ("C" in the figure). The counting is performed in the same manner in the following description, and the counting is performed. The counting value within a certain period of time and a preset threshold value of the counting value are compared.
A comparison is made at -11, and a switching signal is supplied to the first selection circuit 9 according to the magnitude of the count value and the threshold value within a certain time.

The output of the first selection circuit 9 is fed back to the phase comparison circuit 7-1 constituting the first clock generation circuit 7, and is supplied to the clock terminal of the flip-flop 5.

FIG. 30 is a diagram based on the principle of the transmission rate detection circuit having the configuration shown in FIG. 29, on the assumption that one of the two transmission rates is detected.

In FIG. 30, the vertical axis indicates the count value of the counter 6-10 in FIG. 29, and the count value C ₁ indicates a typical count value at a high speed among the assumed transmission speeds. ₂ indicates a typical count value in the case of a low speed among the assumed transmission speeds.

The hatchings above and below the counts C ₁ and C ₂ indicate that the counts fluctuate slightly depending on the nature of the information to be transmitted, ie, voice, data, and images. Therefore, the threshold value of the count value needs to be set in consideration of the fluctuation.

It is to be noted that the count value C depends on the format of the transmission code.
₁ and C ₂ are different values. Therefore, the threshold value given to the comparison circuit 6-11 in FIG. 29 is naturally set to a different value depending on the format of the transmission code.

When the count value is larger than the threshold value, it is easy to output the logic level "0" to the comparison circuit 6-11, so that the first selection circuit 9 includes the voltage control oscillation circuit 7-3. And supplies it as a clock to the flip-flop 5 and feeds it back to the phase comparator 7-1.

Accordingly, the first clock generation circuit 7 controls the oscillation frequency and phase of the voltage controlled oscillation circuit 7-3 according to the phase difference between the output of the identification circuit 4 and the output of the first selection circuit 9, and Control is performed so that a clock synchronized with the digital signal output from the circuit 4 is supplied to the clock terminal of the flip-flop 5.

Thus, the signal digitized by the identification circuit 4 can be correctly reproduced by the flip-flop 5.

Conversely, when the count value is smaller than the threshold value, it is easy to output the logic level "1" to the comparison circuit 6-11. -3 is selected by the first frequency divider 8 to divide the frequency of the output by 1 / n and the flip-flop 5
And a feedback to the phase comparison circuit 7-1.

Accordingly, the first clock generation circuit 7 controls the oscillation frequency and the phase of the voltage control oscillation circuit 7-3 according to the phase difference between the output of the identification circuit 4 and the output of the voltage control oscillation circuit 7-3, Control is performed so that a clock synchronized with the digital signal output from the identification circuit 4 is supplied to the clock terminal of the flip-flop 5.

As a result, the signal digitized by the identification circuit 4 can be correctly reproduced by the flip-flop 5 at different transmission speeds.

That is, according to the configuration of FIG. 29, one of the two assumed transmission speeds is selected by specifying the used transmission speed out of the two assumed transmission speeds, and digitized by the identification circuit 4. The reproduced signal can be reproduced.

The configuration shown in FIG. 29 shows an example in which one transmission rate is specified from two different transmission rates, and a clock signal matching the transmission rate is selected to reproduce a digital signal. It is also possible to specify one transmission speed from the above transmission speeds and select a clock that matches the transmission speed to reproduce the digital signal.

[0071]

In the configuration shown in FIG. 29, the maximum speed is obtained when the output signal of the identification circuit 4 is an alternating signal of "0" and "1" at any transmission speed. The counter 6-10 must be able to follow the alternating signal. That is, the counter 6-10 must be capable of following the highest possible transmission speed.

By the way, a so-called high-speed process needs to be applied as a semiconductor process in order to form an electronic circuit that can follow at a high speed.

In general, a semiconductor integrated circuit that can operate at a higher speed consumes more power.

Further, since the transmission rate is determined based on the count value within a predetermined time, the number of bits of the count value increases as the transmission rate increases.
Since the gate size of the counter 6-10 also increases, the power consumption of the counter 6-10 further increases.

For this reason, in addition to increasing the cost of the semiconductor integrated circuit including the counter 6-10, it is necessary to consider the use of the radiation fins and the like in mounting the configuration of FIG. This leads to an increase in cost and an increase in mounting area and mounting volume.

The present invention has been made in view of the above problems, and has as its first object to provide a transmission rate detection circuit capable of specifying a digital transmission rate with a simple configuration even if the digital transmission rate is unknown in advance. It is another object of the present invention to provide a transmission rate detection circuit that can specify a digital transmission rate and finally select a clock that matches the transmission rate even during operation of the digital transmission system.

A second object of the present invention is to provide a digital transmission receiver using the above-mentioned transmission rate detection circuit and operating with a clock corresponding to the transmission rate specified by the transmission rate detection circuit.

[0078]

SUMMARY OF THE INVENTION A first aspect of the present invention provides a high-voltage power supply for an inverter which is basically constructed by charging / discharging a load capacitor at an output terminal of an inverter constituted by a pair of active elements having complementary characteristics. Utilizing that the voltage obtained by integrating the voltage drop generated in the resistor on the power supply side or the low-voltage power supply side (hereinafter referred to as a detection voltage) has a specific relationship with the transmission speed, the detection voltage is used as the reference voltage. On the other hand, it is a transmission speed detection circuit that generates a clock switching signal depending on whether it is large or small.

According to the first invention, the transmission speed depends on whether the detected voltage generated by charging / discharging of the load capacitor at the output terminal of the inverter paired with active elements having complementary characteristics is larger or smaller than the reference voltage. Since a switching signal indicating a clock that matches the transmission speed can be generated, it is possible to specify the correct transmission speed among the assumed clocks even if the transmission speed is unknown in advance.

Moreover, since the clock switching signal can be generated by a simple circuit, the power consumption of the transmission speed detecting circuit can be reduced.

The second invention determines that the transmission rate is on the high-speed side when the shortest code of the transmission code at the high-speed side of the two transmission rates can be detected from the identification data, If the shortest code of the transmission code at the higher transmission rate of the two transmission rates cannot be detected from the identification data, the transmission code transmitted at the higher transmission rate of the two transmission rates becomes A transmission rate detection circuit that determines that the transmission rate is on the low-speed side by using an allowable continuous time of the same code as a protection time and generates a clock switching signal.

According to the second invention, it is determined whether the two transmission speeds are the high-speed side or the low-speed side based on whether or not the shortest code on the high-speed side can be detected from the identification data. If it is determined that the transmission speed is not on the high-speed side, the same code continuation time allowed for the transmission code transmitted at the high-speed side of the two transmission speeds is used as the protection time to set the transmission speed on the low-speed side. Since it is determined that there is a clock switching signal, a correct transmission speed can be specified from transmission speeds assumed by the clock switching signal.

Further, since the clock switching signal can be generated by a simple circuit, the power consumption of the transmission speed detecting circuit can be reduced.

According to a third aspect of the present invention, the transmission rate is specified from the identification data by using the transmission rate detection circuit of the first or second aspect, and a clock that matches the transmission rate is selected to reproduce the identification data. Is a digital transmission receiver technology.

According to the third aspect, the transmission rate can be specified from the identification data by the transmission rate detecting circuit of the first aspect or the second aspect. Also, it is possible to realize a digital transmission receiver that can reproduce the identification data by selecting a clock that matches the transmission speed.

[0086]

FIG. 1 shows a first embodiment of a transmission rate detecting circuit according to the present invention.

In FIG. 1, 6-1 is a P-channel field-effect transistor, 6-2 is an N-channel field-effect transistor, 6-3 is a resistor, 6-3a is a resistor, 6-3b is a resistor, 6-3c. Is a resistor, 6-3d is a resistor, 6-3e is a resistor, 6-4 is a capacitor, 6-4a is a capacitor,
4b is a capacitor, 6-5 is an operational amplifier circuit, 6-6 is a comparison circuit, and 6-6-1 is a power supply for supplying a reference voltage for voltage comparison to the comparison circuit 6-6.

Here, the P-channel type field effect transistor 6-1 and the N-channel type field effect transistor 6-2 constitute an inverter. A digital signal is supplied to an input terminal of the inverter, and the P-channel field-effect transistor 6-1 and the N-channel field-effect transistor 6-2 are alternately turned on and off by the digital signal.

The capacitor 6-4 is charged when the P-channel field-effect transistor 6-1 is on, and discharged when the N-channel field-effect transistor 6-2 is on. Note that the capacitor 6-4 may be a capacitor physically connected to the output terminal of the inverter, or a so-called parasitic capacitor or a floating capacitor parasitic on the output terminal of the inverter.

The capacitor 6-4a is connected to the capacitor 6-4.
Of the resistor 6-3 due to the current for charging the resistor 6-3.

On the other hand, the capacitor 6-4b integrates a voltage drop generated across the resistor 6-3a due to the current discharged from the capacitor 6-4.

Since the integrated voltage of the two capacitors 6-4a and 6-4b increases as the transmission speed of the digital signal input to the inverter increases, the integrated voltage of the two capacitors 6-4a and 6-4b is reduced. Operational amplifier circuit 6
5 is supplied to a feedback amplifier circuit composed mainly of the reference voltage 5, and the difference voltage between the two integrated voltages (this is called "detection voltage" for the time being. The definition of "detection voltage" will be extended to other than the above. Is generated, the detected voltage becomes lower as the transmission speed is higher.

Therefore, when the detected voltage is supplied to the non-inverting input terminal of the comparing circuit 6-6 and compared with the reference voltage supplied to the inverting input terminal of the comparing circuit 6-6, the transmission speed is low and the When the detection voltage is higher than the reference voltage, the comparison circuit 6-
6 outputs a signal of a logic level "1", and outputs a signal of a logic level "0" when the transmission speed becomes high and the detection voltage becomes lower than the reference voltage.

By the above operation, the configuration of FIG. 1 can specify the level of the transmission rate from the digital signal of the two transmission rates.

Hereinafter, the principle of realizing the above operation by the inverter will be described in more detail.

FIG. 4 shows a P-channel type field effect transistor and static characteristics.

In FIG. 4A showing a P-channel field effect transistor, 101 is a P-channel field effect transistor, and 102 is a resistor.

Then, the source terminal of the P-channel type field effect transistor 101 (shown as "S" in the figure).
In the figures, the same applies hereinafter. ) Is the power supply on the high voltage side (labeled “V _CC ” according to convention in the figure.
The same applies hereinafter. Note that the same V _cc may mean the power supply on the high voltage side and the power supply voltage on the high voltage side. ), And a drain terminal (shown as “D” in the figure. In the figure, the same applies hereinafter) is connected via a resistor 102 to a power supply on the low voltage side (in the figure, according to a customary method). in the. drawing are labeled "V _EE", also titled similarly later. Note that the power supply means of the low voltage side in the same V _EE, the may mean a power supply voltage of the low voltage side.) Shall be connected. The P-channel field effect transistor 1
In general, a substrate (substrate) 01 is used in connection with a source terminal.

One of the power supply V _CC on the high voltage side and the power supply V _EE on the low voltage side may be ground instead of a substantial power supply. Such a power supply may be selected according to the logic level of the digital signal to be handled.

In FIG. 4B showing the static characteristics of the P-channel field-effect transistor, the vertical axis represents the drain current of the P-channel field-effect transistor 101 shown in FIG. 4A ( _{ID in} FIG. 4A). The horizontal axis is P.
This is the gate voltage of the channel type field effect transistor 101.

When the gate voltage is set between the power supply voltage V _CC on the high voltage side and the threshold voltage V _THP of the P-channel field effect transistor, the P-channel field effect transistor is off. When the gate voltage is set to be equal to or lower than the threshold voltage V _THP , the P-channel field effect transistor 101 turns on.

FIG. 5 shows the N-channel field effect transistor and the static characteristics.

In FIG. 5A showing an N-channel type field effect transistor, 103 is an N-channel type field effect transistor, and 104 is a resistor. The source terminal of N-channel field effect transistor 103 is connected to a power supply V _EE on the low voltage side, the drain terminal of which is connected to a power supply V _CC of the high-voltage side through a resistor 104. still,
The substrate (substrate) of the N-channel field-effect transistor 103 is generally used by connecting to a source terminal.

In FIG. 5B showing the static characteristics of the N-channel field-effect transistor, the vertical axis represents the drain current of the N-channel field-effect transistor 103 shown in FIG. 5A (I _{D in} FIG. 5A). The horizontal axis is N.
This is the gate voltage of the channel type field effect transistor 103.

Then, when the gate voltage is the power supply voltage on the constant voltage side,
V_EETo N-channel field-effect transistor threshold
Voltage V_THNN channel if set between
The field effect transistor 103 is off and the gate
The voltage is the threshold voltage V _THNSet above
In this case, the N-channel field effect transistor 103 is turned off.
On.

FIG. 6 shows an inverter using a field effect transistor and static characteristics.

In FIG. 6A showing an inverter, 1
01 is a P-channel field effect transistor, 103 is N
It is a channel type field effect transistor. The gate terminals of the P-channel field-effect transistor 101 and the N-channel field-effect transistor 103 are connected to serve as input terminals, and the drain terminal of the P-channel field-effect transistor 101 is connected to the N-channel field-effect transistor 10.
3 of the drain terminal connection points and an output terminal, P-channel source terminal of the field effect transistor 101 connected to the power supply V _CC of the high voltage side, N-channel type power source terminal low-voltage side of the field effect transistor 103 Connect to _VEE .

The P-channel field effect transistor 1
01 is connected to the source terminal of the P-channel field-effect transistor 101, and the substrate of the N-channel field-effect transistor 103 is connected to the source terminal of the N-channel field-effect transistor 103. The same applies to the case where each field effect transistor is used alone and the case where both field effect transistors constitute an inverter.

In the configuration shown in FIG. 6A, the power supply V _CC on the high voltage side and the P-channel
1 and the source terminal of the N-channel field-effect transistor 103 and the low-voltage side power supply _VEE, no resistor is inserted. However, the static characteristics of the inverter depend on the insertion of the resistor. The same is true.

In FIG. 6B showing the static characteristics of the inverter, the vertical axis on the left is the drain current of each field-effect transistor, and the vertical axis on the right is the voltage at the output terminal of the inverter (in FIG. In the figure,
The same applies hereinafter. ), The horizontal axis is the voltage of the input terminal of the inverter (in the figure, it is simply referred to as “input voltage”).
In the figure, the same applies hereinafter. ).

As described with reference to FIGS. 4 and 5, when the input voltage of the inverter is set between the power supply voltage V _CC on the high voltage side and the threshold voltage V _THP of the P-channel field effect transistor 101, The P-channel field-effect transistor 101 is off, and when the voltage is set to be equal to or lower than the threshold voltage V _THP , the P-channel field-effect transistor 101 is turned on.

On the other hand, when the input voltage of the inverter is on the low voltage side,
Power supply voltage V_EEAnd N-channel field effect transistor 10
Threshold voltage V of 3_THNIf set between
N-channel field effect transistor 103 is off
Yes, the threshold voltage V _THNSet above
In this case, the N-channel field effect transistor 103 is turned off.
On.

Therefore, in the region A shown in FIG. 6B, the N-channel field-effect transistor 103 is turned off, and the P-channel field-effect transistor 101 is turned off.
Is on. Conversely, in the region C, the P-channel field-effect transistor 101 is off and the N-channel field-effect transistor 103 is on. In the intermediate region B, the P-channel field-effect transistor 10
1 and the N-channel field-effect transistor 103 are both on, and an on-current flows between both power supplies through the P-channel field-effect transistor 101 and the N-channel field-effect transistor 103.

FIG. 7 is an equivalent circuit of the inverter.

In FIG. 7A showing an equivalent circuit of the region A, 101-1 is an equivalent switch representing a P-channel field-effect transistor, and 103-1 is an equivalent switch representing an N-channel field-effect transistor.

As described with reference to FIGS. 4 and 5, in this region, the P-channel field effect transistor is almost completely turned on, so that the equivalent switch 101-
1 can be expressed in a short-circuit state, and since the N-channel field-effect transistor is almost completely off, the equivalent switch 103-1 can be expressed in an open state.

Therefore, in the region A, the current flowing from the P-channel field-effect transistor to the N-channel field-effect transistor is zero.

In FIG. 7C showing an equivalent circuit of region C, reference numeral 101-1 denotes an equivalent switch representing a P-channel type field effect transistor, and reference numeral 103-1 denotes an equivalent switch representing an N-channel type field effect transistor.

As described with reference to FIGS. 4 and 5, in this region, the P-channel field effect transistor is almost completely turned off, so that the equivalent switch 101-
1 can be expressed in an open state, and since the N-channel field-effect transistor is almost completely turned on, the equivalent switch 103-1 can be expressed in a short-circuit state.

Therefore, even in the region C, the current flowing from the P-channel field-effect transistor to the N-channel field-effect transistor is zero.

In FIG. 7B showing an equivalent circuit of the region B, 101-1 is an equivalent switch representing a P-channel type field effect transistor, 101-2 is a channel resistance of the P-channel type field effect transistor, and 103-1 is An equivalent switch representing an N-channel type field effect transistor;
3-2 is a channel resistance of the N-channel field effect transistor.

In this region, since both field effect transistors are in the ON state, current can flow from the P channel type field effect transistor to the N channel type field effect transistor. However, in this region, it is necessary to consider the channel resistance of each field effect transistor.

In the region B, the input voltage of the inverter is equal to the threshold voltage V of the N-channel field effect transistor.
_{In the} vicinity of _THN , the channel resistance of the N-channel field-effect transistor is large, so that when the P-channel field-effect transistor tries to flow a large current, the drain-source voltage of the P-channel field-effect transistor decreases. As a result, the P-channel field-effect transistor cannot operate as a current source, so that the current flowing from the P-channel field-effect transistor to the N-channel field-effect transistor is small.

When the input voltage of the inverter is in the vicinity of the threshold voltage V _{THP of the} P-channel field-effect transistor in the region B, the channel resistance of the P-channel field-effect transistor is large. If the effect transistor tries to pass a large current, the voltage between the drain and the source of the N-channel field-effect transistor drops and the N-channel field-effect transistor cannot operate as a current source.
The current flowing from the P-channel field-effect transistor to the N-channel field-effect transistor is small.

On the other hand, when the input voltage of the inverter is near the center of the region B, both field effect transistors are on and the channel resistances of both are not so large, so that the drain currents are suppressed from each other. I can't meet. Accordingly, it can be seen that the current flowing from the P-channel field-effect transistor to the N-channel field-effect transistor near the center of the region B becomes maximum.

The output voltage of the inverter becomes V _CC when the input voltage of the inverter is in the area A, V _EE when the input voltage of the inverter is in the area C, and V _EE when the input voltage of the inverter is in the area B. _The curve connects _CC and _VEE .

That is, the static characteristics of the inverter shown in FIG. 6A are as shown in FIG.

As described above, in the region B, the current flows between the drains of both the field effect transistors, that is, between the high voltage side power supply and the low voltage side power supply, but the inverter is in the region B state. The time is extremely short, and the power consumption by the current can be ignored.

By the way, since an inverter composed of complementary field-effect transistors has a high impedance between stages, a parasitic capacitor is connected to the output terminal of the inverter without connecting a substantial capacitor. When the output voltage of the inverter changes, charging and discharging are performed in the load capacitor. Of course, even when a substantial capacitor is connected, the load capacitor is charged and discharged when the output voltage of the inverter changes.

FIG. 8 is a diagram for explaining the charging / discharging operation of the load capacitor of the inverter.

In FIG. 8, reference numeral 101-1 denotes an equivalent switch representing a P-channel field effect transistor;
1 is an equivalent switch representing an N-channel field effect transistor, and 105 is a load capacitor at the output terminal of the inverter.

When the input voltage of the inverter changes between the power supply voltage V _cc on the high voltage side and the power supply voltage V _EE on the low voltage side, V
_{Since the} P-channel field-effect transistor is turned on and the N-channel field-effect transistor is turned off between _EE and the threshold voltage V _THN of the N-channel field-effect transistor, as shown in FIG. the capacitor is charged to a voltage (V _CC -V _EE).

On the other hand, when the input voltage of the inverter changes between the power supply voltage V _EE on the low voltage side and the power supply voltage V _CC on the high voltage side, the voltage between the threshold voltage V _{THP of the} P-channel type field effect transistor and V _CC . Then, the N-channel field-effect transistor is turned on and the P-channel field-effect transistor is turned off, so that the charge charged in the load capacitor is discharged as shown in FIG.

This charge / discharge is performed every time the logic level of the input signal of the inverter changes. Now, let p be the power consumption of the inverter, f be the repetition frequency of the input signal,
Assuming that the capacitance of the load capacitor is C, the power consumption p of the inverter is expressed by the following well-known equation.

P = (V _CC −V _EE ) ² · C · f (1) The repetition frequency f in the above equation (1) is,
Since it is the speed of the input signal, the transmission speed can be specified by detecting the power consumption of the inverter itself or an amount that is uniquely related to the power consumption of the inverter.

Actually, the configuration shown in FIG. 1 is a configuration for detecting a voltage that has a unique relationship with the power consumption of the inverter and outputting a switching signal for specifying the transmission speed.

That is, the charging current of the capacitor 6-4 in FIG. 1 flows via the P-channel field effect transistor 6-1. Therefore, the voltage drop in the resistor 6-3 due to the charging current flows through the capacitor 6-4a. Is integrated. The higher the transmission speed, the higher the integrated voltage.

Therefore, as shown in FIG. 2A, the source voltage V _A of the P-channel field effect transistor 6-1 (this is referred to as an integral voltage) becomes high when the transmission speed is zero. At the power supply voltage V _cc on the voltage side, the lower the transmission speed, the lower the voltage, and the slope of the decrease is proportional to the transmission speed.

Similarly, since the discharge current of capacitor 6-4 in FIG. 1 flows through N-channel field effect transistor 6-2, a voltage drop in resistor 6-3a due to the discharge current is caused in capacitor 6-4b. Is integrated. And
The higher the transmission speed, the higher the integrated voltage.

Therefore, as shown in FIG. 2A, the voltage V _{B at} the source of the N-channel field effect transistor 6-2a (also referred to as an integral voltage) is low when the transmission speed is zero. At the power supply voltage _VEE on the voltage side, the higher the transmission speed, the higher the voltage, and the rising slope is proportional to the transmission speed.

The operational amplifier circuit 6-5 and the resistor 6-3b shown in FIG.
Or because it generates a detection voltage difference is a voltage of the two integrated voltage V _A and V _B by configured feedback amplifier by 6-3E, the difference between the detection voltages of both of the power supply voltage when the transmission speed is zero ( (V _CC -V _EE ), the higher the transmission rate, the lower the voltage, and the slope of the decrease is proportional to the transmission rate.

Therefore, in order to specify which of the two transmission speeds the input signal has, it is sufficient to determine whether the detected voltage is higher or lower than a predetermined reference voltage. When the detected voltage is supplied to the non-inverting input terminal of the comparing circuit 6-6 and the reference voltage is supplied to the inverting input terminal of the comparing circuit, as shown in FIG. From 6-6, when the detected voltage is higher than the reference voltage, that is, when the transmission speed is lower than the reference speed, a signal of logic level "1" is output. When the detected voltage is lower than the reference voltage, that is, when the transmission speed is lower. Is higher than the reference speed, a signal of logic level "0" is output, so that the transmission speed can be specified by the configuration of FIG.

FIG. 3 is a diagram showing the relationship between the fluctuation of the integrated voltage and the time constant.

In order to transmit significant information, the pulse width of the transmitted signal naturally changes. That is, when the digital signal input to the transmission rate detection circuit is viewed microscopically, FIG.
As shown in (a), the speed of the digital signal changes every moment.

The higher the speed of the digital signal, the higher the voltage integrated in the capacitors 6-4a and 6-4b.

Therefore, the resistor 6-3 and the capacitor 6-4a
Time constant determined by the resistor 6-3a and the capacitor 6
When the time constant determined by -4b is small, FIG.
As shown in (b), capacitors 6-4a and 6-4b in a time zone where the repetition frequency of the digital signal pulse is low.
Is reduced. That is, fluctuations indicated by two arrows occur in the integrated voltage.

Here, the resistor 6-3 and the capacitor 6-4a
Time constant determined by the resistor 6-3a and the capacitor 6
If the time constant determined by -4b is set to be larger than the longest pulse width in the time zone where the pulse repetition frequency of the digital signal is low, the fluctuation can be suppressed as shown in FIG.

Therefore, the resistor 6-3 and the capacitor 6-4a
Time constant determined by the resistor 6-3a and the capacitor 6
-4b is set to be larger than the longest pulse width of the digital signal to prevent the integrated voltage and the detection voltage from changing due to a microscopic change in the digital signal, and to specify the transmission speed. Accuracy can be increased.

Here, in the digital transmission system, since the number of continuations of the logic level “0” and the logic level “1” is defined by a code rule, as described above, the resistor 6-3 and the capacitor 6-4a are used. Determined time constant and resistance 6
It is easy to set the time constant determined by 3a and the capacitor 6-4b to be larger than the longest pulse width of the digital signal.

Although the field effect transistors shown in FIG. 1 and thereafter are shown assuming the most usual insulated gate field effect transistors, they may be junction gate type field effect transistors. Furthermore, a so-called high electron mobility transistor (HEMT: High Electron Mo
field effect transistor having a structure such as bility transistor.

Furthermore, the elements constituting the inverter are not limited to the field effect transistors, but may be junction type transistors.

FIG. 9 shows a transmission speed detection circuit according to a second embodiment of the present invention.

In FIG. 9, 6-7 is a PNP transistor, 6-8 is an NPN transistor, 6-3 is a resistor,
6-3a is a resistor, 6-3b is a resistor, 6-3c is a resistor, 6
-3d is a resistor, 6-3e is a resistor, 6-4 is a capacitor,
6-4a is a capacitor, 6-4b is a capacitor, 6-5
Denotes an operational amplifier circuit, and 6-6 denotes a comparison circuit.

Here, the PNP transistors 6-7 and N
The PN transistor 6-8 forms an inverter, and the PNP transistor 6-7 and the NPN transistor 6-8 alternately turn on and off in response to a digital signal input to the inverter.

The capacitor 6-4 is charged when the PNP transistor 6-7 is on and the NPN transistor 6-8 is off, and when the NPN transistor 6-8 is on, the PN
Discharged when P transistor 6-7 is off.

The capacitor 6-4a is connected to the capacitor 6-4.
Of the resistor 6-3 due to the charging current of the above.

On the other hand, capacitor 6-4b integrates a voltage drop generated across resistor 6-3a due to the discharge current of capacitor 6-4.

Since the integrated voltages of the capacitors 6-4a and 6-4b increase as the transmission speed increases, both integrated voltages are supplied to the feedback amplifier circuit mainly composed of the operational amplifier circuit 6-5. Then, when a detection voltage which is a difference voltage between the two integrated voltages is generated, the detection voltage becomes lower as the transmission speed is higher.

Therefore, when the detected voltage is supplied to the non-inverting input terminal of the comparing circuit 6-6 and compared with the reference voltage supplied to the inverting input terminal of the comparing circuit 6-6, the transmission speed is low and When the detection voltage is higher than the reference voltage, the comparison circuit 6-
6 outputs a signal of a logic level "1", and outputs a signal of a logic level "0" when the transmission speed becomes high and the detection voltage becomes lower than the reference voltage.

By the above operation, the transmission speed can be specified even with the configuration of FIG.

That is, regardless of the type of the active element constituting the inverter, a circuit for integrating the voltage drop due to the charging / discharging current of the load capacitor at the output terminal of the inverter is connected between the active element constituting the inverter and the power supply. For example, a transmission speed detection circuit can be configured.

Further, the position at which the circuit for integrating the voltage drop due to the charging / discharging current of the load capacitor at the output terminal of the inverter is not limited to the position between the elements constituting the inverter and the power supply. , P-channel field effect transistor 6-1 and N-channel field effect transistor 6-2. However, in this case, a detection voltage is generated by extracting a voltage between the drain of the P-channel field-effect transistor 6-1 and the drain of the N-channel field-effect transistor 6-2.

In any case, in the transmission speed detecting circuit of the present invention, a circuit for integrating a voltage drop caused by a charging current and a discharging current of a capacitor at an output terminal of the inverter is inserted in series with an active element constituting the inverter. Then, it can be said that the circuit determines a level of the transmission speed by generating a detection voltage for specifying the transmission speed from a voltage obtained by integrating a voltage drop caused by a charging current and a discharging current of the load capacitor at the output terminal of the inverter.

FIG. 10 shows a third embodiment of the transmission rate detecting circuit of the present invention.

In FIG. 10, 6-1 is a P-channel field-effect transistor, 6-2 is an N-channel field-effect transistor, and a P-channel field-effect transistor 6--6.
1 and an N-channel field effect transistor 6-2 constitute an inverter.

6-9, 6-9a, 6-9b and 6-9c
Is a diode, and a diode bridge is constituted by the diodes 6-9 to 6-9c.

6-3f is a resistor and 6-4c is a capacitor.

Reference numerals 6-5a and 6-5b denote operational amplifier circuits.
Here, a voltage follower is configured.

6-5c is an operational amplifier circuit, 6-3g, 6-
3h, 6-3j and 6-3k are resistors, 6-4d is a capacitor, and the operational amplifier circuit 6-5c and subsequent capacitors 6-4d
A circuit that integrates while amplifying the difference between the two input voltages by using the components described above (referred to as an amplification / integration circuit for convenience).

Reference numeral 6-6 denotes a comparison circuit, and reference numeral 6-6-1 denotes a power supply for supplying a reference voltage for voltage comparison to the comparison circuit 6-6.

A first terminal of the diode bridge is connected to an output terminal of the inverter, and a capacitor 6-4 is connected to a terminal diagonal to the first terminal of the diode bridge.
and a resistor 6-3f between the remaining terminals of the diode bridge.

Then, the voltage between both ends of the resistor 6-3f is taken out by the voltage follower by the operational amplifier circuit 6-5a and the voltage follower by the operational amplifier circuit 6-5b, and the difference between the output voltages of the two voltage followers is computed. The signal is amplified and integrated by the amplifying / integrating circuit mainly composed of the amplifying circuit 6-5c.

Finally, the output of the amplification / integration circuit (this is referred to as a detection voltage) and a signal of a logic level corresponding to the magnitude of the reference voltage are obtained as switching signals from the comparison circuit 6-6.

The P-channel field effect transistor 6-1 and the N-channel field effect transistor 6-2 are repeatedly turned on and off by the digital signal input to the inverter, and the P-channel field effect transistor 6-1 is turned on. When the N-channel field-effect transistor 6-2 is off, the capacitor 6-4c is charged via the diode 6-9a, the resistor 6-3f and the diode 6-9b, and the N-channel field-effect transistor 6-2 is turned on. When the P-channel field effect transistor 6-1 is off, the electric charge charged in the capacitor 6-4c via the diode 6-9c, the resistor 6-3f and the diode 6-9 is discharged.

That is, the charge current and the discharge current flow in the resistor 6-3f in the same direction, and the voltage drop due to the charge current and the voltage drop due to the discharge current occur in the same direction.

The voltage at both ends of the resistor 6-3f is taken out by the voltage follower by the operational amplifier circuits 6-5a and 6-5b and supplied to the amplifier / integrator circuit. A detection voltage obtained by integrating the voltage drop occurring at -3f is output.

FIG. 11 is a diagram for explaining the operation of the configuration of FIG.

FIG. 11A shows a change in the detected voltage with respect to the transmission speed. If the transmission speed is zero, the charging / discharging of the capacitor 6-4c is not performed, so the detection voltage is zero. The higher the transmission speed, the more frequently the capacitor 6-4c is charged and discharged, so that the resistance 6-3
A voltage drop frequently occurs in c. Since the voltage effect is integrated by the amplification / integration circuit, the higher the transmission speed, the higher the detection voltage.

If the detected voltage is supplied to the inverting input terminal of the comparing circuit 6-6a and a predetermined reference voltage is supplied to the non-inverting input terminal of the comparing circuit 6-6a, the comparing circuit 6-6a has a low transmission speed. The logic level "1" is output while the detection voltage is lower than the reference voltage, and the logic level "0" is output when the transmission speed is high and the detection voltage is higher than the reference voltage.

Therefore, the configuration of FIG. 10 also serves as a transmission rate detection circuit, similarly to the configurations of FIGS.

In order to suppress the fluctuation of the detection voltage with respect to the microscopic change in the speed of the input signal, the integration time constant of the amplification / integration circuit may be sufficiently increased. In this case, since the integration time constant is determined by the mirror capacitance obtained by multiplying the capacitance of the capacitor 6-4d by the voltage amplification factor of the amplification / integration circuit and the resistor 6-3g, the integration time constant of the amplification / integration circuit must be sufficiently large. The configuration shown in FIG. 10 makes it possible to specify the transmission speed almost without being affected by the fluctuation of the detection voltage with respect to the microscopic speed change of the input signal.

FIG. 10 shows the case where an insulated gate field effect transistor is used as an active element constituting an inverter, but the insulated gate field effect transistor, high electron mobility transistor, and Needless to say, a junction transistor can be applied.

Further, the configuration of the transmission rate detecting circuit of the present invention is not limited to the configurations shown in FIGS. 1, 9 and 10.

That is, in the configurations shown in FIGS. 1 and 9, the difference between the integrated voltage generated between the complementary active element forming the inverter and the power supply is amplified and used as the detection voltage. Even if an integrated voltage generated between one active element and the power supply is amplified and used as a detection voltage, a voltage corresponding to the transmission speed can be obtained. 1 and 9
The only reason is that the sensitivity of the detected voltage with respect to the transmission speed can be increased by amplifying the difference between the integrated voltages generated between the complementary active elements constituting the inverter and the power supply to obtain the detected voltage. .

In the configuration shown in FIG. 10, a diode bridge is formed by four diodes, and terminals other than the terminal connected to the output terminal of the inverter of the diode bridge and the terminal connected to the capacitor 6-4c are connected. Is connected to a resistor 6-3f, and the voltage drop generated at both ends of the resistor 6-3f is taken out, amplified and integrated because the current when the inverter charges the capacitor 6-4c and the current discharged from the capacitor 6-4c This is because both of the currents at the time of the operation are taken out to increase the sensitivity of the detection voltage to the transmission speed.

Therefore, if the sensitivity of the detected voltage to the transmission speed can be reduced by half, it is possible to reduce the current when the inverter charges the capacitor 6-4c or when the inverter discharges the capacitor 6-4c. Can be taken out and used as the detection voltage.

In this case as well, there may be a plurality of configurations, but the simplest is to connect a series circuit of one diode and one capacitor having one terminal grounded to the output terminal of the inverter, and reduce the terminal voltage of the capacitor. In this configuration, the operational amplifier circuit is taken out by a feedback amplifier circuit and the output of the feedback amplifier circuit is supplied to a comparison circuit. If the anode of the diode is connected to the output terminal of the inverter, the inverter will take out only the current when charging the capacitor, and if the cathode of the diode is connected to the output terminal of the inverter, Will extract only the current when discharging from the capacitor.

However, whether the inverter takes out a current for charging a capacitor on the output terminal side, whether the configuration of FIG. 1 or FIG. 9 or the configuration of FIG. It should be noted that the relationship between the voltage integrated in the capacitor on the output terminal side of the inverter and the transmission speed is reversed when the current discharged from the capacitor is taken out.

FIG. 12 shows a fourth embodiment of the transmission rate detecting circuit of the present invention.

In FIG. 12, 6-12 is a first edge detection circuit, 6-12a is a second edge detection circuit, and 6-1.
3 is an inverter, 6-14 is the first mono-stable
Multivibrator (abbreviated as “mono / multi” in the figure. In the figure, the same applies hereinafter), 6-1.
4a is a second mono-stable multivibrator,
6-15 is a first flip-flop, 6-15a is a second flip-flop, 6-16 is an OR circuit,
Reference numeral 17 is a set / reset flip-flop.

6-9d is a diode, 6-4e and 6-4f are capacitors, 6-3m and 6-3n are resistors,
6-6a is a first comparison circuit, 6-6b is a second comparison circuit, 6-6a-1 is a power supply for supplying a reference voltage for voltage comparison to the comparison circuit 6-6a, and 6-6b-1 is Comparison circuit 6
-6b is a power supply for supplying a reference voltage for voltage comparison. And a diode 6-9d and a capacitor 6-4e.
6-4f, resistors 6-3m and 6-3n, comparison circuit 6
-6a and 6-6b, power supplies 6-6a-1 and 6-6b-
1 by forming the same reference numerals continuous timekeeping circuit which outputs a pulse when not detect the shortest code in the data transmitted by the transmission speed of the high speed side in ₄ predetermined time T.

The first edge detection circuit 6-12 detects the rising edge of the input digital signal, and the second edge detection circuit 6-12a detects the falling edge of the input digital signal.

The first mono-stable multivibrator 6-14 outputs the duration of the shortest code and the edge detection pulse in the data transmitted at the higher transmission speed by the output of the first edge detector 6-12. , And a pulse having a time shorter than twice the duration of the shortest code in the data transmitted at the higher transmission rate, the second monostable multivibrator 6-14a Second edge detection circuit 6-12
The output of a is longer than the sum of the duration T ₁ of the shortest code and the duration T ₂ of the edge detection pulse in the data transmitted at the high-speed transmission rate, and is the shortest code in the data transmitted at the high-speed transmission rate. Generates a pulse with a time shorter than twice the duration of

The first flip-flop 6-15 is driven by the rising edge of a signal obtained by logically inverting the input digital signal, thereby causing the first mono-stable multivibrator 6 to operate.
−14 output and the second flip-flop 6−
15a is a second mono-stable multivibrator 6-14 according to the rising edge of the input digital signal.
Hold the output of a.

Set / Reset / Flip / Flop 6
-17 is set by the logical sum of the outputs of the first flip-flop 6-15 and the second flip-flop 6-15a, and indicates that the transmission speed has been switched from the low-speed side to the high-speed side.

[0196] Then, while the transmission rate of the high speed side is continued can always detect the shortest code in the data transmitted by the transmission speed of the high speed side within a predetermined time T _4, of identity one code continuity timekeeping Since the circuit cannot output the reset pulse, the set-reset flip-flop 6 is used while the transmission speed on the high-speed side continues.
The logic level of the output of −17 remains at “1”.

[0197] On the other hand, when the transmission rate is switched to the low speed side from the high-speed side, always be impossible to detect the shortest code in the data transmitted by the transmission speed of the high speed side a predetermined time T _4, of identity one code continuity time Since the holding circuit outputs the reset pulse, the logic level of the output of the set / reset flip-flop 6-17 changes to "0", indicating that the transmission speed has been switched to the lower transmission speed.

[0198] Then, while the transmission speed of the low speed side is continued, it is impossible to always detect the shortest code in the data transmitted by the transmission speed of the high speed side to the high speed side of the predetermined time T _4, the Since the same code continuous time holding circuit keeps outputting the reset pulse every predetermined time,
The logic level of the output of the reset flip-flop 6-17 remains at "0".

FIG. 13 is a time chart (part 1) for explaining the operation of the configuration shown in FIG. 12, and shows the operation when the transmission speed is switched to the high speed side.

FIG. 14 is a time chart (part 2) for explaining the operation of the configuration shown in FIG. 12, and shows the operation when the transmission speed is switched to the low speed side.

FIG. 15 is a time chart for explaining the operation of the same code continuous time holding circuit.

Hereinafter, the operation of the configuration of FIG. 12 when the transmission speed is on the high speed side will be described in detail with reference to FIGS. 13 and 15 while also referring to FIG.

FIG. 13A shows a digital signal supplied to the input terminal of the transmission speed detection circuit having the configuration shown in FIG.
Since it is actually data supplied from the identification circuit,
It is labeled "Identification data." In identification data, which is the shortest code portion that is given where time T ₁ with an arrow is transmitted by the transmission speed of the high speed side.

FIG. 13B shows inverted data obtained by logically inverting the identification data by the inverter 6-13 in FIG.

First edge detection circuit 6-12 in FIG.
Detects a rising edge of the identification data and outputs a pulse. This is shown in FIG. Similarly, FIG. 13D shows a signal output by the second edge detection circuit detecting the rising of the inverted data. The duration of the edge detection pulse and T _2.

The first mono-stable multivibrator 6-14 in FIG. 12 includes a first edge detection circuit 6-1.
Transition to the logic level “1” by the output pulse of 2
Transitions to a logic level "0" after time T _3, the duration T
Outputs ₃ pulses. Similarly, the second item in FIG.
Stable multivibrator 6-14a is to transition to a logic level "1" by the output pulse of the second edge detection circuit 6-12A, logic level after a time T ₃ "0"
Transition, and outputs a pulse of duration T _3.

Here, if 2T ₁ > T ₃ ≧ T ₁ + T ₂ is set, the first mono-stable multivibrator 6-14 outputs at the rising edge of the shortest code at the transmission speed on the high-speed side. The rising time of the inverted data is always included in the duration of the pulse, and the rising time of the inverted data is not necessarily included in the duration of the pulse output when the code other than the shortest code at the high-speed transmission rate rises.
This is the same for the second mono-stable multivibrator 6-14a. The pulse output from the second mono-stable multivibrator 6-14a at the rising edge of the shortest code at the transmission speed on the high-speed side. The rising time of the inverted data is always included in the duration, and the rising time of the inverted data is not necessarily included in the duration of the pulse output when the code other than the shortest code rises at the transmission speed on the high-speed side.

Therefore, as shown in FIG. 13 (g), P of the output pulses of the first monostable multivibrator
Only the pulse indicated as ₁ is held in the first flip-flop 6-15 at the rising edge of the inverted data.
(H) as the second of the second flip-flop only pulses, labeled as the inner P ₂ output pulses of the mono-stable multi-vibrator at the rising edge of the identification data 6-
15a.

As a result, the output of the OR circuit 6-16 in FIG. 12 is as shown in FIG.

The set / reset flip-flop 6-17 shown in FIG. 12 is set by the pulse shown in FIG. 13 (L), and transitions to the logic level "1", from the transmission speed on the low speed side to the transmission speed on the high speed side. Switching signal.

Now, the same code continuous time holding circuit of FIG. 12 operates as shown in FIG.

When the input logic level of the same code continuous time holding circuit changes from "1" to "0" as shown in FIG. 15A, the electric charge stored in the capacitor 6-4e in FIG. -3m, the terminal voltage of the capacitor 6-4e decreases in an exponential function.
It drops to the reference voltage V _ref1 of -6A-1, the logic level of the output of the comparison circuit 6-6a in FIG. 12 changes to "1" to "0".

The output of comparison circuit 6-6a is connected to capacitor 6-
Since the signal is supplied to the comparison circuit 6-6b through a differentiating circuit composed of the resistor 4f and the resistor 6-3n, a dip occurs in the input voltage of the comparison circuit 6-6b as shown in FIG. Comparator circuit 6-6B when the dip level is lower than the reference voltage V _ref2 of the power 6-6b-1 outputs such a reset pulse of Figure 15 (e).

The set / reset flip-flop 6-17 shown in FIG. 12 is reset by the pulse shown in FIG. The time T ₄ from when the input logic level of the same code continuous time holding circuit changes to “0” to when the same code continuous time holding circuit outputs a reset pulse.
Is set to the continuous time of the same code allowed in the data transmitted at the higher transmission rate (of course,
Some margin must be taken into account. ).

[0215] Incidentally, while the transmission speed of the high speed side is continued, always shortest code appears to within the continuous time of the same symbols allowed T ₄ in the data transmitted by the transmission speed of the high speed side. Therefore, while the transmission speed on the high-speed side continues, the same code continuous time holding circuit in FIG.
No pulse is output.

That is, as shown in FIG. 13 (N), while the transmission speed on the high-speed side continues, the logic level of the output of the same code continuous time holding circuit of FIG. 12 is fixed to “0”, and It does not reset the reset flip-flop 6-17.

For this reason, as shown in FIG.
The output of the reset flip-flop 6-17 is kept as it is as a signal for selecting a clock that matches the transmission speed on the high-speed side, while transitioning from the logic level "0" to the logic level "1".

On the other hand, the operation of the configuration shown in FIG. 12 when the transmission speed is switched from the high speed side to the low speed side will be described in detail with reference to FIGS.

FIG. 14A shows identification data supplied to the input terminal of the transmission rate detection circuit having the configuration shown in FIG. In identification data, which is the shortest code portion that is given where time T ₁ with an arrow is transmitted by the transmission speed of the high speed side. The shortest code duration after switching to the low speed side, if the transmission speed of the low speed side is 1/2, the 2T _1.

FIG. 14B shows inverted data obtained by logically inverting the identification data by the inverter 6-13 in FIG.

First edge detection circuit 6-12 in FIG.
Detects a rising edge of the identification data and outputs a pulse. This is shown in FIG. Similarly, FIG. 14D shows a signal output by the second edge detection circuit detecting the rising edge of the inverted data. The duration of the edge detection pulse and T _2.

The first mono-stable multivibrator 6-14 in FIG. 12 includes a first edge detection circuit 6-1.
Transition to the logic level “1” by the output pulse of 2
Transitions to a logic level "0" after time T _3, the duration T
Outputs ₃ pulses. Similarly, the second item in FIG.
Stable multivibrator 6-14a is to transition to a logic level "1" by the output pulse of the second edge detection circuit 6-12A, logic level after a time T ₃ "0"
Transition, and outputs a pulse of duration T _3.

If 2T ₁ > T ₃ ≧ T ₁ + T ₂ is set, the first mono-stable multivibrator 6-14 outputs when the shortest code rises at the transmission speed on the high-speed side. The rising time of the inverted data is always included in the duration of the pulse, and the rising time of the inverted data is not necessarily included in the duration of the pulse output when the code other than the shortest code at the high-speed transmission rate rises.
This is the same for the second mono-stable multivibrator 6-14a. The pulse output from the second mono-stable multivibrator 6-14a at the rising edge of the shortest code at the transmission speed on the high-speed side. The rising time of the inverted data is always included in the duration, and the rising time of the inverted data is not necessarily included in the duration of the pulse output when the code other than the shortest code rises at the transmission speed on the high-speed side.

Therefore, as shown in FIG. 14 (g), P of the output pulses of the first monostable multivibrator
Only the pulse indicated as ₁ is held in the first flip-flop 6-15 at the rising edge of the inverted data.
(H) as the second of the second flip-flop only pulses, labeled as the inner P ₂ output pulses of the mono-stable multi-vibrator at the rising edge of the identification data 6-
15a.

As a result, the output of the OR circuit 6-16 in FIG. 12 is as shown in FIG.

The set / reset flip-flop 6-17 shown in FIG. 12 is set by the pulse shown in FIG. 14 (L), and transitions to the logic level "1", so that the transmission speed changes from the low-speed transmission speed to the high-speed transmission speed. Switching signal.

As shown in FIG. 14 (N), while the transmission speed on the high-speed side continues, the logic level of the output of the same code continuous time holding circuit of FIG. 12 is fixed at “0”, and It does not reset the reset flip-flop 6-17.

For this reason, as shown in FIG.
The output of the reset flip-flop 6-17 is kept as it is as a signal for selecting a clock that matches the transmission speed on the high-speed side, while transitioning from the logic level "0" to the logic level "1".

Now, after the logic level of the output of the OR circuit of FIG. 14 (L) transitions to “0”, the continuous time T ₄ of the same code allowed in the data transmitted at the higher transmission speed is calculated. As time elapses, as described above, FIG.
The same sign continuous time holding circuit outputs a reset pulse as shown in FIG. Since the pulse width of the reset pulse is determined by the time constant of the capacitor 6-4f and the resistor 6-3n in FIG. 12, it is completely independent of the transmitted code length.

The reset pulse output from the same code continuous time holding circuit in FIG.
Since it is supplied to the reset terminal of the flip-flop 6-17, the set / reset flip-flop 6-1
7 is reset and transits to the logic level “0”. This is shown on the low speed side in FIG.

The shortest code length on the low speed side and the output pulse width of both monostable multivibrators are 2
Since the relationship of T ₁ > T ₃ ≧ T ₁ + T ₂ is set,
On the low-speed side, the rise time of the identification data or the rise of the inverted data is never included in the duration of the output pulse of both monostable multivibrators.

Therefore, while the transmission speed is on the low speed side, FIG.
The second OR circuit 6-16 does not transition to the logical level "1", and the set / reset flip-flop 6-17 also continuously outputs the signal of the logical level "0".

In summary, the configuration of FIG. 12 outputs a logic level "1" as a transmission speed switching signal when the transmission speed is on the high speed side, and outputs a logical level "1" when the transmission speed is on the low speed side. It can be seen that 0 "is output. This is a relationship in which the logic level is opposite to the configuration of FIG. 1, 9 or 10. However, in FIG. 12, the output of the OR circuit 6-16 is supplied to the reset terminal of the set / reset flip-flop 6-17, and the output of the second comparison circuit 6-6b is supplied to the set / reset flip-flop. If the voltage is supplied to the set terminal 6-17, the logic level can be adjusted to the same level as the configuration of FIG. 1, 9 or 10. Therefore, when describing the embodiment of the optical digital receiver to which the transmission rate detection circuit of the present invention is applied, in consideration of the above, it is assumed that all transmission rate detection circuits output signals of the same logic level. Please note that it will be explained.

By the way, it should be pointed out that according to the transmission speed detection circuit having the configuration of FIG. 12, the delay time of clock switching is extremely short.

That is, when the transmission speed is switched to the high-speed side, as shown in FIG. 13, the logical level of the switching signal is inverted at the moment when the shortest code transmitted at the high-speed side transmission speed can be detected, and the transmission speed is reduced. When switching to the low speed side, FIG.
As shown in the above, after the logical level of the detection signal of the shortest code transmitted at the high-speed transmission rate changes, the switching signal is output at the moment when the continuous time of the same code allowed when transmitting at the high-speed transmission rate has elapsed. Is inverted.

Therefore, especially when the transmission speed is switched to a lower speed, there is no practical error in the transmission code.

On the other hand, when the transmission rate is switched to the high-speed side, the configuration shown in FIG. 12 cannot select a clock matched to the high-speed side until the shortest code transmitted at the high-speed side transmission rate is detected. Code errors can occur. However, if the identification data is delayed by the continuous time T _{4 of the} same code allowed for the transmission speed on the high-speed side, the head of the identification data can be made later than the head of the selected clock, thereby preventing a code error. It is easy to do.

Further, another circuit excluding the set / reset / flip / flop of the configuration shown in FIG. 12 is provided, and one of the circuits detects the shortest code at the time of transmission on the high-speed side.
After the shortest code at the time of transmission on the high-speed side cannot be detected, the pulse for resetting the set / reset / flip-flop is output after the continuous time of the same code allowed on the high-speed side has elapsed, and the other side outputs the pulse at the low speed. The shortest code for transmission on the low-speed side is detected, and after the continuous time of the same code allowed on the low-speed side elapses after the shortest code for transmission on the low-speed side cannot be detected, the set / reset flip / With the configuration as shown in FIG. 16 in which a pulse for setting the flop is output, even when the transmission speed is switched to the high-speed side, no transmission code error occurs practically. In FIG. 16, the circuit shapes of the dashed box showing the detailed internal circuit and the dashed box omitting the inside are the same, and only the pulse width output by the mono-stable multivibrator is different. The circuit of a solid box showing a detailed internal circuit and the circuit of a solid box omitting the inside are the same including constants. Therefore, the description of the circuit configuration and operation of FIG. 16 is omitted.

That is, if the transmission rate detection circuit of the present invention based on the configuration of FIG. 12 is applied, it is possible to prevent a code error at the time of clock switching.

Now, each circuit constituting the transmission rate detection circuit of FIG. 12 will be briefly described.

FIG. 17 shows a configuration example (part 1) of the edge detection circuit.

In FIG. 17A showing the circuit configuration, FIG.
-12-1 is a resistor, 6-12-2 is a capacitor, 6-1
2-3 is an inverter, and 6-12-4 is a logical product circuit.

The operation waveform of the edge detection circuit having the configuration shown in FIG. 17 is shown in FIG.

When a rectangular wave as shown in (1) of FIG. 17 (b) is input, a resistor 6-12-1 and a capacitor 6-12-
2 cuts off the high frequency component of the rectangular wave and outputs an exponential function waveform. Inverter 6-12-3
Outputs a logic level "1" when the exponential function waveform is lower than its own threshold value, and outputs a logic level "0" when the exponential function waveform is higher than its own threshold value. Therefore, the edge detection pulse output from the AND circuit 6-12-4 has both the input and the output of the inverter 6-12-3 at the logic level "1".
At this time, the waveform becomes a pulse.

FIG. 18 shows a configuration example (part 2) of the edge detection circuit.

In FIG. 18A showing the circuit configuration, 6
-12-3 is an inverter, 6-12-4a is a first AND circuit for inverting output, 6-12-4b is a second AND circuit, and 6-12-5 is a delay circuit.

When a rectangular wave as shown in (1) of FIG. 18B is input, the delay circuit 6-12-5 delays the input by its own delay time τ. Inverter 6-12-3 inverts the logic level of the delayed input.

The first AND circuit 6-12-4a outputs a pulse when the logic level of the input and the output of the delay circuit 6-12-5 is inverted, and the second AND circuit 6-12-4a outputs a pulse. −
4b outputs a pulse when the output of the first AND circuit 6-12-4a and the output of the inverter 6-12-3 match in logic level. Therefore, the second AND circuit 6-
An edge detection pulse can be obtained from 12-4b.

If the edge detection circuit shown in FIG. 17 or FIG. 18 is applied, the edge can be detected by the delay of the rising of the input by the delay circuit or the integration circuit, and the clock can be detected like the differentiating circuit to which the flip-flop is applied. Is not required, an edge detection pulse having an arbitrary width can be obtained.

FIG. 19 is a structural example of a mono-stable multivibrator.

In FIG. 19A showing the circuit configuration, FIG.
-14-1 is a flip-flop, 6-14-2 is a resistor, 6-14-3 is a cathode connected to the flip-flop side terminal of a resistor 6-14-2, and a resistor 6-14-
2, a diode having a cathode connected to the terminal opposite to the flip-flop, 6-14-4 a capacitor,
6-14-5 is an inverter.

The operation waveform of the monostable multivibrator in FIG. 19A is as shown in FIG.

The input pulse is a flip-flop 6-14.
When the clock signal -1 is supplied to the clock terminal -1, the data terminal of the flip-flop 6-14-1 is fixed at the logical level "1", so that the output of the flip-flop 6-14-1 becomes the logical level "1". To ". When the output of the flip-flop 6-14-1 transitions to the logic level "1", the terminal voltage of the capacitor 6-14-4 is an exponential function of the time constant determined by the resistor 6-14-2 and the capacitor 6-14-4. Level rises. When the terminal voltage of the capacitor 6-14-4 reaches the threshold value of the inverter 6-14-5, the logic level of the inverter 6-14-5 changes from "1" to "0". This allows flip flop 6-14-
Since 1 is reset, flip-flop 6-14
The logic level of the output of −1 changes to “0”. And
The output of the flip-flop 6-14-1 becomes an edge detection pulse. When the logic level of the output of the flip-flop 6-14-1 changes to "0", the capacitor 6-
The charge charged in 14-4 is changed to a diode 6-14-
3, the terminal voltage of the capacitor 6-14-4 drops to the potential of the logic level "0" and becomes constant, and at the same time, the logic level of the inverter 6-14-5 rises to "1". And become constant.

The structure of the mono-stable multivibrator is not limited to the structure shown in FIG. For example, an external resistor and capacitor may be connected to an integrated circuit dedicated to the monostable multivibrator.

FIG. 20 shows a set / reset / flip /
It is a structural example of a flop.

In FIG. 20, 6-17-1 and 6-1
7-1a is an output inversion OR circuit. The output of the OR circuit 6-17-1 is output from the OR circuit 6-17-1a.
Is supplied to one input terminal of the OR circuit 61-1
a is supplied to one input terminal of the OR circuit 6-17-1, the other input terminal of the OR circuit 6-17-1 becomes a set input terminal, and the OR circuit 6-17-1a
Is the reset input terminal, and the output terminal of the OR circuit 6-17-1a is the set / reset terminal.
Output terminal of flip-flop.

In the set / reset flip-flop having the configuration shown in FIG. 20, if the logical level of the set input terminal is "1" regardless of the logical level of the reset input terminal, the logical level of the output becomes "1". That is, regardless of the logic level of the set input terminal, when the logic level of the reset input terminal is "1", the output logic level becomes "0".

FIG. 21 is a first embodiment of an optical digital transmission receiver using the transmission rate detecting circuit of the present invention.

In FIG. 21, 1 is a photodiode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage for voltage comparison to the identification circuit 4. Reference numeral 5 denotes a flip-flop, 6 denotes a transmission rate detection circuit of the present invention, 7 denotes a first clock generation circuit, 8 denotes a first frequency divider circuit, and 9 denotes a first selection circuit.

The transmission rate detecting circuit of the present invention includes:
Any of the transmission speed detection circuits described above may be applied. However, considering that the logical level of the switching signal output from the transmission rate detection circuit is not the same in all the embodiments of the transmission rate detection circuit, the logic level is uniformly matched to the transmission rate on the high-speed side. It is assumed that the logic level for selecting a clock is "0" and the logic level for selecting a clock that matches the transmission speed on the low-speed side is "1". This means that it is only necessary to add an inverter to the output of the circuit in which the logic level of the switching signal for selecting the high-speed clock is "1" and invert the logic level.

In the configuration shown in FIG. 21, the received optical signal is converted into an electric signal by the photodiode 1, and the output current of the photodiode 1 is converted into a voltage by the preamplifier circuit 2 and amplified with low noise. The output of the preamplifier 2 is amplified by the main amplifier 3 to a required amplitude.

The output of the main amplifying circuit 3 is supplied to the other input terminal of the discriminating circuit 4 which receives a reference voltage at one input terminal, and the logic is determined according to the reference voltage and the magnitude of the output amplitude of the main amplifying circuit 3. It is identified as level “1” or “0”.

The output of the discriminating circuit 4 is supplied to the data terminal of the flip-flop 5 and also to the first clock generating circuit 7 and the transmission speed detecting circuit 6 of the present invention.

The first clock generation circuit 7 comprises a phase comparison circuit 7-1, a low-pass filter 7-2, and a voltage-controlled oscillation circuit 7-3, and outputs an output to a first frequency division circuit. 8 and one input terminal of the first selection circuit 9.

The transmission rate detection circuit 6 of the present invention generates a switching signal corresponding to the transmission rate and supplies it to the selection signal terminal of the first selection circuit 9 as described above.

The output of the first selection circuit 9 is supplied to the phase comparison circuit 7-1 constituting the first clock generation circuit 7 and to the clock terminal of the flip-flop 5.

Since the flip-flop 5 reproduces the digital signal output from the discriminating circuit 4 by the clock received at the clock terminal, the optical digital transmission receiver having the configuration shown in FIG. 21 reproduces the received signal by the clock corresponding to the transmission speed. can do.

FIG. 21 specifies that the transmission speed is one of two assumed transmission speeds. In this case, the first selection circuit 9 may have the configuration shown in FIG. .

In FIG. 23 showing an example of the configuration of the first selection circuit 9, 9-1 and 9-1a denote AND circuits, 9-2 denotes an OR circuit, and 9-3 denotes an inverter.

Then, the first clock which is the output of the voltage controlled oscillation circuit 7-3 shown in FIG. 21 is supplied to one input terminal of the AND circuit 9-1, and the other clock of the AND circuit 9-1 is supplied to the other input terminal. A signal obtained by logically inverting the switching signal output from the transmission speed detection circuit 6 of the present invention shown in FIG. 21 is supplied to the input terminal.

A second clock output from the first frequency divider 8 in FIG. 21 is supplied to one input terminal of the AND circuit 9-1a, and the other input terminal of the AND circuit 9-1a is supplied to the other input terminal. The switching signal is supplied to the input terminal.

Since the logic level of the switching signal is "1" when the transmission speed is low, the second clock output from the first frequency dividing circuit 9 is selected and the flip-flop shown in FIG. Supplied to the flop 5 as a clock On the other hand, when the transmission speed is on the high-speed side, the logic level of the switching signal is "0", so that the first clock which is the output of the voltage-controlled oscillation circuit 7-3 is selected and supplied to the flip-flop 5 as a clock. Supplied.

Therefore, the configuration of FIG. 21 is an optical digital transmission receiver that specifies the level of the transmission rate, selects a clock that matches the transmission rate, and reproduces the received signal.

FIG. 22 shows a second embodiment of the optical digital transmission receiver using the transmission rate detecting circuit of the present invention.

In FIG. 22, 1 is a photodiode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage for voltage comparison to the identification circuit 4. Is a flip-flop, 6 is a transmission rate detecting circuit of the present invention, 7a is a second clock generating circuit, 8 is a first frequency dividing circuit, and 9 is a first selecting circuit.

The transmission speed detecting circuit of the present invention includes:
Any of the transmission speed detection circuits described above may be applied. However, considering that the logical level of the switching signal output from the transmission rate detection circuit is not the same in all the embodiments of the transmission rate detection circuit, the logic level is uniformly matched to the transmission rate on the high-speed side. It is assumed that the logic level for selecting a clock is "0" and the logic level for selecting a clock that matches the transmission speed on the low-speed side is "1".

In the configuration shown in FIG. 22, the received optical signal is converted to an electric signal by the photodiode 1, the output current of the photodiode is converted to a voltage by the preamplifier circuit, and is amplified with low noise. The output of the preamplifier circuit 2 is amplified by the main amplifier circuit 3 to a required amplitude.

The output of the main amplifying circuit 3 is supplied to the other input terminal of the discriminating circuit which receives a reference voltage at one input terminal, and has a logic level according to the reference voltage and the magnitude of the output amplitude of the main amplifying circuit 3. The signal is identified as “1” or “0” and converted into a digital signal.

The output of the discriminating circuit 4 is supplied to the data terminal of the flip-flop 5 and also to the second clock generating circuit 7a and the transmission speed detecting circuit 6 of the present invention.

The second clock generation circuit 7a comprises a band-pass filter 7-4 and a timing amplifier circuit 7-5, and outputs the output of the timing amplifier circuit 7-5 to the first frequency divider circuit 8 and It is supplied to one input terminal of the first selection circuit 9.

The transmission rate detection circuit 6 of the present invention generates a switching signal corresponding to the transmission rate and supplies it to the selection signal terminal of the first selection circuit 9 as described above.

The output of the first selection circuit 9 is supplied to the band-pass filter 7-4 constituting the second clock generation circuit 7a and to the clock terminal of the flip-flop 5.

Since the flip-flop 5 reproduces the digital signal output from the discriminating circuit 4 by the clock received at the clock terminal, the configuration shown in FIG. 22 also allows the optical digital transmission receiver to reproduce the received signal by the clock matched to the transmission speed. can do.

Note that the configuration of FIG. 22 also specifies that the transmission speed is one of the two assumed transmission speeds. In this case, the first selection circuit 9 must have the configuration of FIG. I just need.

Since the configuration shown in FIG. 22 includes a band-pass filter and a timing amplification circuit to generate a clock, it is suitable for a case where the output signal of the identification circuit 4 is a code having a clock component such as an RZ code. .

FIG. 24 shows a third embodiment of the optical digital transmission receiver using the transmission rate detecting circuit of the present invention.

In FIG. 24, 1 is a photodiode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage for voltage comparison to the identification circuit 4. Reference numeral 5 denotes a flip-flop, 6 denotes a first transmission rate detection circuit of the present invention (in the figure, simply referred to as “transmission rate detection circuit of the present invention”), and 6a denotes a second transmission rate detection circuit of the present invention. A speed detecting circuit (in the figure, simply referred to as "transmission speed detecting circuit of the present invention"), 7 is a first clock generating circuit, 8 is a first frequency dividing circuit, and 8a is a second frequency dividing circuit. The circuit 9a is a second selection circuit.

The first transmission rate detection circuit 6 and the second transmission rate detection circuit 6a of the present invention basically include:
Any of the transmission speed detection circuits described above may be applied. However, since one of three assumed transmission speeds is specified by using two transmission speed detection circuits, the first transmission speed detection circuit 6 and the second transmission speed detection circuit 6a are configured to specify one transmission speed. It is preferable to use a transmission speed detection circuit of the same circuit type. When the transmission rate detection circuit having the configuration shown in FIG. 1, 9 or 10 is used, it is desirable to use a transmission rate detection circuit in which the same active element is applied to both transmission rate detection circuits. Also, considering that the logical level of the switching signal output from the transmission rate detection circuit is not the same in all the embodiments of the transmission rate detection circuit, the logic level is uniformly matched to the transmission rate on the high-speed side. It is assumed that the logic level for selecting a clock is "0" and the logic level for selecting a clock that matches the transmission speed on the low-speed side is "1".

In the configuration shown in FIG. 24, the received optical signal is converted into an electric signal by the photodiode 1, and the output current of the photodiode 1 is converted into a voltage by the preamplifier circuit 2 and amplified with low noise. The output of the preamplifier 2 is amplified by the main amplifier 3 to a required amplitude.

The output of the main amplifying circuit 3 is supplied to the other input terminal of the discriminating circuit 4 which receives a reference voltage at one input terminal, and the logic is determined according to the reference voltage and the magnitude of the output amplitude of the main amplifying circuit 3. The signal is identified as level “1” or “0” and is converted into a digital signal.

The output of the discriminating circuit 4 is supplied to the data terminal of the flip-flop 5, and the first clock generating circuit 7, the first transmission rate detecting circuit 6 of the present invention, and the second transmission rate of the present invention It is supplied to the speed detection circuit 6a.

The first clock generation circuit 7 includes a phase comparison circuit 7-1, a low-pass filter 7-2, and a voltage-controlled oscillation circuit 7-3.
3 to a first frequency dividing circuit 8 and a second frequency dividing circuit 8a.
And to the first input terminal of the second selection circuit 9. The frequency dividing ratio n of the first frequency dividing circuit 8 is smaller than the frequency dividing ratio m of the second frequency dividing circuit 8a, and the output frequency of the first frequency dividing circuit 8 is the output frequency of the second frequency dividing circuit 8a. The frequency is higher than the frequency, and the output of the first frequency dividing circuit 8 is the second selecting circuit 9a.
And the output of the second frequency divider 8a is supplied to the third input terminal of the second selector 9a.

As described above, the first transmission rate detection circuit 6 of the present invention and the second transmission rate detection circuit 6a of the present invention generate a switching signal corresponding to the transmission rate to generate the second selection circuit. To supply.

As described above, the configuration shown in FIG. 24 is for reproducing a received signal by specifying one transmission speed from three assumed transmission speeds. The transmission speed at which the switch outputs the switching signal must be different from the transmission speed at which the second transmission speed detection circuit 6a of the present invention outputs the switching signal.

Accordingly, the first transmission rate detection circuit 6 of the present invention and the second transmission rate detection circuit 6a of the present invention are shown in FIG.
When the transmission speed detection circuit having the configuration of FIG. 9 or 10 is used, the first transmission speed detection circuit 6 of the present invention and the second transmission speed detection circuit 6a of the present invention are connected to the output terminal side of the inverter. The capacitors that integrate the voltage drop caused by the charging and discharging of the capacitors to be used may have different capacities.

FIG. 25 is a diagram for explaining the operation of transmission rate detection when the transmission rate detection circuit of FIG. 1 or 9 is applied to the configuration of FIG. The operation is basically the same even if the transmission speed detection circuit of FIG. 10 is used.
Only the case where the transmission rate detection circuit of FIG. 1 or FIG. 9 is applied will be described.

In FIG. 24, the first transmission rate detecting circuit 6 of the present invention and the second transmission rate detecting circuit 6a of the present invention use a capacitor for integrating a voltage drop caused by charging and discharging of the capacitor on the output terminal side of the inverter. They have different capacities. Therefore, in the transmission speed detection circuit in which the capacitance of the capacitor for integrating the voltage drop caused by charging and discharging on the output terminal side of the inverter is set to a small value, the capacitance of the capacitor for integrating the voltage drop caused by charging and discharging is increased. The logic level of the switching signal changes at a transmission speed lower than the transmission speed detection circuit set to the value.

Now, if the switching signal whose logic level changes at a lower transmission rate is the second switching signal, and the switching signal whose logic level changes at the higher transmission rate is the first switching signal, The second switching signal has a relationship as shown in the lower two figures of FIG.

The truth table of the second selection circuit is shown in FIG.
If 6 as setting, the transmission speed when the first and second switching signals are both logic level "1" can be identified as being in the slow speed range S _1, the logic level of the first switching signal there "1" logic level of the second switching signal is "0" the transmission rate can be identified as being in the middle of the speed range S ₂ when the first and second switching signals are both logic level " transmission speed when the 0 "may be identified as being in fast speed range S _3.

FIG. 27 shows a configuration example of the second selection circuit, in which the selection operation is adapted to the truth table of FIG.

In FIG. 27, 9-1, 9-1a, 9-
1b, 9-1c and 9-1d are AND circuits, 9-2 and 9-2a are OR circuits, and 9-3 and 9-3a are inverters.

The first switching signal output from the first transmission rate detecting circuit 6 of the present invention in FIG. 24 is supplied to one input terminal of the AND circuit 9-1b and the inverter 9-3a in FIG. . The second switching signal, which is the output of the second transmission rate detection circuit 6a of the present invention in FIG. 24, is connected to one input terminal of the AND circuit 9-1a of FIG.
3 is supplied.

The voltage controlled oscillation circuit 7- in FIG.
The first clock which is the output of the AND circuit 3 is the AND circuit 9 in FIG.
-1d is supplied to one input terminal of the first frequency dividing circuit 8
The output of the second clock is the AND circuit 9- in FIG.
The third clock supplied to one input terminal of the first and the second output of the second frequency divider 8a is the AND circuit 9-1 of FIG.
a is supplied to one input terminal.

In FIG. 27, inverter 9-
The output of 3a is supplied to one input terminal of AND circuit 9-1c, and the output of inverter 9-3 is the other input terminal of AND circuit 9-1 and the other input terminal of AND circuit 9-1d. It is supplied to the terminal.

Further, in FIG. 27, an AND circuit 9-1 is shown.
And the output of the AND circuit 9-1a are connected to the OR circuit 9-2.
, The output of the OR circuit 9-2 is supplied to the other input terminal of the AND circuit 9-1b, and the output of the AND circuit 9-1d is supplied to the AND circuit 9-1c. The output of the AND circuit 9-1b is supplied to one input terminal of the OR circuit 9-2a, and the output of the AND circuit 9-1c is supplied to the other input terminal. The output is supplied to one input terminal, and the output of the OR circuit 9-2a becomes the output of the second selection circuit.

In the configuration shown in FIG. 27, if the logic levels of the first switching signal and the second switching signal are set to "0" and "1" and the clock selected is tested, the following result is obtained. .

That is, when the logical levels of the first switching signal and the second switching signal are both "1", the logical product circuit 9-1a
Since only the AND circuit 9-1b does not mask the input signal, the slowest third clock is selected and output.

Next, when the logic level of the first switching signal is "1" and the logic level of the second switching signal is "0", only the AND circuits 9-1 and 9-1b are used. Does not mask the input signal, a second clock having an intermediate speed is selected and output.

Further, when the logical levels of the first switching signal and the second switching signal are both "0", the logical product circuit 9-1d
Since only the AND circuit 9-1c does not mask the input signal, the fastest first clock is selected and output.

As a result, it could be verified that the configuration of the second selection circuit in FIG. 27 satisfies the truth table in FIG.

The first transmission rate detection circuit 6 and the second transmission rate detection circuit 6a shown in FIG.
When the transmission speed detection circuit is applied, it is not necessary to set the reference voltages supplied to the comparison circuits 6-6 to be equal to determine the transmission speed.

That is, if the reference voltages for judging the transmission speed in the first and second transmission speed detection circuits are set to different values, the first transmission speed detection circuit of the present invention and the first transmission speed detection circuit of the present invention With the second transmission speed detection circuit, it is possible to output the first switching signal and the second switching signal at different transmission speeds, even if the capacitors that integrate the voltage drop caused by charging and discharging are equalized It is.

In this way, the optical digital transmission receiver having the configuration shown in FIG. 24 can reproduce one of the identification data by specifying one of the three transmission speeds and selecting a clock.

By the way, in the transmission rate detection circuit of FIG. 1, 9 or 10, if a plurality of comparison circuits having different reference voltages are provided in the portion of the comparison circuit for generating the switching signal, a window comparator is constituted. In addition to selecting one of the two transmission rates, it becomes possible to select one transmission rate from three or more transmission rates. When the transmission rate detection circuit having this configuration is applied, in an optical digital transmission receiver that reproduces identification data by selecting a clock that matches one transmission rate among three or more transmission rates, a plurality of diagrams are used. 1, it is not necessary to apply the transmission rate detection circuit of FIG. 9 or FIG.

The above description has been made on the assumption that the transmission rate detection circuit of FIG. 1, 9 or 10 is applied. Of course, the transmission rate detection circuit of FIG. 12 or 16 can be applied. is there.

That is, in FIG. 24, the transmission rate detecting circuit 6 of the present invention detects the shortest code at the highest transmission rate and outputs the switching signal to output the two mono-stable multivibrators of FIG. 12 or FIG. The second transmission rate detection circuit 6a of the present invention detects the shortest code at an intermediate transmission rate and outputs a switching signal to output the switching signal. If the pulse width of the vibrator is set, one of the three transmission speeds of the highest, middle and lowest can be specified. Therefore, the optical digital transmission receiver in FIG. Identification data can be reproduced by selecting a clock that matches one transmission rate. still,
The configuration of the second selection circuit for this may be the configuration shown in FIG.

By the way, if the configuration of FIG. 16 is modified so that the outputs of the two identical code continuous time holding circuits are directly extracted to the outside, a switching signal capable of specifying one of the three transmission speeds can be obtained. Can be.

Therefore, if the transmission rate detection circuit obtained by modifying the configuration of FIG. 16 as described above is applied, one of the three transmission rates is specified, and a clock that matches the transmission rate is selected and identified. In the optical digital transmission receiver for reproducing data, it is not necessary to apply a plurality of transmission rate detection circuits of FIG. 12 or FIG.

With reference to FIG. 24, an optical digital transmission receiver that specifies one of the three transmission speeds, selects a clock that matches the transmission speed, and reproduces the identification data has been described. It is easy to guess that it is possible to specify one transmission rate from four or more transmission rates and select a clock that matches the transmission rate and reproduce the identification data. Is omitted.

FIG. 28 is a fourth embodiment of the optical digital transmission receiver using the transmission rate detecting circuit of the present invention.

In FIG. 28, 1 is a photodiode, 2 is a preamplifier circuit, 3 is a main amplifier circuit, 4 is an identification circuit, and 4-1 is a power supply for supplying a reference voltage for voltage comparison to the identification circuit 4. 5 is a flip-flop, 6 is a transmission rate detection circuit of the present invention, 7 is a first clock generation circuit, 8 is a first frequency divider circuit, 9 is a first selection circuit, 11 is a logical product circuit, 12 Is a register.

In the configuration shown in FIG. 28, the received optical signal is converted to an electric signal by the photodiode 1, and the output current of the photodiode 1 is converted to a voltage by the preamplifier circuit 2 and amplified with low noise. The output of the preamplifier 2 is amplified by the main amplifier 3 to a required amplitude.

The output of the main amplifying circuit 3 is supplied to the other input terminal of the discriminating circuit 4 which receives a reference voltage at one input terminal. The signal is identified as level “1” or “0” and is converted into a digital signal.

The output of the discriminating circuit 4 is supplied to the data terminal of the flip-flop 5 and also to the first clock generating circuit 7 and the transmission speed detecting circuit 6 of the present invention.

The first clock generation circuit 7 includes a phase comparison circuit 7-1, a low-pass filter 7-2, and a voltage-controlled oscillation circuit 7-3.
The three outputs are supplied to one input terminal of the first frequency divider 8 and the first selector 9.

The transmission rate detection circuit 6 of the present invention generates a switching signal corresponding to the transmission rate and supplies it to the first selection circuit 9 as described above.

The output of the first selection circuit 9 is supplied to the phase comparison circuit 7-1 constituting the first clock generation circuit 7 and to the clock terminal of the flip-flop 5.

The flip-flop 5 is connected to the first selection circuit 9
Since the digital signal output from the identification circuit 4 in response to the selected clock matched with the transmission speed is reproduced, FIG.
The optical digital transmission receiver having the above configuration can also reproduce a received signal by using a clock corresponding to the transmission speed.

Here, the feature of the configuration of FIG. 28 is that the selection signal for selecting the clock corresponding to the transmission rate is determined during the training period of the optical digital transmission receiver, and the selection signal is determined during the operation period of the optical digital transmission receiver. The point is that a clock corresponding to the transmission speed is fixedly selected by the selection signal determined during the training period.

That is, during the training period, the training signal (set to the logic level "1" for the time being).
Is supplied to the training signal terminal, and the photodiode 1 is supplied with an optical signal modulated by specific data.

In the transmission rate detection circuit 6 of the present invention, the transmission rate is detected based on the specific data, a switching signal is output, and the switching signal is written to the register 12 via the AND circuit 11.

When the training period ends, the logic level of the training signal changes to "0". That is, in the configuration of FIG. 28, the transmission rate is detected based on specific data during the training period, and the output of the transmission rate detection circuit 6 of the present invention is output by the AND circuit 1 during the operation period
1 will be masked.

In other words, the configuration shown in FIG. 28 has an advantage that it is not necessary to take into account the fluctuation of the detection voltage of the transmission speed detection circuit due to the microscopic change of the data received during the operation period.

Accordingly, any of the transmission rate detection circuits described above may be basically applied as the transmission rate detection circuit of the present invention. However, the transmission rate detection circuit having the configuration shown in FIG. 12 or FIG. There is no need to apply to the 28 configuration. As described above, the transmission rate detection circuit having the configuration shown in FIG. 12 or FIG. 16 can detect the transmission rate at a very high speed and output the switching signal. Because it is not necessary to consider the fluctuation of the detection voltage of the transmission speed detection circuit due to the microscopic change of
This is because it is not necessary to provide a training period and generate a switching signal.

Although FIG. 28 shows a configuration based on the configuration of FIG. 21, it goes without saying that FIG.
24 or a configuration based on the configuration of FIG. 24 can be applied.

FIG. 28 specifies that the transmission speed is one of two assumed transmission speeds. In this case, the configuration of the first selection circuit 9 is shown in FIG. Any configuration may be used.

Here, the configuration of FIG. 28 shows an example in which the AND circuit 11 for receiving the training signal is provided on the output side of the transmission rate detecting circuit 6 of the present invention.
1 may be provided on the input side of the transmission rate detection circuit 6 of the present invention. In this case, during the operation period, the output of the identification circuit 4 is not supplied to the transmission rate detection circuit 6 of the present invention, and the transmission rate detection circuit 6 of the present invention does not operate. It has the advantage that it becomes possible.

[0338] Then, from the assumed three transmission speeds, 1
When specifying two transmission speeds, the configuration shown in FIG.
What is necessary is just to make the composition of 4 a compromise. That is, two transmission rate detection circuits having different settings are provided, and the logical product of the output of the two transmission rate detection circuits and the training signal is shown in FIG.
May be stored in the register 12.

Alternatively, in the optical digital transmission receiver of FIG. 21 or FIG. 22, a window comparator may be applied to a comparison circuit for generating a switching signal in the transmission speed detection circuit of FIG. 1, FIG. 9 or FIG. If the outputs of the two identical code continuous time holding circuits are directly drawn out to the outside, one transmission speed detection circuit specifies one transmission speed from three transmission speeds, and a clock matching the transmission speed. Can be selected to reproduce the identification data.

Further, since it is easy to infer that one transmission rate can be specified from four or more transmission rates, and a clock that matches the transmission rate can be selected to reproduce the identification data, further explanation will be given. Is omitted.

Finally, although the description has been given of an optical digital transmission receiver in this specification, as described earlier, an optical digital transmission repeater, a digital transmission receiver using an electric signal, and a digital transmission relay are described. It is to be noted that the transmission rate detection circuit of the present invention can be applied to a device. The digital transmission receiver, the optical digital transmission repeater, the digital transmission receiver, and the digital transmission repeater are collectively referred to as a digital transmission receiver.

[0342]

According to the first aspect of the present invention, the detection voltage generated by charging / discharging of the load capacitor connected to the output terminal of the inverter paired with active elements having complementary characteristics is larger or smaller than the reference voltage. The switching signal generated according to the above makes it possible to select a clock having a correct transmission speed from the assumed clocks, so that a clock corresponding to the transmission signal can be generated even if the transmission speed is unknown in advance. .

According to the second aspect of the present invention, depending on whether it is possible to detect the shortest time code of the higher transmission speed of the two transmission speeds from the identification data, the higher transmission speed or the lower transmission speed of the two transmission speeds is determined. If it is determined that the transmission speed is not the high speed, the transmission speed is determined to be low with the same code continuation time allowed for the high speed of the two transmission speeds as a protection time. As a result, a clock switching signal is generated, so that a clock having a correct transmission speed can be selected from clocks assumed by the clock switching signal.

According to the third aspect, since the transmission rate of the input signal can be specified by the transmission rate detection circuit, a digital signal capable of reproducing the input signal even if the transmission rate is unknown in advance. A transmission receiver can be realized.

As described above, it is possible to realize a transmission rate detecting circuit capable of selecting a clock that matches a correct transmission rate among clocks assumed according to the present invention, and it is not possible to determine the transmission rate in advance. A digital transmission receiver that can generate a clock that matches the transmission signal and reproduce the input signal can be realized.

Further, in the third invention, if the transmission rate detection operation is performed only during the training period, and the clock is selected by the switching signal determined during the training period during the operation period, the clock that matches the transmission rate more stably can be obtained. Can be selected.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a transmission rate detection circuit according to the present invention.

FIG. 2 is a view for explaining the operation of the configuration of FIG. 1;

FIG. 3 shows a relationship between fluctuation of an integrated voltage and a time constant.

FIG. 4 shows static characteristics of a P-channel field-effect transistor.

FIG. 5 shows static characteristics of an N-channel field effect transistor.

FIG. 6 shows an inverter using a field effect transistor and static characteristics.

FIG. 7 is an equivalent circuit of an inverter.

FIG. 8 shows a charge / discharge operation of a load capacitor of the inverter.

FIG. 9 shows a second embodiment of the transmission rate detection circuit of the present invention.

FIG. 10 shows a third embodiment of the transmission rate detection circuit of the present invention.

11 is a view for explaining the operation of the configuration of FIG. 10;

FIG. 12 shows a fourth embodiment of the transmission rate detection circuit of the present invention.

FIG. 13 is a time chart (1) for explaining the operation of the configuration of FIG. 12;

FIG. 14 is a time chart (part 2) for explaining the operation of the configuration of FIG. 12;

FIG. 15 is a time chart for explaining the operation of the same code continuous time holding circuit.

FIG. 16 shows a fifth embodiment of the transmission rate detection circuit of the present invention.

FIG. 17 shows a configuration example (part 1) of an edge detection circuit.

FIG. 18 is a configuration example (part 2) of an edge detection circuit.

FIG. 19 is a configuration example of a mono-stable multivibrator.

FIG. 20 is a configuration example of a set / reset / flip-flop.

FIG. 21 is a first embodiment of an optical digital transmission receiver using the transmission rate detection circuit of the present invention.

FIG. 22 is a second embodiment of an optical digital transmission receiver using the transmission rate detection circuit of the present invention.

FIG. 23 is a configuration example of a first selection circuit.

FIG. 24 is a third embodiment of an optical digital transmission receiver using the transmission rate detection circuit of the present invention.

FIG. 25 is a view for explaining a transmission rate detection operation when the transmission rate detection circuit of FIG. 1 or 9 is applied to the configuration of FIG. 24;

FIG. 26 is a truth table of the second selection circuit.

FIG. 27 is a configuration example of a second selection circuit.

FIG. 28 is a fourth embodiment of an optical digital transmission receiver using the transmission rate detection circuit of the present invention.

FIG. 29 is a configuration example of an optical digital transmission receiver using a conventional transmission rate detection circuit.

30 shows the principle of the transmission rate detection circuit having the configuration shown in FIG. 29.

FIG. 31 is a configuration example of an optical digital transmission receiver.

FIG. 32 is a configuration example of a digital transmission receiver.

FIG. 33 is a configuration example of an optical digital transmission repeater.

FIG. 34 shows various signal waveforms and spectrum intensities.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Preamplifier circuit 3 Main amplifier circuit 4 Identification circuit 5 Flip-flop 6 Transmission speed detection circuit of the present invention, first transmission speed detection circuit of the present invention 6a Second transmission speed detection circuit of the present invention 6b Conventional transmission rate detection circuit 7 First clock generation circuit, clock generation circuit 7a Second clock generation circuit 8 First frequency division circuit 8a Second frequency division circuit 9 First selection circuit 9a Second selection Circuit 10 Electric-optical conversion circuit 11 Logical product circuit 12 Register 6-1 P-channel type field effect transistor 6-2 N-channel type field effect transistor 6-3 Resistance 6-3a Resistance 6-3b Resistance 6-3c Resistance 6-3d Resistance 6-3e Resistance 6-3f Resistance 6-3g Resistance 6-3h Resistance 6-3j Resistance 6-3k Resistance 6-4 Capacitor 6-4a Capacitor 6-4b Capacitor 6-4c Capacitor 6-4d Capacitor 6-5 Operational amplifier circuit 6-5a Operational amplifier circuit 6-5b Operational amplifier circuit 6-5c Operational amplifier circuit 6-6 Comparison circuit 6-6a Comparison circuit 6-7 PNP transistor 6 -8 NPN transistor 6-9 diode 6-9a diode 6-9b diode 6-9c diode 6-10 counter 6-11 comparison circuit 7-1 phase comparison circuit 7-2 low-pass filter (LPF) 7- 3 Voltage Controlled Oscillator (VCO) 7-4 Band Pass Filter (BPF) 7-5 Timing Amplifier 9-1 Logical Product 9-1a Logical Product 9-1b Logical Product 9-1c Logical Product 9 -1d AND circuit 9-2 OR circuit 9-2a OR circuit 9-3 Inverter 9-3a Inverter 101 P-channel type field effect Transistor 101-1 P-channel field-effect transistor switch 101-2 P-channel field-effect transistor channel resistance 102 Resistance 103 N-channel field-effect transistor 103-1 N-channel field-effect transistor switch 103-2 N-channel type Channel resistance of field-effect transistor 104 Resistance 105 Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K029 AA18 DD02 EE19 HH27 HH29 LL03 LL11 5K034 AA11 FF02 HH02 HH03 HH04 KK04 MM08 5K047 AA16 GG11 GG29 JJ09 MM35 MM53 MM62

Claims (4)

[Claims] An inverter constituted by active elements having complementary characteristics, a circuit for integrating a voltage drop caused by a charge / discharge current of a load capacitor at an output terminal of the inverter, and a voltage caused by a charge / discharge current of the load capacitor A transmission rate detection circuit comprising: a circuit that generates a detection voltage corresponding to a transmission rate from a voltage obtained by integrating the drop; and a comparison circuit that compares the detection voltage with a reference voltage and outputs a clock switching signal. circuit. 2. When the shortest code transmitted at the higher transmission rate of the two transmission rates can be detected from the input digital signal, it is determined that the transmission rate is the higher transmission rate. If the shortest code transmitted at the higher transmission rate of the two transmission rates cannot be detected from the digital signal to be transmitted, the transmission transmitted at the higher transmission rate of the two transmission rates is performed. A transmission rate detection circuit, wherein a transmission rate is determined to be on a low side with a same code continuous time allowed for a code as a protection time, and a clock switching signal is generated. 3. A digital signal identifying a received signal is supplied to at least one of the transmission rate detection circuits according to claim 1 and a plurality of digital signals are output by a switching signal output from the transmission rate detection circuit. A digital transmission receiver which selects a clock matching the transmission speed from the clocks of the digital transmission and reproduces the digital signal. 4. The digital transmission receiver according to claim 3, wherein at least one digital signal identifying a received signal supplied during a training period is converted into at least one digital signal.
And selecting a clock that matches the transmission speed from a plurality of clocks by a switching signal determined by the transmission speed detection circuit during the training period, and supplying the selected clock during the operation period. A digital transmission receiver for reproducing the digital signal.