JP4045223B2 - Burst optical receiver using gain switching method - Google Patents

Description

  The present invention relates to an optical receiving circuit that receives an optical signal and outputs an electrical signal, and is particularly suitable for a PON (Passive Optical Network) type optical receiving circuit that transmits and receives burst signals at high speed.

  In the PON system, the base station is required to have the ability to receive burst signals from each slave station having different light intensities due to the difference in distance between the base station and each slave station. In order to widen the optical reception dynamic range, a pre-amplifier is known which has a clamp method of cutting and outputting an input signal exceeding a specified level. However, due to the waveform extinction due to the deterioration of the extinction ratio of the optical transmission signal and the signal band limitation, the conventional circuit configuration of the receiver using the clamp type preamplifier receives a large signal with a strong strength at which the clamp circuit operates. In this case, the reception output waveform is greatly distorted, and the optical reception dynamic range is limited. This becomes more prominent as the transmission speed increases.

  In order to realize a wide optical reception dynamic range required by the PON system, it is necessary to suppress the pulse width distortion of the reception output signal, and as a means for that, a gain switching system is used for the preamplifier. In the gain switching method, the change in the output signal amplitude is suppressed within a certain range by controlling the gain of the preamplifier. In other words, when a large signal is input, the gain is reduced to limit the amplitude to avoid saturation of the reception output of the preamplifier, and the automatic threshold setting circuit (hereinafter referred to as ATC (Automatic Threshold Control)) in the subsequent stage has a pulse width distortion. A small received output signal is transmitted.

  As the gain switching method, as shown in FIGS. 1 and 4 of Japanese Patent Laid-Open Publication No. 2001-196876, a threshold setting operation of a subsequent automatic threshold setting circuit (hereinafter referred to as ATC) is performed during gain switching of the preamplifier. There is no method.

Japanese Patent Laid-Open No. 2001-196876

In the gain switching type receiver, the preamplifier performs gain switching according to the light intensity of the received signal,
The received signal converted to a level within the specified range is transmitted to the ATC at the subsequent stage.
In the invention described in the above-mentioned published patent publication 2001-196876, in the ATC at the subsequent stage, in order to determine whether the input voltage signal is a regular signal output from a preamplifier or external noise, A signal detection threshold is provided in the previous gate generation circuit. If the magnitude of the voltage signal input to the gate generation circuit preceding the ATC is smaller than the signal detection threshold value, the voltage signal is determined to be noise.

  Here, in order to process a weak signal from the preamplifier, if the signal detection threshold value of the gate generation circuit in the preceding stage of the ATC is set low, an external noise larger than the threshold value is erroneously determined as the output of the preamplifier and the ATC Will be cancelled. For this reason, a signal determination threshold value for determining whether the input voltage is high level or low level in the ATC is set by the external noise, and a malfunction occurs.

  In order to avoid this malfunction, it is necessary to set the signal detection threshold value of the gate generation circuit in the previous stage of the ATC to be high, but if the signal detection threshold value of the gate generation circuit is set high in this way, the weak signal from the preamplifier Since ATC cannot pass through the gate generation circuit, the ATC reset is not released, and the ATC cannot set the signal determination threshold based on the weak signal. That is, the signal detection threshold value in the gate generation circuit restricts the minimum light receiving sensitivity of the receiving device.

  In the present invention, after the external reset signal is input to the preamplifier in the receiving device of the base station, the gain switching is performed in the preamplifier according to the optical burst signal intensity from each slave station. A method (reset method) is used in which a reset signal is sent to the ATC and the received signal level discrimination threshold of the ATC is reset.

  In other words, instead of setting the ATC threshold by releasing the ATC reset by using the first bit of the preamplifier output as a trigger, the ATC signal discrimination threshold can be set once when the ATC reset is released by releasing the external reset signal. State. Then, the signal discrimination threshold is set by the input voltage that is noise or a normal signal input to the ATC. After that, when gain switching occurs in the preamplifier in front of the ATC, a reset signal is sent from the gain switching control unit to the ATC, and the ATC signal discrimination threshold is reset by the voltage signal input to the ATC.

  According to this method, by setting the signal detection threshold value for gain switching in the preamplifier sufficiently higher than the noise level, it is possible to suppress malfunction of the gain switching control unit, that is, unnecessary gain switching. As for the reception of weak signals, the ATC can receive signals when the external reset signal is released. Therefore, the ATC can set the signal discrimination threshold by the weak signal output from the preamplifier, and the minimum light reception. There is no restriction on sensitivity.

  According to the present invention, since the signal determination threshold value of the ATC at the subsequent stage is reset according to the gain switching of the preamplifier, the ATC can set an appropriate signal determination threshold value according to the output of the preamplifier. . Therefore, ATC can correctly determine whether a weak signal output from a preamplifier is noise or a signal.

  Embodiments of the present invention will be described below by dividing them into Embodiment 1 (FIGS. 1 and 2), Embodiment 2 (FIGS. 3 to 9), and Embodiment 3 (FIGS. 10 and 11).

  As a configuration of the present invention, FIG. 1 shows a block diagram of the receiving device 35 and FIG. 2 shows a timing chart. PD1 is a light receiving element that performs processing for converting an optical burst signal received from each slave station into a current. AMP2 performs a process of converting a current output from the light receiving element into a voltage. The gain of AMP2 can be controlled by adjusting the variable impedance 3. The gain switching control unit 4 monitors the voltage value output from the AMP2, adjusts the impedance value of the variable impedance 3 according to the voltage value, and controls the gain of the AMP2. As will be described later, the gain switching control unit 4 adjusts the variable impedance 3 and outputs a reset signal to the ATC 5 so that the signal determination threshold for the input voltage of the ATC 5 is reset according to the switching of the gain of the AMP 2. Send it out.

  The AMP5 with ATC outputs a high level (digital signal level 1) voltage signal when the voltage value output by the AMP2 is larger than the signal determination threshold set by the ATC, and is higher than the threshold set by the ATC. When the voltage is small, a low level (digital signal level 0) voltage signal is output. In this embodiment, the ATC function is incorporated into the AMP to provide the AMP with ATC. However, the ATC and the AMP may be different. In that case, the AMP is arranged between the ATC and the signal processing unit. The signal processing unit 32 is a mechanism for processing a voltage signal converted and amplified by the TIA 33 and the AMP 5 with ATC. The reset signal sending unit 37 performs a process of sending a reset signal to the gain switching control unit 4 and the AMP 5 with ATC via the external reset terminal 31 between the optical burst signal and the next received optical burst signal. With this reset signal, the value of the variable impedance 3 is initialized, or the ATC is reset, and a signal determination threshold can be set.

  Next, the process flow will be described. First, while the optical burst signal is transmitted from each slave station, the external reset signal S1 is input to the ATC 5 and the preamplifier side from the reset signal sending unit 37 via the external reset terminal 31. The external reset signal S1 is sent to the variable impedance 3 as an internal reset signal S2 via the gain switching control unit 4. By receiving this Internal Reset signal S2, the variable impedance 3 is set to an initial value, and the gain of TIA33 is also set to an initial value. Similarly, the threshold for the input voltage of ATC5 is also set to an initial value.

  When an optical burst signal from each slave station of the receiver is input to the receiver, the optical signal is converted into a current signal by the photodiode (PD) 1 that is a light receiving element. This current signal is converted into a voltage signal by a preamplifier 2 (AMP) and a variable impedance 3 (a combination of the preamplifier 2 and the variable impedance 3 is referred to as Trans Impedance AMP, hereinafter abbreviated as TIA). It is sent to the gain switching control unit 4 and the ATC 5.

  The gain switching control unit 4 determines the strength of the voltage signal output from the TIA 33. As an intensity determination method, for example, there is a method of measuring a peak value of a voltage signal. The gain switching control unit 4 sends a gain switching signal S4 according to the measured voltage signal intensity to switch the variable impedance 3, thereby changing the gain of the TIA 33.

  Further, the gain switching control unit 4 changes the gain of the TIA 33 and sends a reset signal S3 to the ATC 5 at the subsequent stage. In the ATC 5 that has received the reset signal S3, the signal level determination threshold value of the TIA output signal S5 is reset. As a threshold value setting method in the ATC 5, for example, means (capacitor or the like) for holding the peak value and the bottom value of the voltage signal output from the preamplifier 5 are provided in the ATC 5, and the output voltage signal of the held preamplifier 5 is held. For example, an intermediate level between the peak value and the bottom value may be set as a threshold value. By receiving the reset signal, the ATC 5 releases the peak value and the bottom value of the held output voltage signal of the amplifier 5 and can set the threshold value again.

  Since the intensity of the optical burst signal from each slave station differs depending on the distance between the base station and each slave station, the number of TIA gain switching and the number of times the reset signal S3 is sent to the ATC 5 is set for each burst signal. Different.

  In order for the signal processing unit 32 to accurately receive the output signal S6 of the AMP 5 with ATC, a clock (clk1) is generated based on the output signal S6 of the AMP 5 with ATC, and the clock (clk1) and the signal processing unit 32 It is necessary to synchronize with the clock (clk2). Here, when the gain of the preamplifier 2 is switched, the phase of the output signal (S6) of the AMP 5 with ATC may change or distortion may occur during gain switching. It is necessary to re-synchronize the clock in the processing unit 32.

  In the present embodiment, the reset signal S3 from the gain switching control unit 4 is also sent to the signal processing unit 32, which is used as a trigger to re-synchronize the clock. That is, the reset signal S3 transmitted from the gain switching control unit 4 to the AMP 5 with ATC is transmitted from the AMP 5 with ATC to the signal processing unit 32 as a reset output signal S7. The signal processing unit 32 that has received the signal S7 performs clock extraction by the clock extraction unit 37, that is, clock synchronization again. In this way, when the gain switching of the preamplifier 2 is performed, the signal processing unit 32 performs the clock extraction operation, so that the signal processing unit 32 of the signal processing unit 32 caused by the phase change of the data output signal S6 accompanying the gain switching is performed. Malfunctions can be suppressed.

  In this embodiment, the signal processing unit 32 is configured to synchronize the clock. However, the ATC-equipped AMP5 may include a clock extracting unit, and the ATC-equipped AMP5 side may be configured to synchronize the clock. .

  As described above, in the first embodiment, the gain switching signal S4 is transmitted from the gain switching control unit 4 according to the light intensity of the burst signal to switch the gain of the TIA 33, and the reset signal from the gain switching control unit 4 to the ATC 5 is also switched. In S3, the signal level discrimination threshold is reset in the ATC5. The data signal S5 sent from the TIA 33 to the AMP5 with ATC is converted to a constant level in the AMP5 with ATC, and sent to the signal processing unit 32 at the subsequent stage as the data output signal S6.

  FIG. 3 shows a configuration example of the preamplifier side when the TIA gain switching is performed in two stages, and FIG. 4 shows a configuration example of the ATC side.

  In FIG. 3, since the outputs of the AND circuits 14 and 19 are Low and the output of the OR circuit 15 is Low in the initial state, the external reset signal S1 input from the external reset terminal passes through the AND circuit 21 and the Internal Reset signal S2. Are input to the three flip-flop circuits 8 (D-FF1), 11 (D-FF2), and 17 (D-FF3), all of the flip-flop circuits are reset, and the Q output is Low and the inverted output of Q is High. At the same time, the internal reset signal S2 is also input to the variable impedance 3, setting the impedance to a high state, and increasing the gain of the TIA as an initial state.

  The optical signal from the transmitter is converted into a current in the photodiode 1 (PD), converted into a voltage by the TIA, and sent to the ATC at the subsequent stage as a data signal S5. The comparator 6 (COMP1) compares the TIA output voltage with the signal detection threshold Vth1, and when a voltage equal to or lower than Vth1 is detected, the inverted output of Q of the flip-flop circuit 8 (D-FF1) at the subsequent stage transitions from High to Low. . While the transition of the inverted output of Q to Low is delayed by the falling edge delay circuit 9 (Fall Deley1) (T1 [s]), the excessive input of the data signal S5 input to the comparator 7 (COMP2) The AND circuit 10 outputs a signal that is less than the determination threshold Vth2.

  For the sake of simplicity, the output signal from the photodiode 1 (PD) is considered at a direct current level, and the operation when the light input intensity is high will be described with reference to the timing chart of FIG.

  When a large signal is input and the output of the AND circuit 10 becomes High, the Q output of the flip-flop circuit 11 (D-FF2) becomes High and the inverted output of Q becomes Low. Here, while the transition of the inverted output of Q to Low is delayed by the falling edge delay circuit 12 (Fall Deley2) (T2 [s]), both inputs to the AND circuit 14 are High, so the output Also during the delay time by the edge delay circuit 12, it becomes High. The high output of the AND circuit 14 becomes the high output of the OR circuit 15 and is sent to the ATC side as the reset signal S3. Further, at the same time, the transition of the Q output of the flip-flop circuit 11 (D-FF2) to High is a trigger, which reduces the impedance of the variable impedance 3 and lowers the TIA gain. Here, T4 [s] is an impedance switching delay time in the variable impedance 3.

  If the TIA output is still smaller than the excessive input determination threshold Vth2 of the comparator 7 (COMP2) even after the gain switching of the TIA, the output of the AND circuit 10 continues to be High. When the output of the falling edge delay circuit 12 (Fall Deley2) transitions to Low after the delay time T2 [s], the output of the AND circuit 16 becomes High, and the flip-flop circuit 17 (D-FF3) The Q output is High and the inverted output of Q is Low.

  While the transition of the inverted output of Q to Low is delayed by the falling edge delay circuit 18 (Fall Deley 3) (T3 [s]), the output of the AND circuit 19 and the output of the OR circuit 15 become High, The reset signal S3 is sent to the ATC side as in the case where the AND circuit 14 becomes High. At the same time, the variable impedance 3 is lowered by using the transition of the Q output of the flip-flop circuit 17 (D-FF3) to High as a trigger to further lower the TIA gain.

  Next, the operation when the optical input intensity is medium will be described with reference to the timing chart FIG. First, an input signal that falls below the excessive input determination threshold Vth2 to the comparator 7 (COMP2) causes one-stage gain switching of the TIA and transmission of the reset signal S3 to the ATC side as in the case where the optical input intensity is large. . However, this gain switching causes the TIA output to exceed the excessive input determination threshold Vth2, the comparator 7 (COMP2) output becomes Low, and the AND circuit 10 output is fixed to Low. Therefore, the circuit subsequent to the AND circuit 10 does not operate, and further gain switching and transmission of the reset signal S3 to the ATC side do not occur.

  Next, the operation when the light input intensity is small will be described with reference to the timing chart FIG. The output of the AND circuit 10 is fixed to Low unless the input signal to the comparator 7 (COMP2) falls below the excessive input determination threshold Vth2. Therefore, the gain switching of TIA and the transmission of the reset signal S3 to the ATC side do not occur.

  Here, with respect to the case where the light input intensity fluctuates with time, the case where the light input intensity is high will be described with reference to the timing chart FIG.

  In FIG. 8, as in the case where the optical input intensity is high (in the case of the timing chart shown in FIG. 5), TIA two-stage gain switching and reset signal S3 are sent to the ATC. After that, even if the optical input intensity fluctuates and the TIA output falls below the excessive input determination threshold Vth2, the Q outputs of the flip-flop circuits 11 (D-FF2) and 17 (D-FF3) are already fixed to High. Therefore, no further TIA gain switching occurs. At this time, the outputs of the falling edge delay circuits 12 (Fall Deley 2) and 18 (Fall Deley 3) are both changed to Low, so the outputs of the AND circuit 14 and the AND circuit 19 are fixed to Low. Therefore, the output of the OR circuit 15 is also fixed to Low, and the reset signal S3 is not sent to the ATC.

  Further, in the case shown in FIG. 9, as in the case where the optical input intensity is medium according to the input optical burst signal (in the case of the timing chart in FIG. 6), one-stage gain switching of TIA and switching to ATC are performed. A reset signal is sent out. Thereafter, when the optical input intensity fluctuates and the TIA output falls below the excessive input determination threshold Vth2, the gain switching at the second stage of the TIA is performed in the same manner as the gain switching at the second stage of the TIA when the optical input intensity is large. And a reset signal is sent to the ATC.

  Note that if the fluctuation of the optical input intensity occurs after the falling delay time T1 [s] of the falling edge delay circuit 9 (Fall Deley1), the output of the AND circuit 10 is fixed low, so that the TIA gain switching And no reset signal is sent to the ATC. In this way, the falling edge delay time T1 [s] of the falling edge delay circuit 9 (Fall Deley1) determines the convergence time of TIA gain switching regardless of the optical input intensity, and the fluctuation degree of signal strength and gain switching The designer can arbitrarily determine the number of times and the delay in each block.

  In the above description, the external reset signal S1 from the ATC side to the preamplifier side and the reset signal S3 from the preamplifier side to the ATC side are transmitted using two independent signal lines. However, the preamplifier needs to be mounted in a photodiode CAN package (PD-CAN) as shown as PD-CAN34 in FIG. 1 for the purpose of high-speed operation and reduction of external noise reception. One ATC generally has a larger chip area than a preamplifier, and it is difficult to mount it in a PD-CAN because the ATC output adversely affects the output of the preamplifier as noise.

  Therefore, the preamplifier and the ATC are mounted spatially separated, and an external reset signal line from the ATC side to the preamplifier side and a reset signal line from the preamplifier side to the ATC side are mounted between the PD-CAN and the ATC. Will be wired. Here, an increase in the number of pins of PD-CAN due to a plurality of wirings becomes a problem in terms of mounting, such as an increase in size of PD-CAN. This mounting problem is solved by sharing the external reset signal line from the ATC side to the preamplifier side and the reset signal line from the preamplifier side to the ATC side as one reset signal line. Can do. That is, in order to reduce the number of pins of PD-CAN, a method of transmitting a reset signal bidirectionally using a single reset signal line as shown below may be used.

  First, an embodiment in which the bidirectional reset signal is positive logic is shown in FIG. 10 and will be described below. Since the OR circuit 15 output is low in the initial state, the bidirectional reset signal level (bidirectional reset unit level) is low, and the reset signal S1 input from the external reset terminal is transmitted to the TIA and ATC. . Further, the MOS switch 20 is turned on by the reset signal output from the OR circuit 15 in accordance with the gain switching of the TIA, and the bidirectional reset signal level transits to High. The transition of the bidirectional reset signal level to High is transmitted to the ATC side as the reset signal S3.

  The bidirectional reset signal line can also be configured using negative logic, and one example thereof is shown in FIG. 11 and will be described below. That is, the reset signal S1 from the outside drives the NPN transistor 28 and a current flows to the constant current source 30, and the bidirectional reset signal level changes from High to Low due to the voltage drop at the impedance 24. Similarly, the reset signal output from the OR circuit 15 in accordance with the gain switching of the TIA drives the NPN transistor 27 so that a current flows to the constant current source 29, and the bidirectional reset signal level is reduced by the voltage drop at the impedance 24. Change from High to Low. By converting the transition of the bidirectional reset signal level from High to Low by the inverter 25 and the inverter 26, the reset signal S1 and the reset signal S3 are transmitted to the TIA and the ATC.

  In the embodiment shown in FIGS. 10 and 11 described above, the reset signal is bidirectionally transmitted on a single wiring between the preamplifier and the ATC in which the number of wirings is limited due to the structure of the receiving device. The above problem can be solved.

It is a block diagram of the receiver explaining the present invention. It is a timing diagram explaining operation | movement of this invention. It is a block diagram which sends out a reset signal from the preamplifier side to the ATC side in accordance with the two-stage gain switching of the TIA which is an embodiment of the present invention. It is a block diagram on the ATC side that receives a reset signal from the preamplifier side in an embodiment of the present invention. It is a timing diagram for demonstrating operation | movement of one Example of this invention, and is a figure in case the optical intensity of an input signal is large. It is a timing diagram for demonstrating operation | movement of one Example of this invention, and is a figure in case the optical intensity of an input signal is medium. It is a timing diagram for demonstrating operation | movement of one Example of this invention, and is a figure in case the optical intensity of an input signal is small. It is a timing diagram for demonstrating operation | movement of one Example of this invention, and is a figure explaining operation | movement in case the optical intensity of an input signal is large and intensity | strength is not stable. It is a timing diagram for demonstrating operation | movement of one Example of this invention, and is a figure explaining operation | movement in case the optical intensity of an input signal is medium and the intensity | strength is not stable. In one embodiment of the present invention, in a configuration in which a reset signal between the preamplifier side and the ATC side is bidirectionally transmitted / received on one reset signal line, the bidirectional reset signal is configured with positive logic. It is an example. In an embodiment of the present invention, in a configuration in which a reset signal between the preamplifier side and the ATC side is bidirectionally transmitted / received on a single reset signal line, the bidirectional reset signal is configured with negative logic. It is an example.

Explanation of symbols

1 Photodiode
2 Preamplifier
3 Variable impedance
4 Gain switching control circuit
5 Amplifier with automatic threshold control circuit
6, 7 Comparator
8, 11, 17 D-flip-flop circuit
9, 12, 18 Delay circuit for transition from high to low (falling edge)
10, 14, 16, 19 AND gate
21 AND gate with negative logic input
13, 25, 26 Inverter
15, 23 OR gate
20 MOS switch
22, 24 impedance
27, 28 transistors
29, 30 Constant current source
31 External reset pin
32 Signal processor
33 TIA
34 PD-CAN
35 Receiver
36 Clock extractor
37 Reset signal transmitter
S1 External reset input signal
S2 Preamplifier internal reset signal
S3 Reset signal from preamplifier side to ATC
S4 Gain switching signal
S5 Data signal from preamplifier to ATC
S6 Data output signal to signal processor
S7 Reset output signal to signal processor

Claims (2)

An optical signal receiving unit that receives an optical signal and converts it into a current signal, a first amplification unit that converts and outputs a current signal output from the optical signal receiving unit into a voltage signal, and a signal determination threshold is set, When a voltage signal output from the first amplifier is larger than the signal determination threshold, a high level voltage signal is output. When a voltage signal output from the first amplifier is lower than the signal determination threshold, a low level voltage is output. In a receiving device having a second amplifier that outputs a signal,
A gain switching control unit that changes the gain of the first amplifier according to the magnitude of the voltage signal output by the first amplifier;
A threshold setting unit configured to set the signal determination threshold according to the magnitude of the voltage signal output by the first amplifier;
A reset signal sending unit that causes the threshold value control unit to reset the threshold value by sending a first reset signal to the threshold value setting unit every time the optical signal is received;
The gain switching control unit is configured to send a second reset signal that causes the threshold setting unit to reset the threshold when changing the gain of the first amplifier,
Between the gain switching control unit and the threshold setting unit, the first reset signal and the second reset signal are bidirectionally transmitted and received on a single signal line,
The threshold setting unit that has received the second reset signal re-sets the signal determination threshold according to the magnitude of the voltage signal output by the first amplification unit after receiving the second reset signal. A receiver characterized by setting. A signal processing unit for processing a voltage signal output from the second amplification unit;
When the threshold setting unit receives the second reset signal, the threshold setting unit outputs the reset signal to the signal processing unit,
The receiving apparatus according to claim 1, wherein the signal processing unit that has received the second reset signal from the threshold setting unit synchronizes with the second amplifying unit.

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