JP2001068481A - Field-effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency of a MESFET and HEMT(High Electron Mobility Transistor) and breakdown voltage between the gate and drain. SOLUTION: A buffer layer 2, a channel layer 3 and source/drain contact layers 4a, 4b are provided on a substrate 1 to constitute a MESFET. A source electrode 5 is brought into ohmic connection to the source contact layer 4a while a drain electrode 6 is brought into ohmic connection to the drain contact layer 4b. A Schottky gate electrode 7 is disposed closer to the source electrode 5 in the channel layer 3 so as to be brought into contact with both the inside and the outside of a recess 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect semiconductor device such as a metal semiconductor field effect transistor (MESFET) and a high electron mobility transistor (HEMT).

Conventional typical MESFETs (Metal Semicondu
1, a semi-insulating GaAs substrate 1, a buffer layer 2, a channel layer 3, a source contact layer 4a, a drain contact layer 4b, and a source electrode, as shown in FIG. 5 and drain electrode 6
And a gate electrode 7. The channel layer 3 has a first recess or recess 8 for obtaining a narrow channel, and the gate electrode 6 is arranged at the center of the first recess 8 and is in Schottky contact with the channel layer 3. The source electrode 5 is a source
The drain electrode 6 is ohmic-connected to the drain contact layer 4b. The source contact layer 4a and the drain contact layer 4b are arranged to face each other such that a second recess, that is, a recess 9 is formed on the channel layer 3. This MESF
In the ET, the spread of the depletion layer of the channel layer 3 is changed by the change in the voltage applied to the gate electrode 7, and the drain current is controlled.

[0003]

SUMMARY OF THE INVENTION MASFETs and HEMTs (High Electron Moments) used in transmission power amplifiers and the like of cellular phones
vility Transistors) are required to have high efficiency and high withstand voltage. In order to realize high efficiency, it is necessary to reduce the on-resistance. In order to reduce the ON resistance of the MESFET or HEMT, it is necessary to reduce the source-gate resistance Rs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a field effect type semiconductor device capable of reducing the gate-source resistance Rs and improving the gate-drain breakdown voltage. is there.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the above object, the present invention provides a current path forming region comprising a single or a plurality of semiconductor layers, and an ohmic contact formed in the current path forming region. A Schottky contact is made between the connected source electrode and the drain electrode and the current path forming region between the source electrode and the drain electrode so that a depletion layer can be formed in the current path forming region. A recess formed in the current path forming region so as to partially thin the current path forming region, wherein the gate electrode is provided with the concave portion. Wherein the semiconductor device is arranged so as to include the step on the source electrode side.

[0006] As described in claim 2, the present invention is applied to ME
Applicable to SFET. Further, as described in claim 3, the present invention can be applied to HEMT.

[0007]

According to the present invention, the following effects can be obtained. (A) Since the gate electrode is arranged so as to include a step on the source electrode side of the concave portion, the control characteristics of the current path (channel) by the depletion layer are maintained almost in the same manner as in the prior art. The resistance Rs between switches can be reduced. That is, the portion of the concave portion of the gate electrode which is arranged at a position with a low step acts in the same manner as the conventional gate electrode within the concave portion, and is arranged at the position of a high step of the concave portion of the gate electrode. The portion contributes to the reduction of the resistance value between the gate electrode and the source electrode. As described above, when the resistance Rs between the gate and the source is reduced, the on-resistance of the field-effect semiconductor device can be reduced, and the efficiency is improved. (B) By disposing the gate electrode on the source electrode side, the distance between the gate electrode and the drain electrode is increased, and the withstand voltage between the gate and the drain is improved.

[0008]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS.

[0009]

First Embodiment The metal semiconductor field effect transistor or MES of the first embodiment shown in FIGS.
The FET includes a semi-insulating GaAs substrate 1, a buffer layer 2, and a channel layer 3 as in the conventional MESFET of FIG.
And a source contact layer 4a, a drain contact layer 4b, a source electrode 5, a drain electrode 6, and a gate electrode 7. Substrate 1 a buffer layer 2 disposed on a uniform thickness on the throat - consists of GaAs-flop, the channel layer 3 disposed on the buffer layer 2, n ^- form of G
consists GaAs, the contact layer 4a, 4b is n ⁺ form of G
aAs.

A current path forming region 10 between the source electrode 5 and the drain electrode 6 is formed by a semiconductor region comprising a buffer layer 2, a channel layer 3, and contact layers 4a and 4b which are sequentially laminated on a substrate 1. Is configured. A first recess 8 is formed substantially at the center of the current path forming region 10 between the source electrode 5 and the drain electrode 6, that is, substantially at the center of the channel layer 3, as in FIG. Therefore, the channel layer 3 has a thin portion 3a and a thicker portion 3b. Since the source contact layer 4a and the drain contact layer 4b are formed in a strip shape on the channel layer 3,
A second recess 9 is formed between the source and drain contact layers 4a, 4b. The source electrode 5 is ohmic-connected to the source contact layer 4a, and the drain electrode 6 is ohmic-connected to the drain contact layer 4b. The gate electrode 7 is made of a material such as Ti, Au, Pt, or Al and is Schottky-connected to the channel layer 3 so that a Schottky barrier is generated between the gate electrode 7 and the channel layer 3. The gate electrode 7 is arranged so as to include a step 8a on the source electrode 5 side of the first concave portion 8 according to the present invention. That is, gate - gate electrode 7 is not provided in the longitudinal drain-side portion of the L ₁ in step 8b and recess 8 of the drain electrode 6 side, source - in the scan-side step portion 8a and the recesses 8 And a part of the source side outside the recess 8. Therefore, the gate electrode 7 is in contact with both the thin portion 3a and the thick portion 3b of the channel layer 3.

The source contact layer 4a, the drain contact layer 4b, the first recess 8, the source electrode 5, the drain electrode 6, and the gate electrode 7 extend in a strip shape as shown in the plan view of FIG. ing. Although not shown in FIGS. 2 and 3, the contact layers 4a, 4a
b, a first recess 8, a plurality of source electrodes 5, a drain electrode 6, and a plurality of gate electrodes 7 are provided. The plurality of electrodes 5 are connected to a common source pad. Are connected to a common drain pad, and a plurality of gate electrodes 7
Are connected to a common gate pad.

When using the MESFET, as is well known,
A drain-source voltage is applied so that the drain electrode 6 is positive and the source electrode 5 is negative, and a control voltage is applied between the gate and source. When a negative voltage is applied to the gate electrode 7 with respect to the source electrode 5, the extent of the depletion layer in the channel layer 3 changes according to the magnitude of the negative voltage, and the magnitude of the drain current increases. Changes.

The MESFET of this embodiment has the following effects. (1) Since the gate electrode 7 is arranged so as to include the step 8a of the concave portion 8 near the source electrode 5, and is in contact with both the thin portion 3a and the thick portion 3b of the channel layer 3, The drain side portion of the gate electrode 7 is formed by the conventional MESF shown in FIG.
Like the ET, it effectively acts on the expansion of the depletion layer in the thin portion 3a of the channel layer 3. Since the source side portion of the gate electrode 7 is in contact with the thick portion 3b of the channel layer 3, the gate electrode 7 is in contact with the gate. This contributes to a reduction in the resistance Rs between the source and the source. As is well known, when the resistance Rs between the gate and the source decreases, the on-resistance of the FET decreases and the efficiency improves. (2) By arranging the gate electrode 7 near the source electrode 5, the distance between the gate electrode 7 and the drain electrode 6 is increased, and the length of the thin portion 3a of the channel layer 3 between the two. L ₁ is increased, the Soviet Union - the scan-to-drain breakdown voltage can be improved.

[0014]

Second Embodiment Next, the MESF of the second embodiment shown in FIG.
Explain ET. However, in FIG. 4 and FIGS. 5 and 6 described later, substantially the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof will be omitted. The MESFET of FIG.
The source contact layer 4a and the drain contact layer 4b are omitted from the MESFET of FIG. As shown in FIG. 4, the same effect can be obtained in the case where the source electrode 5 and the drain electrode 6 are ohmic-connected to the channel layer 3 by making the arrangement of the gate electrode 7 the same as in FIG. can get.

[0015]

Third Embodiment The MESFET of the third embodiment shown in FIG.
In place of the contact layers 4a and 4b of FIG.
In addition, n ⁺ -type contact regions 11 and 12 are provided below the drain electrode 6 based on the implantation of n-type impurity ions, and the other structure is the same as that of FIG. Contact region 11,
12 is a buffer layer 2 formed entirely on the substrate 1
The contact region 1 is formed by selectively implanting ions into the channel layer 3 by a known method.
A source electrode 5 and a drain electrode 6 are ohmically connected to 1 and 12, respectively. Since the gate electrode 7 is also formed in the MESFET of FIG. 5 in the same manner as in FIG. 2, the MESFET of FIG. 5 has the same effect as the MESFET of FIG.

[0016]

Fourth Embodiment FIG. 6 schematically shows a HEMT to which the present invention is applied. The HEMT includes a semiconductor substrate 1 made of a semi-insulating GaAs semiconductor, and a buffer layer or a P-type GaAs semiconductor layer made of an N-type GaAs semiconductor having a relatively low impurity concentration formed on the upper surface of the substrate 1. A buffer layer 21 composed of a plurality of layers and N 2 having a relatively high impurity concentration
Electron supply layer 22 made of AlGaAs semiconductor
A channel layer 23 made of a GaAs semiconductor or an InGaAs semiconductor having substantially no impurities doped therein, a second electron supply layer 24 made of an N-type AlGaAs semiconductor having a relatively high impurity concentration, And a source and drain contact layer 4a, 4b made of a GaAs semiconductor having a relatively high impurity concentration. In this embodiment, the current path forming region 10a
Is composed of a buffer layer 21, a first electron supply layer 22, a channel layer 23, a second electron supply layer 24, a Schottky layer 25, and contact layers 4a and 4b which are sequentially stacked. Therefore, the current path forming region 10a includes a compound semiconductor heterojunction to obtain a known two-dimensional electron gas layer.

A recess 8 is formed in the Schottky layer 25 of FIG. 6 similarly to the channel layer 3 of FIG. 2, and the gate electrode 7 is arranged so as to include the step 8a on the source side of the recess 8. Thus, the Schottky layer 25 is in contact with the Schottky layer. Also in this HEMT, the source electrode 5 and the drain electrode 6
A voltage is applied to the gate electrode 7 in the same manner as in the MESFT of FIG. 2, and the drain current flowing between the source electrode 5 and the drain electrode 6 is controlled based on the voltage of the gate electrode 7. That is, the spread of the depletion layer of the channel layer 23 is controlled based on the gate-source voltage, and the drain current flowing therethrough is controlled.

In the HEMT shown in FIG.
Are arranged in the same manner as in FIG.
The same effect as T can be obtained.

[0019]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The HEMT of FIG. 6 can have a configuration in which the contact layers 4a and 4b are omitted as in FIG.
Also in the HEMT of FIG. 6, contact regions 11 and 12 can be provided by ion implantation as in FIG. (2) Increase / decrease in the number of semiconductor layers in the current path forming region 10 of the MESFET, and the current path forming region 10a of the HEMT
The number of semiconductor layers can be increased or decreased. (3) The gate electrode can be provided only on the step 8a. The portion provided on the flat portion in the recess 8 of the gate electrode 7 preferably has a width of 2 in the lateral direction of FIG.
It is desirable that the thickness be within or less, more preferably １ ／ or less.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a conventional MESFET.

FIG. 2 is a sectional view showing a part of the MESFET according to the first embodiment of the present invention.

FIG. 3 is a plan view of the MESFET of FIG. 2;

FIG. 4 is a sectional view showing a part of the MESFET of the second embodiment.

FIG. 5 is a sectional view showing a part of the MESFET of the third embodiment.

FIG. 6 is a sectional view showing a part of the HEMT according to a fourth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Channel layer 4a, 4b Contact layer 5 Source electrode 6 Drain electrode 7 Gate electrode 8 Depression

Claims (3)

[Claims] A current path forming region including a single or a plurality of semiconductor layers; a source electrode and a drain electrode ohmically connected to the current path forming region; and a depletion layer in the current path forming region. So that it can be formed
A field effect type semiconductor device having a gate electrode in Schottky contact with the current path forming region between a source electrode and the drain electrode, wherein the current path forming region is partially thinned. A semiconductor device, wherein a recess is provided in the current path forming region, and the gate electrode is arranged so as to include a step portion of the recess on the source electrode side. 2. The method according to claim 1, wherein the field-effect semiconductor device is a metal-based semiconductor device.
Semiconductor field effect transistor (MESFET)
2. The field effect semiconductor device according to claim 1, wherein the current path forming region has a channel layer, a combination of a buffer layer and a channel layer, or a combination of a buffer layer, a channel layer, and a contact layer. . 3. The field-effect semiconductor device according to claim 1, wherein said field-effect semiconductor device is a high electron mobility transistor (HEMT), and said current path forming region includes a compound semiconductor heterojunction.