JPS62188380A - Field effect transistor - Google Patents

Abstract

PURPOSE:To realize a high-performance transistor with its source/drain gap reduced, source resistance greatly lowered, and mutual conductance high by a method wherein source/drain electrodes are located lower than the surface of a gate-carrying upper semiconductor layer constituting a heterojunction and extend into under the gate electrode. CONSTITUTION:A heterojunction is built of a high-purity or P-type first semiconductor layer 4 and a second semiconductor layer 2 with its electron affinity weaker than that of the first semiconductor layer 4. A gate electrode 1 is provided for controlling the number of carriers in an electron channel formed in the hetero interface and source/drain electrodes 6 are formed on both sides of the gate electrode 1, respectively. In such a field effect transistor the source/drain electrodes 6 are located under the surface of the second semiconductor layer 2 and extend into under the gate electrode 1. For example, on a semi-insulating GaAs substrate 5, a P<->-GaAs layer 4 is grown and, as a second semiconductor layer 2, a wafer is formed of an N-Al0.3Ga0.7As layer, N-AlxGa1-xAs layer, and N-GaAs layer, formed in that order. On the wafer, an Al- made gate electrode 1 is built. Ti, Au, Ge, and Ni are attached to the opening wherein source/drain regions are embedded, to be subjected to heat treatment for conversion into an alloy for the construction of source/drain electrodes 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high performance field effect transistors with low parasitic resistance and small dimensions.

[Conventional technology]

As the structure of the conventional field effect transistor, the master and M wind s
A case of a semiconductor device using a two-dimensional electron gas at a hetero-interface will be described.

The structure of this field effect transistor is as shown in FIG. AI doped into the mold! A 0.3Gα0,7Aa layer is used. In this structure, the first semiconductor 4 is made of GaAs.
Due to the difference in electron affinity between the second semiconductor 2 and JGaAs, a two-dimensional electron gas is formed on the GaAs side. Then, for the source and drain electrodes, a wire mesh containing AuGe/Ni is deposited on the surface of the second semiconductor, and alloying is performed to form the second semiconductor layer 2 and the first semiconductor layer with a low donor impurity density in the depth direction. 4 is directly alloyed to reach the two-dimensional electronic layer.

In the figure, 1 is a gate electrode, 3 is a two-dimensional electron gas, and 6 is an ohmic electrode.

[Problem that the invention seeks to solve]

In a field effect transistor having the above structure, important factors for obtaining high performance characteristics include reducing the source resistance and shortening the gate length. One way to do this is to shorten the distance between the source and gate, and between the gate and drain. However, in the conventional structure, the limit is 0.5 μm between the source and gate, and if you try to make the distance closer than that, it is difficult to 34. The drain metal and the entire gate react and come into contact. (
As shown in b), a device in which an n+ region 8 is formed next to the gate by K ion implantation has been reported (IEE Electron Device EEL-5).

129 (1984)), in this case the second semiconductor Jg
Because the thickness of the n-AlGaAs layer, which is II2, is as thin as several hundred ions, it is difficult to implant high-dose ions into such a shallow area.If implanted deeply to obtain a small sheet resistance, that is, a low source resistance, the drain conductance can be reduced. increases. In addition, the gate reverse breakdown voltage is low, and annealing treatment at a high temperature is required, which has the drawback of causing crystal deterioration at the hetero interface and changes in the threshold voltage.

The present invention provides a microscopic, high-performance transistor that overcomes the limitations in element structure and performance of the prior art as described above.

[Means for solving problems]

The present invention includes a heterojunction between a high-purity or P-type first semiconductor layer and a second semiconductor layer having a lower electron affinity, and a gate electrode that controls the number of carriers in an electron channel formed at the Peter interface. and a field effect transistor in which a source electrode and a drain electrode are provided across the gate electrode, characterized in that the field effect transistor has a source/drain electrode below the surface of the second semiconductor layer and extending into the gate side. This is a field-effect transistor.

[Effect]

The structure and effects of the present invention will be described below with reference to the cross-sectional structure shown in FIG.

As shown in FIG. 1 (α), a gate electrode l having a gate length d1 is formed on a wafer in which a first semiconductor layer 4 and a second semiconductor layer 2 are successively laminated on a local resistance substrate 5. The source/drain electrodes are formed laterally below the surface of the second semiconductor layer 2 by a thickness d in the gate direction. Now, if the length of the second half conductor layer 2 is d, then the effective source-drain spacing Hd, -2d, and the source-drain distance of the conventional structure shown in FIG.
It becomes shorter than the drain interval d3. Therefore, the source resistance is significantly reduced and the carrier transit time is also shortened. Further, when GaAs is used as the first semiconductor layer 4 and MλM is used as the second semiconductor layer 2, the mean free path of electrons in GaAs is w as shown in Table 1, and according to the structure of the present invention, From the relationship between the length d of the semiconductor layer 2 in No. 2 and the lateral depth d of the ohmic electrode 6 region, it is possible to easily approach the source-drain distance to about 0.1 μm. As a result, the spacing between the source and drain electrodes is sufficiently shorter than the mean free path of electrons, and the ballistic conduction effect, in which electrons pass between the electrodes without being scattered, becomes noticeable, and ultra-high-speed operation is expected.Table 1
na [Examples] Examples of the present invention will be described in detail below.

As shown in FIG. 2 (α), a single layer of P-G with a carrier density of #1x1014d3 and a thickness of 0.8 μm is grown as a first semiconductor layer 4 by MBE method on a semi-insulating GIZA s substrate 5, , and further has a donor density of 2×1 as the second semiconductor layer 2.
0"c+ff", 100 people n-M6.3-07 8 layers, 200 people thickness, M and As(1) molar ratio is 0.3
A gate 1 of M is formed on a wafer on which an n=MxGcL, . The source and drain electrodes are
After etching the source/drain region by 700 layers and digging down to the second semiconductor layer 2, Ti: 20 layers, AuG
e: 500A.

Ni: 150A is deposited only on the source/drain electrode openings. Thereafter, the ohmic gold stripes are alloyed by heat treatment to form source and drain electrodes. At this time, during the heat treatment, about 11 μm of O diffuses in the lateral direction, that is, in the gate direction, so the alloy layer that will become the ohmic electrode 6 is
It is formed laterally by about 0.1 μm below the surface of the semiconductor layer 40 . Therefore, the distance between the source and drain is approximately 0.2 μ narrower than the length of the first semiconductor layer 4. As a result, source resistance was significantly reduced and mutual conductance was greatly improved. Here, the 20-layer Ti layer acts as a stopper 7 to prevent the diffusion of AuGe in the depth direction, and as a result, even if the gate length is shortened, the short channel effect is small, and a high-performance field effect transistor with fine dimensions can be realized.

Furthermore, if the gate length is set to 0.3 μm and the length of the first semiconductor layer 4 is made the same as the gate length as shown in FIG. 2(b),
The distance between the source and drain is 0.1 μms, and a halitic conduction effect is also expected.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to realize a high-performance field effect transistor having a short source-drain interval, a significantly reduced source resistance, and high mutual conductance. Furthermore, the present invention has the effect of realizing a ballistic conduction phenomenon.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a field effect transistor according to the present invention, FIGS. 2 (α) and (b) are cross-sectional views showing embodiments of the present invention, and FIG. 3 (α) is a cross-sectional view of a short interelectrode structure. FIG. 3(b) is a sectional view showing an n+-cella line structure formed by ion implantation. 1... Gate electrode 2... Second semiconductor layer 3
...Two-dimensional electron gas 4...First semiconductor layer 5.
...High resistance substrate 6...Ohmic electrode 7...
・Stopper patent applicant: NEC Co., Ltd.

Claims (1)

[Claims] (1) A gate electrode that has a heterojunction between a high-purity or P-type first semiconductor layer and a second semiconductor layer that has a lower electron affinity, and controls the number of carriers in the electron channel formed at the heterointerface. and a field effect transistor in which a source electrode and a drain electrode are provided across the gate electrode, the source and drain electrodes being below the surface of the second semiconductor layer and extending into the gate side. A field effect transistor featuring: