JP2001063128A - Image recorded and recording method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reproducibility of halftone by classifying the gradation levels into a plurality of groups in the order of gradation level, making the recording voltage variable depending on a group to which the gradation level of an image signal belongs and making the recording time variable depending on the gradation level of the image signal for a part which can not be reproduced with the recording voltage. SOLUTION: A control section 10 transfers the image signal of a pixel to be recorded to three registers 11-13. An image signal inputted to the register 11 is transferred to the register 12 thence to the register 13 and the image signal of three pixels is stored. Subsequently, a subtrator 14-16 latches an image signal outputted from the register 11-13 with a latch signal delivered from the control section 10. An AND gate 17-19 of an output signal from the subtrator 14-16 and a clear signal from the control section 10 outputs a recording time signal. The recording time signal is fed, along with a recording voltage signal from a recording voltage generating section 22, to a recording head 20 and recording is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image recording apparatus and an image recording method for performing halftone recording with high reproducibility by combining a recording voltage and a recording time.

[0002]

2. Description of the Related Art Conventionally, a printer device that performs halftone printing reproduces halftone by changing a recording voltage applied to a recording element or an application time (recording time) of the recording voltage.

For example, Japanese Patent Application Laid-Open No. Hei 3-213365 discloses that
A printer device is disclosed in which the density of pixels to be printed can be changed by changing the printing voltage applied to the printing head. Japanese Patent Application Laid-Open No. Sho 62-105649 discloses a printer device that performs halftone printing by controlling the recording pulse width that defines the power supply period to the thermal head and changing the effective energy.

As described above, the conventional printer device reproduces a halftone by controlling the effective energy supplied to the recording element by changing the recording voltage or the recording time.

[0005]

However, in the conventional printer device, since halftone recording is performed by changing only one of the recording voltage and the recording time, a large dynamic range cannot be obtained. There was a limit to the reproduction of the key.

In order to deal with an image signal having a high number of gradations, a digital image signal for D / A conversion is required.
There is a problem that the circuit scale of the A converter becomes large and the cost increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and by combining a recording voltage and a recording time to obtain a desired density, a large dynamic range can be obtained and the reproducibility of halftones can be improved. It is an object of the present invention to provide an image recording apparatus and an image recording method which can improve the number of types of recording voltages, and can prevent an increase in circuit scale.

[0008]

According to the present invention, the gradation levels are classified into a plurality of groups in order of density, and the recording voltage is made variable according to the group to which the gradation level of the image signal belongs. The part that cannot be covered is reproduced finely by changing the recording time according to the gradation level of the image signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first aspect of the present invention relates to a recording element for performing recording at a density corresponding to a recording voltage and a recording time;
An image recording apparatus comprising: a recording voltage variable unit that changes the recording voltage in accordance with an upper bit of an image signal; and a recording time variable unit that changes the recording time in accordance with a lower bit or all bits of the image signal. .

According to this configuration, it is possible to perform halftone recording using a combination of the recording voltage and the recording time, thereby increasing the dynamic range and improving the reproducibility of the halftone.

According to a second aspect of the present invention, in the image recording apparatus according to the first aspect, the recording voltage varying means arranges the gradation levels in the order of density and sets the gradation level with the upper bit of bit data representing each gradation level. The recording voltages are classified into a plurality of groups, and the recording voltages of the groups to which the upper bits of the image signal belong are generated.

According to this configuration, since the recording voltage varying means only needs to generate the recording voltage corresponding to the upper bits of the image signal, the number of bits can be reduced, the circuit scale can be suppressed, and all the gradations can be reduced. There is no need to generate a recording voltage corresponding to the level, and the number of types of voltages can be reduced.

According to a third aspect of the present invention, in the image recording apparatus according to the first or second aspect, the recording time varying means registers a recording time for lower bits or all bits of bit data representing each gradation level. It is provided with a recording time table and a recording time timer for measuring the recording time taken out of the recording time table.

According to this configuration, since the recording time for the lower bits or all bits of the bit data representing each gradation level is registered in the recording time table, the recording time for the lower bits or all bits of the image signal can be obtained. Thus, a portion that cannot be reproduced by the recording voltage can be reproduced in the recording time.

In a fourth aspect of the present invention, a register for holding an image signal, the image signal held in the register are latched, and the gradation level of the image signal is decremented each time a time-over signal is input. A subtractor; a gate circuit for outputting a recording time signal of logic 1 until the gradation level of the image signal latched by the subtractor becomes 0 level; A counter that increments each time an over signal is input, voltage generating means for changing the recording voltage in accordance with the upper bits of the counter, and a counter in which the recording time for the lower bits or all bits of the bit data representing each gradation level is registered. Recording time table that outputs the recording time for the lower bits or all the bits of A recording time timer that outputs a time-over signal when the recording time reaches the recording time obtained by measuring the recording time, and a recording voltage generated by the voltage generating means is applied over a period in which the recording time signal is logic 1. And a recording element for performing halftone recording.

According to this configuration, while the count value of the counter is counted up from the 0 level to the gradation level of the image signal, the recording voltage is switched in accordance with the change of the upper bit of the counter, while being latched by the subtractor. However, the recording time is continued until the tone level of the signal becomes 0 level.

A fifth aspect of the present invention is the image recording apparatus according to the fourth aspect, further comprising a gate for outputting a lower bit of the image signal when an upper bit of the image signal matches an upper bit of the counter. did.

According to this configuration, since the lower bits of the image signal are not latched by the subtractor until the upper bits of the image signal match the upper bits of the counter, a recording voltage corresponding to the upper bits of the image signal is obtained. By the way, since the recording time signal becomes logic 1 and only the lower bits are latched by the subtractor, there is only one kind of recording voltage.

According to a sixth aspect of the present invention, the gradation levels are arranged in order of density, and the gradation levels are classified into a plurality of groups by the upper bits of the bit data representing each gradation level. While generating a recording voltage, a recording time corresponding to the lower bits or all bits of the image signal is taken out from a recording time table in which recording times for lower bits or all bits of bit data representing each gradation level are registered. An image recording method characterized in that halftone recording is performed by combining the recording time obtained and the recording voltage.

According to this method, halftone recording using a combination of the recording voltage and the recording time becomes possible, the dynamic range can be increased, and the reproducibility of the halftone can be improved.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

(First Embodiment) FIG. 1 is a functional block diagram of an image recording apparatus according to a first embodiment of the present invention.
In the present embodiment, it is assumed that the image signal is 5-bit data having 32 gradation levels, and that the recording head includes three recording elements.

The operation of the entire image recording apparatus of the present embodiment is controlled by the control unit 10. Control unit 10
The three registers 11 store the image signal of the pixel to be recorded.
To the shift register composed of.

The shift register is a first register 11
Is transferred to the second register 12, and
The second register 12 transfers the input image signal to the third register 13 to store the image signals for three pixels.

Three subtractors 14 to 16 are connected in parallel to the output stages of the three registers 11 to 13. Subtractor 1
4 to 16 latch the image signals output from the corresponding registers 11 to 13 by the latch signal supplied from the control unit 10. The gradation level of the latched image signal is decremented each time a time-over signal described later is input. The subtractors 14 to 16 maintain the output signal of logic 1 until the gradation level of the latched image signal becomes 0 level.

Three AND gates 17 to 19 are connected in parallel to the output stages of the three subtractors 14 to 16. AN
D gates 17 to 19 are respectively provided with corresponding subtracters 14 to 16
Of the output signal from the controller and the clear signal given from the control unit 10. When both the output signal of the subtractor and the clear signal are at logic 1, a recording time signal of logic 1 is output.

The three recording time signals output from the AND gates 17 to 19 are input to the recording head 20 in parallel. The recording head 20 is composed of three recording elements as described above. Recording time signals are input from AND gates 17 to 19 corresponding to each of the three recording elements. To each recording element, a recording voltage generated by a recording voltage generation unit 22 described later is applied over a period in which a recording time signal is a logic 1. Then, recording is performed at a density corresponding to the effective energy obtained by combining the recording voltage and the recording time.

On the other hand, the recording voltage and the recording time are controlled based on the count value of the counter 21. The counter 21 sequentially counts up 5-bit bit data from one gradation level to 31 gradation levels corresponding to the 31 gradation levels. The counter 21 counts up each time a counter increment signal described later is input.

FIG. 2 shows a state where 5-bit bit data from the 0th gradation level to the 31st gradation level are arranged in the order of density. As shown in the figure, the upper two bits of the bit data representing the gradation level are divided into four groups G for each density.
1 to G4.

In the present embodiment, the upper two
The bits are input to the recording voltage generator 22. The recording voltage generator 22 determines the recording voltage to be generated for each group, and generates a recording voltage corresponding to the group to which the upper two bits input from the counter 21 belong. As described above, since it is sufficient that four types of recording voltages can be generated in order to perform halftone recording of 32 gradations, the recording voltage generation unit 22
Is simplified, and four types of high-precision recording voltages can be easily generated.

In this embodiment, all bits (upper bits and remaining lower bits) of the counter 21 are input to the recording time table 23. The recording time table 23 is
As shown in FIG. 3, the recording times T0 to T correspond to the 5-bit bit data from one gradation level to 31 gradation levels.
31 are registered. Recording time T0 to T31
Is set to a time width that can compensate for a portion that cannot be reproduced with four types of recording voltages. The recording time table 23 is
When all the bits of the counter 21 are input from the counter 21, the corresponding recording time Ti is output.

The recording time Ti output from the recording time table 23 is given to a recording time timer 24. The recording time timer 24 starts counting when the recording time Ti is given, and outputs a time-over signal when the recording time Ti has elapsed. The time-over signal is supplied to the subtracters 14 to 16 as a signal for subtraction, while the counter 21
Is provided as a counter increment signal.

The operation of the image recording apparatus configured as described above will be described. First, the control unit 10 resets the counter 21 by setting the clear signal to logic 0,
The AND gates 17 to 19 are closed.

The shift register (11 to 1)
The image signal is transferred to 3) in synchronization with the clock signal, and the shift registers (11 to 13) hold the image signals for three pixels.

When the transfer of image signals for three pixels is completed, the control unit 10 turns on the latch signal and latches the image signals of the registers 11 to 13 to the corresponding subtracters 14 to 16.

Next, the control unit 10 switches the clear signal from logic 0 to logic 1. Thus, the recording time timer 24 is activated, and the counter 21 outputs bit data (00001) of one gradation level as initial data.

The recording voltage generator 22 generates a recording voltage corresponding to the group G1 to which the counter upper bit (00) belongs. FIG. 4 shows four types of recording voltages V1 to V4 generated by the recording voltage generator 22.

When the gradation level of the image signal belongs to the group G1, how much the recording voltage V1 is maintained is determined according to all the bits of the image signal. The recording time at the recording voltage V1 is subdivided into T0 to T6, and the accumulated time between T0 and T6 is determined according to the gradation level of the image signal.

On the other hand, if the gradation level of the image signal is the recording voltage Gi equal to or higher than G2, the effective energy is accumulated at the recording voltage of each group up to Gi, and then the recording is performed at the Gi recording voltage. Storage time gradation level of image signal (all bits)
It is decided according to.

That is, in this embodiment, the effective energy supplied to the recording element is accumulated stepwise as shown in FIG. 4, and the end of the accumulation time is determined by the gradation level (all bits) of the image signal. I am trying to be. FIG. 5 shows an example of the effective energy when the gradation level of the image signal is 10 gradation levels.

In this embodiment, the following method is employed to determine the end of the accumulation time. That is, the counter 21 sequentially counts up bit data from one gradation level to 31 gradation levels, and the recording time Ti at each gradation level is measured by the recording time timer 24. Then, the gradation levels of the image signal are subtracted one by one in synchronization with the time-over signal by the subtracters 14 to 16 and when the zero level is reached, the AND gate is closed to stop the accumulation of the effective energy. Thus, the count-up timing of the counter 21 and the subtractors 14 to 16
By synchronizing the timing of subtracting the gradation level of the image signal latched to the time-over signal, the recording time T
The accumulation of effective energy can be controlled in units of i.

As described above, according to the present embodiment, halftone recording can be performed by combining the recording voltage and the recording time, so that the dynamic range can be increased and a high-quality recorded image can be obtained. Can be.

Further, while the recording voltage is largely changed for each density group, the recording time is subdivided, so that the type of recording voltage can be reduced, the number of input bits can be reduced, and the circuit scale can be reduced.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described. The second embodiment is an example in which the effective energy is accumulated only by the recording voltage of the group to which the gradation level of the image signal belongs, instead of sequentially changing the recording voltage supplied to the recording element during the accumulation period.

FIG. 6 is a functional block diagram of the image recording apparatus according to the second embodiment. Parts having the same functions as those of the image recording apparatus shown in FIG. 1 are denoted by the same reference numerals.

In this embodiment, the shift register (11
13) and the subtractors 14 to 16 are provided with a gate unit 60. The gate unit 60 includes registers 11 to 1
When the upper bit of the image signal held in 3 coincides with the upper bit of the counter 21, the operation is performed so as to output the lower bit of the image signal to the subtractors 14-16.

FIG. 7 is a circuit diagram of the gate section 60.
The gate unit 60 includes gate circuits 81 to 83 provided corresponding to the registers 11 to 13, respectively, and gate circuits 81 to 8
Comparing units 84 to 8 for generating gate-on signals for
6 is comprised. Each of the gate circuits 81 to 83 receives an image signal from the corresponding register 11 to 13 and receives only a lower bit of the image signal when a gate-on signal is input from each of the comparators 84 to 86. The comparator 84 receives the image signal input to the corresponding gate circuit and the upper bit of the counter 21 and, when the upper bit (A) of the image signal matches the upper bit (B) of the counter, matches the gate-on signal. Output to the gate circuit.

In the present image recording apparatus configured as described above, even if the control unit 10 switches the clear signal from logic 0 to logic 1, the upper bits of the counter 21 are the same as the upper bits of the image signal input to the gate circuit. Subtractor 14 until they match
The output signals of .about.16 remain at logic zero. Subtractor 14 ~
While the output signal of 16 is logic 0, AND gates 17-19
Remains closed, so that the recording time signal becomes logic 0.
During the period when the recording time signal is logic 0, the recording voltage generated by the recording voltage generator 22 corresponding to the upper bits of the counter is not applied to the corresponding recording element of the recording head.

When the counter 21 is incremented by the counter increment signal,
When the upper bits of the counter match the upper bits of the image signal input to the gate circuit, the lower bits of the image signal are output to the corresponding subtractors (14 to 16). Since the lower bits held in the subtractor are for specific upper bits, the subtracter has held the gradation level in the group to which the image signal belongs.

When the lower bit is latched by the subtractor, the recording time signal output from the AND gate becomes logic 1.
The subtractor performs subtraction every time a time-over signal is input from the lower bits of the image signal. When the lower bit held in the subtractor becomes 0, the logic of the recording time signal output from the AND gate changes from 1 to 0.

In the recording head 20, the recording voltage of the group to which the gradation level of the image signal belongs is applied to the corresponding recording element only during the period when the recording time signal is logic 1. FIG. 8 shows a state of accumulation of effective energy when the gradation level of the image signal belongs to the group G3.

As described above, according to the present embodiment, instead of sequentially changing the recording voltage supplied to the recording element during the accumulation period, a combination of the recording voltage and the recording time of the group to which the gradation level of the image signal belongs is used. Alone, halftone recording can be performed.

In the second embodiment, the gate section 60 is provided between the shift register and the subtractor. However, the gate section 60 may be provided before the shift register.

In the above description, a method in which all bits of the counter value are input to the recording time table to extract the recording time Ti is exemplified. However, as shown in FIG. 9, only the lower bits of the counter are input to the recording time table. May be configured to take out the corresponding recording time. As shown in FIG. 2, since the same numerical value is repeated for the lower bits in a group unit, eight types of recording times T0 to T7 may be registered in correspondence with 000 to 111 in the case of 32 gradations. FIG. 10 shows the contents of the recording time tables of the groups G2 to G4 when the recording time is extracted only from the lower bits. In the case of group G1, T0 is white
Only T1 to T7. There are advantages such as a reduction in table capacity.

[0055]

As described in detail above, according to the present invention, a desired dynamic density is obtained by combining a recording voltage and a recording time, whereby a large dynamic range can be obtained, and the reproducibility of halftone can be improved. In addition, it is possible to provide an image recording apparatus and an image recording method that can reduce the types of recording voltages and can prevent an increase in circuit scale.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image recording apparatus according to a first embodiment of the present invention;

FIG. 2 is a state diagram in which 5-bit image signals are arranged in order of density and classified into 4 groups.

FIG. 3 is a diagram showing table contents of a recording time table according to the first embodiment;

FIG. 4 is a schematic diagram of effective energy by a combination of a recording voltage and a recording time according to the first embodiment.

FIG. 5 is a diagram showing a specific example of effective energy in the first embodiment.

FIG. 6 is a configuration diagram of an image recording apparatus according to a second embodiment of the present invention;

FIG. 7 is a circuit diagram of a gate unit in Embodiment 2.

FIG. 8 is a schematic diagram of effective energy by a combination of a recording voltage and a recording time according to the second embodiment.

FIG. 9 is a diagram showing input bits of a recording time table according to a modification.

10 is a diagram showing table contents of a recording time table shown in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Control part 11-13 Register 14-16 Subtractor 17-19 AND gate 20 Recording head 21 Counter 22 Recording voltage generation part 23 Recording time table 24 Recording time timer 60 Gate part

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C066 CD01 CD04 CD06 CD14 CD16 5C051 AA02 CA01 DE03 EA02 5C074 AA05 BB12 CC26 DD03 DD07 DD08 DD11 DD16 EE06 FF05

Claims (6)

[Claims] A recording element for performing recording at a density corresponding to a recording voltage and a recording time; a recording voltage varying means for changing the recording voltage in accordance with upper bits of an image signal; An image recording apparatus comprising: a recording time varying unit that varies the recording time according to a bit. 2. The recording voltage varying means arranges the gradation levels in the order of density, classifies the gradation levels into a plurality of groups by the upper bits of bit data representing each gradation level, and records the group to which the upper bits of the image signal belong. The image recording apparatus according to claim 1, wherein the apparatus generates a voltage. 3. A recording time varying means, comprising: a recording time table in which recording times for lower bits or all bits of bit data representing each gradation level are registered; and a recording time measuring the recording time taken out from the recording time table. 3. The image recording apparatus according to claim 1, further comprising a time timer. 4. A register for holding an image signal, a subtractor for latching the image signal held in the register and decrementing the gradation level of the image signal each time a time-over signal is input, and the subtractor A gate circuit that outputs a recording time signal of logic 1 until the gradation level of the image signal latched by the timer becomes 0 level, and a bit data representing the gradation level is input every time the time-over signal is input in order from 0 level. A counter for incrementing, a voltage generating means for changing a recording voltage in accordance with an upper bit of the counter, and a recording time for lower bits or all bits of bit data representing each gradation level are registered, and a recording time for lower bits or all bits of the counter is registered. The recording time table that outputs the recording time and the recording time that is output from this recording time table are counted. A recording time timer that outputs a time-over signal when the recording time reaches the recording time, and a recording voltage generated by the voltage generating means is a logical 1
And a recording element that performs halftone recording by being applied over a period of time. 5. The image recording apparatus according to claim 4, further comprising a gate for outputting a lower bit of the image signal when an upper bit of the image signal matches an upper bit of the counter. 6. A method of arranging gradation levels in order of density, classifying the gradation levels into a plurality of groups by higher bits of bit data representing each gradation level, and generating a recording voltage of a group to which the higher bits of the image signal belong. Taking the recording time corresponding to the lower bits or all bits of the image signal from the recording time table in which the recording time for the lower bits or all bits of the bit data representing each gradation level is registered,
An image recording method, wherein halftone recording is performed by combining the extracted recording time and the recording voltage.