JP2001061283A - Three-phase neutral clamped pwn inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the safety and the quality of the output voltage of a three-phase neutral clamped PWM inverter device by making the potential at the neutral point adjustable at over-modulating time, by compensating the phase output terminals of three phases out of eight switching states with six switching states except two switching states by simultaneously connecting the output terminals to a positive or negative bus. SOLUTION: The time of a three-phase output voltage at which six switching states in which a positive bus P, a negative bus N, and a neutral line O are respectively connected to phase output terminals of three phases 1 is suppressed to a first set value or lower. The deficiency of the output voltage of a three-phase neutral clamped inverter device caused by the suppression of the time can be compensated with six switching states except two switching states, by simultaneously connecting the phase output terminals of the three phases 1 to the positive or negative bus P or N out of the eight switching states, in which each of the phase output terminals is connected to the positive or negative bus P or N. Therefore, the safety and the quality of the output voltage of the inverter device can be improved, because the fluctuation of the neutral potential can be suppressed and, in addition, the neutral potential can be adjusted at over-modulating time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device such as an inverter and a servo drive for driving a motor at a variable speed, and a power conversion device for system interconnection.

[0002]

2. Description of the Related Art Conventionally, a PWM pulse generating method for a three-phase neutral point clamp type PWM inverter device is disclosed in
The generation time of each vector is calculated using the unipolar modulation / dipolar modulation that outputs a pulse by comparing an amplitude command and a carrier as shown in -146160 or the concept of a space vector as disclosed in Japanese Patent Application Laid-Open No. 5-292754. PW
There is a method of generating M pulses. FIG. 10 is a vector diagram showing the output voltage vector of the three-phase neutral point clamp type PWM inverter on a plane. Three-phase neutral point clamp type PW
The state of the switch whose phase output terminal of the M inverter is connected to the positive bus is P, the state of the switch connected to the negative bus is N, the state of the switch connected to the neutral line is O, and the UV of the output phase is
If arranged in the order of W, the output voltage vector that can be taken by the three-phase neutral point clamp type inverter has 27 kinds of switch states as shown in FIG.

Here, for convenience of explanation, 27 kinds of switch states that can be taken by the three-phase neutral point clamp type PWM inverter shown in FIG. 10 are described as zero vector PPP: Op OOO: Oo NNN: Onx vector POO, OPO, OOP : Xp ONN, NON, NNO: xny vector PPO, OPP, POP: yp OON, NOO, ONO: yn vector PON, OPN, NPO, NOP, ONP: za vector PNN, NPN, NNP: ab vector PPN , NPP, PNP: b, and the area surrounded by the zero vector, the x vector, and the y vector is 1-1 to 6-1. The area surrounded by the x vector, the a vector, and the z vector is 1-2. 6-2 The area surrounded by the x vector, y vector, and z vector is defined as 1-3 to 6-3 y vector, b vector, Partitioning the area surrounded by the vector as 1-4～6-4. In order for the three-phase neutral point clamp type PWM inverter to output a certain voltage vector A in the area shown in FIG. 10, the vectors of the switch state closest to the tip of the voltage vector are used, and these vectors are sequentially converted. Pulse width modulation (PW) so that the composite value of the vector within a certain unit time is the same as the voltage vector A.
M) to obtain an output voltage.

[0004]

In a three-phase neutral point clamp type PWM inverter, smoothing capacitors 3 and 4 are provided between a main circuit positive bus P and a negative bus N in order to generate a neutral point voltage as shown in FIG. In general, even numbers are connected in series, and a neutral wire is taken out from a terminal 0 of a capacitor having a voltage exactly intermediate between the positive bus P and the negative bus N and used. 9, 1 is a three-phase AC power supply, 2 is a rectifier diode bridge,
6 to 11 are clamp diodes, 12 to 23 are freewheeling diodes, 24 to 35 are IGBTs, 36 to 38 are current sensors, and 39 is a load motor. The neutral line 0 is PWM
Connection is made as shown in FIGS. 7 and 8 depending on the inverter output load (load motor 39) and the state of the switches of the PWM inverter. The potential of the neutral line (neutral point potential) varies depending on the current for charging the capacitor from the positive and negative buses and the current from the connected load. In the switch state shown in FIG. 7, the line voltage output to the load is the same, but the phase of the load connected to the neutral line is different. ), The neutral point potential can be finely controlled by adjusting the time ratio at which this set of switch states is generated. However, in the switch state shown in FIG. 8, the neutral point potential fluctuates depending on the phase current of the load connected to the neutral line and the time ratio at which the switch state is generated, and the switch state for completely correcting the neutral point potential is changed. Since they do not exist, the neutral potential fluctuations caused by the switch state of FIG. 8 must be corrected using the switch state of FIG.

Therefore, conventionally, as shown in Japanese Patent Application Laid-Open No. 2-261630, a zero-phase voltage is applied to the modulation factor to adjust the generation time of the set of switch states shown in FIG. Neutral point potential fluctuation is controlled without changing the output voltage during the period. Also, a voltage vector to be output is output using a set of switch states shown in FIG. 7 in a space vector manner, and a neutral point potential is controlled by adjusting the generation time of the switch states of the set. I was
In the three-phase neutral point clamp PWM inverter, the neutral point potential fluctuation in the switch state of FIG. 8 is determined by the phase current of the load connected to the neutral line from FIG. FIG. 11 shows the phase current of the load connected to the neutral line (when the load power factor = 1). As for the direction of the phase current 110 of the load connected to the neutral line, the output voltage vector changes by 120 degrees. In this case, the neutral point potential fluctuates at a frequency three times the output frequency. Further, when the modulation rate is considerably large, the occurrence time ratio of the switch state shown in FIG. 8 becomes larger than that in the switch state shown in FIG. 7, and in the overmodulation state where the modulation rate exceeds about 1.15, FIG.
8 has become completely zero, and there has been a problem that the fluctuation of the neutral point potential caused by the switch state shown in FIG. 8 cannot be suppressed.
Therefore, the problem to be solved by the present invention is to suppress the neutral point potential fluctuation of the three-phase neutral point clamp type PWM inverter device and to adjust the neutral point potential at the time of overmodulation, which was impossible in the past. It is intended to improve safety and output voltage quality.

[0006]

In order to solve the above-mentioned problems, the present invention provides: (1) a positive bus, a negative bus, and a neutral wire, wherein the positive bus, the phase voltage output terminal, and the negative bus are provided; A first and a second switch element, and a third and a fourth switch element are connected in series between the bus and the phase output terminal, respectively, and a connection point between the first and the second switch elements; In a three-phase neutral point clamp type PWM inverter provided with three neutral point clamp type PWM inverters each having a connection point of the third and fourth switch elements connected to the neutral line via a clamp element for three phases. , The positive bus, the negative bus, and the neutral conductor are each connected to the three-phase output terminal of three phases, and suppress the time of the three-phase output voltage to be equal to or less than the first set value, Suppressed below the first set value. The three output terminals of the three phases are simultaneously selected from the eight switch states in which each of the three phase output terminals is connected to the positive bus or the negative bus. A three-phase neutral point-clamped PWM inverter device characterized in that six switch states are supplemented except for two switch states connected to the positive bus or the negative bus.

(2) In the three-phase neutral point clamp type PWM inverter device of (1), the six switch states suppressed to be equal to or less than the first set value compensate for the shortage of the output voltage. A three-phase neutral point-clamped PWM inverter device characterized in that the switch state of only one phase of the neutral point-clamped PWM inverter changes at the time of transition to two switch states. (3) In the three-phase neutral point-clamped PWM inverter device according to (1) or (2), the first set value is changed depending on a value of a modulation factor. It is assumed to be a PWM inverter device. (4) In the three-phase neutral point-clamped PWM inverter device according to (1) or (2), the first set value is changed according to a direction of a current flowing through a neutral wire or a phase of an output current. -Phase neutral point clamp PWM
Inverter device. (5) In the three-phase neutral point clamp type PWM inverter device according to (1) or (2), the first set value is changed according to a voltage value of the neutral line. Neutral point clamp type PWM inverter device.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. 1 to 4 show the PWM of the present invention.
It is an example of an output pulse train. FIGS. 1 to 4 show that the PWM output cycle is 2 × T, the horizontal axis is time series, and pulses are output in order from left to right. In the examples shown in FIGS. 1 to 3, when the z vector is included in the three vectors close to the output voltage vector, the z vector can be moved by a change in the switch state of only one phase from the z vector, and the z vector can be moved. Also output a or b vectors not included in the three vectors. 1-3 to 6-3 region (FIG. 1) Example 1: yp → b → z → yn → xn → a → z → xp → y
p 1-2 to 6-2 region (FIG. 2) Example 2: xp → z → b → z → a → xn, xn → a → z →
b → z → xp Example 3: b → z → xp → a → xn, xn → a → xp → z
→ b 1-4 to 6-4 region (FIG. 3) Example 4: yp → b → z → a → z → yn, yn → z → a →
b → yp Example 5: yp → b → yn → z → a, a → z → yn → b →
yp Although not shown in the above example, the average value of the output voltage is the same as in the above example even in the reverse order of the above example (PWM pulses are output in order from right to left).

When a pulse train as described above is output, the generation time of each switch state is determined by setting the modulation rate of the output voltage vector to k (the radius of the inscribed circle of the hexagon in FIG. 10 is 1) and the angle to be one. The angle between the closest a-vector and θ is T, the period of the PWM output pulse is T, and the output time of the z-vector is T2.
In the 1-3 to 6-3 regions, the generation time (T0) of the zero vector is T0 = 0 and the generation time (T1) of the x vector is T1 = T {1-2ksin
θ} z vector generation time (T2) is T2 = T {2ksin (θ +
π / 3) -1} and an arbitrary value equal to or greater than zero The generation time (T3) of the y vector is T3 = T {1-2ksin
(π / 3−θ)} The generation time (T4) of the a vector is T4 = [T {2ksin (θ +
π / 3) -1} −T2] / 2 The generation time (T5) of the b vector is T5 = [T {2ksin (θ ′ +
π / 3) -1} -T2] / 2 In the 1-2-2-6-2 region, the generation time (T0) of the zero vector is T0 = 0 and the generation time (T1) of the x vector is T1 = T {1-ksin ( θ
+ Π / 3)} The generation time (T2) of the z vector is T2 = 2 Any value equal to or less than Tksinθ and not less than zero The generation time (T3) of the y vector is T3 = 0 The generation time (T4) of the a vector is T4 = T (3 ^1/2 kcosθ
-1) -T2 / 2 The generation time (T5) of the b vector is T5 = (2Tksinθ-T
2) / 2 In the 1-4 to 6-4 region, the generation time (T0) of the zero vector is T0 = 0, the generation time (T1) of the x vector is T1 = 0, and the generation time (T2) of the z vector is T2 = 2Tksin ( π / 3−
θ) Any value equal to or less than zero and equal to or greater than zero The generation time (T3) of the y vector is T3 = 2T {1-ksin
(θ + π / 3)} The generation time (T4) of the a vector is T4 = {2ksin (π / 3−
θ) −T2} / 2 b Vector generation time (T5) is T5 = T (3 ^1/2 kcos
(π / 3-θ) -1) -T2 / 2.

Further, in the 1-3 to 6-3 regions, Example 6: yp → xp → z → a → xn → yn, yn → a →
z → x → yp Example 7: xp → yp → b → z → yn → xn, xn → yn
→ z → b → yp → xp It is possible to take a pattern as shown in FIG. 4. In this case, the generation time of each switch state is as follows: yp → xp → z → a → xn → yn Zero vector generation The time (T0) is T0 = 0 The generation time (T1) of the x vector is T1 = T {2−3ksinθ
-3 ^1/2 kcosθ} + T2 z vector generation time (T2) is T2 = {2ksin (θ + π /
3) Any value less than or equal to zero and greater than or equal to zero The generation time (T3) of the y vector is T3 = T {2ksinθ}-
T2 a vector generation time (T4) is T4 = T {3 ^1/2 kcosθ
+ Ksinθ-1} -T2 xp → yp → b → z → bn → xn when zero vector generation time (T0) is T0 = 0 x vector generation time (T1) is T1 = T {3 ^1/2 kcosθ
−ksin θ} −T2 The generation time (T2) of the z vector is T2 = {2ksin (θ + π /
3) Any value equal to or less than −1} and equal to or greater than zero The generation time (T3) of the y vector is T3 = T {2−2 · 3 ^1/2 k
cosθ} + T2 The generation time (T5) of the b vector is T5 = T {ksinθ + 3
^1/2 kcos θ-1} -T2.

With the above-described PWM output pulse train, the generation time (T2) of the z vector shown in FIG. 8 can be determined to be an arbitrary value equal to or greater than zero. The fluctuation of the neutral point potential can be suppressed, and when the modulation rate is large (when the generation time of the x and y vectors is short), the generation time of the z vector that fluctuates the neutral point potential can be shortened. It is possible to suppress the neutral point potential fluctuation which fluctuates three times. Also,
If the PWM pulse train of the present invention as described above is used, PWM
Since only one phase of the switch state changes at the time of the pulse transition, the fluctuation range of the output line voltage becomes substantially the same as the neutral point potential, and the load surge can be suppressed. Note that the above PWM
The pulse train is an example, and there are other pulse trains that satisfy the characteristics of the present invention. FIG. 5 is a block diagram showing an example of the present invention. In the figure, 101 is a z-vector generation time calculator 1, 102 is a z-vector generation time upper limiter, 103
Is a PWM generation time calculator, 104 is a vector generation time setting device, and 105 is a PWM pattern generator. Since the generation time of the z vector varies greatly depending on the modulation rate,
When the modulation rate is small and the time for generating the z vector is small,
When the generation time of the z vector is further shortened, the generation time of both the z vector and the a or b vector output to supplement the z vector becomes very small, and if the response of the switch element is slow, a correct pulse is not output. The output voltage may be insufficient. Therefore, as shown in FIG. 5, a z-vector generation time calculator 1 (101) for changing the set value of T2 according to the modulation rate is added.
Is optimized so that the generation of each of the z, a, and b vectors is adjusted so as not to be too short, so that the output voltage does not become insufficient.

FIG. 6 is a block diagram showing an example of the present invention. In the figure, reference numeral 106 denotes a z vector generation time calculator 2.
The direction in which the neutral point potential fluctuates when the z vector is generated is determined by the direction of the load current of the phase connected to the neutral line. When a current flows into the neutral line, the neutral point potential increases and the current Flows out, the neutral potential decreases. The current sensor 3 shown in FIG. 9 is used to determine the modulation rate and phase of the voltage vector and the direction of the phase current of the load connected to the neutral line using a circuit having the configuration shown in FIG.
6, 37 and 38, and the time setting of T2 is calculated by the z vector generation time calculator 2 (106) according to the current direction and the neutral point potential control command.

When the neutral point potential control command is (1) a command to increase the neutral point potential, when the current flows into the neutral line from the switch state and the phase current state, the generation time ratio of the z vector is increased. Otherwise, the generation time ratio of the z vector is reduced. (2) In the case of a command to lower the neutral point potential, when the current flows into the neutral line from the switch state and the phase current state, the generation time ratio of the z vector is increased. Decrease the ratio. (3) In the case of a command to hold the neutral point potential, the generation time ratio of the z vector is set to a constant value. By doing as described above, the neutral point potential can be adjusted to a desired potential. In a state of overmodulation in which the modulation factor exceeds 1, the generation time of the x and y vectors that can adjust the neutral point potential, which has been conventionally used, is almost eliminated, and the neutral point potential cannot be adjusted. FIG. 6
By adjusting the generation time of the z-vector with the circuit configuration shown in FIG. 1, the neutral point potential can be adjusted even during overmodulation.

[0014]

As described above, according to the present invention, 3
Neutral point potential fluctuation of the phase neutral point clamp type PWM inverter device is suppressed, and the neutral point potential at the time of overmodulation, which was impossible in the past, can be adjusted, thereby improving safety and improving output voltage quality. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a time chart showing an example of a PWM pulse pattern according to the present invention.

FIG. 2 is a time chart showing an example of a PWM pulse pattern according to the present invention.

FIG. 3 is a time chart showing an example of a PWM pulse pattern according to the present invention.

FIG. 4 is a time chart showing an example of a PWM pulse pattern according to the present invention.

FIG. 5 is a block diagram illustrating an example of a PWM pulse generation circuit according to the present invention.

FIG. 6 is a block diagram illustrating an example of a PWM pulse generation circuit according to the present invention.

FIG. 7 is an explanatory diagram showing a connection state with a load in a switch state 1 of the three-phase neutral point clamp inverter.

FIG. 8 is an explanatory diagram showing a connection state with a load in a switch state 2 of the three-phase neutral point clamp inverter.

FIG. 9 is a circuit configuration diagram of a three-phase neutral point clamp inverter.

FIG. 10 is an output voltage space vector diagram of a three-phase neutral point clamp inverter.

FIG. 11 is a diagram of a current flowing through a neutral wire (load power factor = 1).
It is.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 three-phase AC power supply 2 rectifier diode bridge 3, 4 smoothing capacitor 6 to 11 clamp diode 12 to 23 freewheeling diode 24 to 35 IGBT 36 to 38 current sensor 39 load motor 101 z vector generation time calculator 1 102 z vector generation time upper limit Setter 103 PWM generation time calculator 104 Each vector generation time calculator 105 PWM pattern generator 106 z vector generation time calculator 2 107 U-phase current 108 V-phase current 109 W-phase current 110 Current

Claims (5)

[Claims] A first and a second switch element between the positive bus and the phase voltage output terminal and between the negative bus and the phase output terminal; and A third and fourth switch element are connected in series, and a connection point between the first and second switch elements and a connection point between the third and fourth switch elements are respectively connected to the middle through clamp elements. In a three-phase neutral point clamp type PWM inverter provided with three neutral point clamp type PWM inverters connected to a neutral line, the positive bus, the negative bus, and the neutral line each have three phases. The time of the three-phase output voltage in the six switch states connected to the output terminal is suppressed to a first set value or less, and the shortage of the output voltage due to being suppressed to the first set value or less is calculated as follows: Each of the three phase output terminals Of the eight switch states connected to the positive bus or the negative bus, six switch states excluding two switch states where three of the three phase output terminals are simultaneously connected to the positive bus or the negative bus. A three-phase neutral point clamp type PWM inverter device characterized by supplementing. 2. The three-phase neutral point clamp type PWM according to claim 1.
In the inverter device, when shifting from the six switch states suppressed to be equal to or less than the first set value to the six switch states that compensate for the shortage of the output voltage, one phase of the neutral point clamp type PWM inverter is used. The three-phase neutral point clamp type P characterized in that only the switch state changes.
WM inverter device. 3. The three-phase neutral point clamp type PWM inverter device according to claim 1, wherein the first set value is changed according to a value of a modulation factor. Formula PWM inverter device. 4. The three-phase neutral point clamp type PWM inverter device according to claim 1, wherein the first set value is changed according to a direction of a current flowing through a neutral line or a phase of an output current. A three-phase neutral point clamped PWM inverter device. 5. The three-phase neutral point clamp type PWM inverter device according to claim 1, wherein the first set value is changed in accordance with a voltage value of the neutral line. Phase neutral point clamp type PWM inverter device.