JP2001060942A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost, to eliminate the adverse influence of mix modulation and to satisfactorily read data from each of digital signals without the need of plural PLL circuits corresponding to the respective digital signals even if the plural digital signals of the same format in a synchronized state are simultaneously transmitted/received, for example. SOLUTION: Word sync detection circuit 4 and 14 detect word sync from each digital signal. A reference clock generation circuit 6 generates the reference clock of a frequency which is sufficiently higher than the transmission bit rate of each of the digital signals. Bit reading clock generation circuits 5 and 15 generate the bit reading clocks of the digital signals based on the word sync of the digital signals and the reference clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus for receiving and processing at least a digital signal to be subjected to digital communication, such as a digital audio signal and a digital video signal.

[0002]

2. Description of the Related Art Conventionally, when a digital signal such as a digital audio signal or a digital video signal is transmitted, a synchronizing signal serving as a reference timing for processing the received digital signal in a receiving device is a digital signal. Sent with

FIG. 10 shows 16-bit digital data D
1 shows an example of a digital signal consisting of T and a word sync which is a synchronization signal transmitted and received with the digital signal.
FIG. 10A shows a word sync, and FIG. 10B shows a digital signal. As shown in FIG. 10, 16-bit digital data d of a digital signal
t is transmitted and received in synchronization with the word sync switching timing.

[0004] The transmission and reception of digital signals is not limited to transmission and reception of only one digital signal, but also includes transmission and reception of a plurality of digital signals of the same format at the same time.

In FIGS. 11 to 13, for example, two digital signals of the same format are transmitted from two transmitting devices, and two digital signals of the same format are received and processed by one receiving device. An example of the system configuration in the case is shown.

In FIG. 11, a receiver 103 is provided with a synchronization signal generation circuit 104. In this receiver 103, the synchronization signal generated by the synchronization signal generation circuit 104 is transmitted to two transmitters 1
01 and 102, while each of the transmitters 101 and 102 generates a word sync based on the synchronization signal supplied from the receiver 103, and outputs a digital signal and a word sync of the same format to the receiver 103, respectively. 1 shows an example of a system configuration in which transmission is performed to a user.

In the case of FIG. 11, the receiver 103 processes the digital signals transmitted from the transmitters 101 and 102 by the corresponding received signal processing circuits 105 and 108, respectively. Connect the processed signal to terminal 1
The data is transmitted from 09 and 110 to the subsequent configuration.

The receiver 103 further includes data read clock generation circuits 106 and 107 for generating a data read clock for reading the 16-bit digital data from the received digital signal in each of the received signal processing circuits 105 and 108. ing. That is,
In the data read clock generation circuits 106 and 107,
Based on the word sync transmitted together with the digital signal from each of the corresponding transmitters 101 and 102, a data read clock is generated, and the data read clock is sent to the corresponding reception signal processing circuits 105 and 108, respectively. Note that the data read clock generation circuit 106,
107 is a PLL (Phase-Lo
cked Loop) circuits 111 and 112.

Thus, each received signal processing circuit 105,
At 108, based on the data read clock,
16-bit digital data is read from the received digital signal, and predetermined processing is performed.

FIG. 12 shows two transmitters 121 and 122.
One of them (the transmitter 121 in the example of FIG. 12) includes a synchronization signal generation circuit 124, and the synchronization signal generation circuit 1
The synchronization signal generated by the transmitter 24 is sent to the other transmitter (the transmitter 122 in the example of FIG. 12), and the transmitters 121, 12
2 shows an example of a system configuration in which word syncs are respectively generated based on the synchronization signals, and a digital signal and a word sync having the same format are respectively transmitted to the receiver 123.

In the case of FIG. 12, the receiver 123 processes the digital signals transmitted from the transmitters 121 and 122 by the corresponding reception signal processing circuits 125 and 128, respectively. Connect the processed signal to terminal 1
The data is transmitted from 29 and 130 to the subsequent configuration.

The receiver 123 includes data read clock generating circuits 126 and 127 for generating a data read clock for reading the 16-bit digital data from the received digital signal in each of the received signal processing circuits 125 and 128. ing. The data read clock generating circuits 126 and 127 generate data read clocks based on the word syncs transmitted together with the digital signals from the corresponding transmitters 121 and 122, and generate the data read clocks with the corresponding received signal. It is sent to the processing circuits 125 and 128. The data read clock generation circuits 126, 1
27 is a PLL circuit 131,
132 is provided.

Thus, each received signal processing circuit 125,
At 128, based on the data read clock,
16-bit digital data is read from the received digital signal, and predetermined processing is performed.

FIG. 13 shows two transmitters 141 and 142.
An independent synchronizing signal generator 144 is provided on the side, and the synchronizing signal generated by the independent synchronizing signal generator 144 is sent to two transmitters 141 and 142.
Reference numerals 1 and 142 show system configuration examples in which word syncs are respectively generated based on the synchronization signals, and digital signals and word syncs having the same format are respectively transmitted to the receiver 123. Note that FIG.
In the case of 3, the configuration of the receiver 123 is the same as that of the example of FIG.

Here, the conventional system configuration example shown in FIGS. 11 to 13 has PLLs in data read clock generation circuits 106, 107, 126, and 127, respectively.
Circuits 111, 112, 131, and 132 are provided. That is, in the system configuration examples of FIGS. 11 to 13, although synchronization is established between the transmitting and receiving devices, the plurality of transmitting devices (ie, a plurality of digital signals to be received) are stored in the receiving device. A corresponding PLL circuit is required.

As described above, in spite of synchronization between the transmitting and receiving devices, PLL circuits respectively corresponding to a plurality of transmitting devices (a plurality of digital signals) are required in the receiving device. Even if a plurality of digital signals of the same format are transmitted in a synchronized state in a plurality of transmitting devices, for example, the state and length of the transmission path,
This is because there is a phase difference in each digital signal that has reached the receiving device depending on the type, characteristics, use conditions, and the like of each transmitting device. The phase difference may be a small value (for example, the phase difference is close to 0) or a large value depending on the state and length of the transmission path, the type and characteristics of each transmitting-side device, the use conditions, and the like. (For example, the phase difference is close to 360 degrees)
There are various cases.

FIG. 14 shows two digital signals DA and DB of the same format, which are transmitted in synchronization with the two transmitting devices A and B, respectively, when the digital signals reach the receiving device. DA and DB, and word syncs WA and WB of the digital signals DA and DB are shown. 14A and 14B show the word sync WA and the digital system signal DA transmitted from one transmitting device A and reaching the receiving device, respectively, and FIGS. d) shows a word sync WB and a digital system signal DB transmitted from another transmitting device B and reaching the receiving device.

As can be seen from FIG. 14, even if digital signals DA and DB of the same format are transmitted in a state where the two transmitting devices A and B are synchronized with each other,
At the time of reaching the receiving device, the digital DA, D
A phase difference φ occurs between B and the word syncs WA and WB.

As described above, even when a plurality of digital signals of the same format are transmitted in a synchronized state in a plurality of transmitting devices, there are various phase differences between the digital signals. In order to be able to read data from each digital signal having a phase difference of satisfactorily, the conventional system configuration includes PLL circuits respectively corresponding to a plurality of transmitting devices (a plurality of digital signals). I have to.

[0020]

As described above, the conventional system configuration example requires PLL circuits respectively corresponding to a plurality of transmitting devices (a plurality of digital signals) in a receiving device. As a result, the cost has risen.

Further, when a plurality of PLL circuits are arranged in the receiving side device, for example, intermodulation or the like occurs due to fluctuation of the oscillator of each PLL circuit, and the device performance is adversely affected.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and is intended for, for example, simultaneous transmission and reception of a plurality of digital signals of the same format in a synchronized state. Multiple P
Provided is a digital signal processing device which does not require an LL circuit, reduces costs, eliminates adverse effects such as cross modulation, and enables data to be read from each digital signal. With the goal.

[0023]

According to a first aspect of the present invention, there is provided a digital signal processing apparatus for receiving at least a plurality of digital signals having the same format and receiving each digital signal. In the digital signal processing device that respectively processes, the reference signal generating means for generating a reference signal of a frequency sufficiently higher than the transmission bit rate of the plurality of digital signals, and a synchronization signal and the reference signal of each of the plurality of digital signals Read clock generation means for generating a read clock for each digital signal based on the

According to a second aspect of the present invention, in order to solve the above-described problem, the reference signal generating means generates the preset reference signal.

According to a third aspect of the present invention, in the digital signal processing apparatus according to the present invention, in order to solve the above-mentioned problem, the reference signal generating means uses a synchronizing signal of one of the plurality of digital signals as a synchronizing signal. A clock having a frequency sufficiently higher than a transmission bit rate of the plurality of digital signals is generated.

According to a fourth aspect of the present invention, in the digital signal processing apparatus according to the present invention, in order to solve the above-mentioned problem, the read clock generating means outputs the read clock signal after a lapse of a predetermined time from the synchronization timing of the synchronization signal. Start generation.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a digital signal processing device according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a schematic configuration of a first embodiment to which the digital signal processing device of the present invention is applied. Note that the configuration of the first embodiment is applied to a receiving portion of a digital signal transceiver that transmits and receives digital signals, or a digital signal receiver that receives only transmitted digital signals.

FIG. 1 shows, for example, FIG.
1 to 13 show an example of a configuration in which two digital signals of the same format and a word sync transmitted from two transmission-side devices are received, but a first embodiment of the present invention is shown. Is applicable not only to receiving two digital signals and word syncs, but also to receiving more digital signals and word syncs.

In FIG. 1, an input terminal 1 has, for example, one of the transmitters (101, 12) shown in FIGS.
1, 141), and a digital signal and a word sync transmitted therefrom are supplied.

On the other hand, the input terminal 11 has, for example, the other transmitters (102, 122, 142) shown in FIGS.
The digital signal and the word sync transmitted from are input.

Hereinafter, the digital signal transmitted from the transmitter and received by the configuration of FIG. 1 is referred to as received digital data, and the received digital data and the corresponding word sync are collectively referred to as a received signal.

The reception signal from the input terminal 1 is input to the reception signal processing circuit 2 and the word sync detection circuit 4, and the reception signal from the input terminal 11 is input to the reception signal processing circuit 12 and the word sync detection circuit 14. .

The word sync detection circuit 4 detects a word sync from the signal received via the input terminal 1 and sends the word sync to the bit read clock generation circuit 5.

The word sync detecting circuit 14 detects a word sync from the received signal via the input terminal 11,
The word sync is used as a bit read clock generation circuit 1
Send to 5.

The reference clock generation circuit 6 generates a preset reference clock. The reference clock is
This clock has a frequency sufficiently higher than the transmission bit rate of the digital signal sent from the transmitter. The reference clock is used as the bit read clock generation circuits 5 and 15
Sent to

In the bit read clock generation circuit 5,
A bit for reading, for example, the aforementioned 16-bit received digital data bits from the received signal input to the input terminal 1 based on the word sync from the word sync detection circuit 4 and the reference clock from the reference clock generation circuit 6 Generate a read clock. More specifically, the bit read clock generation circuit 5 generates, as a bit read clock, a frequency-divided output obtained by dividing the reference clock by the frequency divider 8 (for example, 1/4 frequency in this embodiment). At the same time, the frequency divider reset device 7 resets the frequency division operation of the frequency divider 8 at the word sync switching timing, thereby generating a frequency divided output synchronized with the word sync, that is, a bit read clock synchronized with the word sync. I do. The bit read clock generated by the bit read clock generation circuit 5 is:
The signal is sent to the reception signal processing circuit 2.

Similarly, in the bit read clock generation circuit 15, based on the word sync from the word sync detection circuit 14 and the reference clock from the reference clock generation circuit 6, for example, 16 A bit read clock for reading the bits of the received digital data is generated. More specifically, the bit read clock generation circuit 15
Then, the reference clock is frequency-divided by the frequency divider 18 (for example, 1
(Divided by ／) is generated as a bit read clock, and the frequency divider reset unit 17 resets the frequency division operation of the frequency divider 18 at the word sync switching timing, thereby synchronizing with the word sync. The divided output, that is, the bit read clock synchronized with the word sync is generated. The bit read clock generated by the bit read clock generation circuit 15 is
The signal is sent to the reception signal processing circuit 12.

The reception signal processing circuit 2 reads 16 bits of the reception digital data from the reception digital signal input to the input terminal 1 based on the bit read clock generated by the bit read clock generation circuit 5, After performing the predetermined signal processing, the signal after the processing is transmitted from the terminal 3 to the subsequent configuration.

Similarly, in the reception signal processing circuit 12, based on the reception digital signal input to the input terminal 11, based on the bit read clock generated by the bit read clock generation circuit 15, the 16 bits of the reception digital data After performing the predetermined signal processing, the signal after the processing is transmitted from the terminal 13 to the subsequent configuration.

FIG. 2 shows the relationship between the word sync of the received signal and the received digital data, the reference clock generated by the reference clock generation circuit 6, and the bit read clocks generated by the bit read clock generation circuits 5 and 15. Is shown. In the configuration of the first embodiment shown in FIG.
The word sync shown in FIG. 2A and the received digital data shown in FIG. 2D are input to the input terminal 1, and the reference clock generation circuit 6 generates the reference clock shown in FIG. The bit read clock generation circuits 5 and 15 generate a bit read clock obtained by dividing (1/4 frequency) the reference clock.

In FIG. 2, a bit read clock is generated based on a word sync and a reference clock. According to the bit read clock, data is read at the center of the received digital data.

In FIG. 3, two digital data DA and DB of the same format which are transmitted in a synchronized state between the two transmitting devices A and B have the configuration of the first embodiment. Digital data DA and DB when reaching the receiving device, and the digital data DA and DB
Word syncs WA, WB and word syncs WA, W
B shows bit read clocks RA and RB generated by the reference clock. FIGS. 3A and 3D show a word sync WA and a digital system signal DA transmitted from one transmitting device A and reaching the receiving device, respectively. (H) shows a word sync WB and a digital system signal DB transmitted from another transmitting device B and reaching the receiving device. 3 (b) and 3 (f) show the same reference clock generated by the reference clock generation circuit 6, and FIG. 3 (c) shows the bit read clock generation circuit 5 using the word sync WA and the reference clock. FIG. 3G shows the generated bit read clock RA, and FIG. 3G shows the bit read clock RB generated from the word sync WB and the reference clock by the bit read clock generation circuit 15.

As can be seen from FIG. 3, even if digital data DA and DB of the same format are transmitted in a state where the two transmitting devices A and B are synchronized with each other,
At the time of reaching the receiving side device, a phase difference φ is generated between the received digital data DA and DB and the word syncs WA and WB.

In this case, in the conventional configuration, since the phase difference φ exists, each of the received digital data DA, DB
However, according to the configuration of the first embodiment of the present invention, the PLL circuit corresponding to the reference clock generated by the same reference clock generating circuit 6 and the received digital data DA and DB are used. Since the bit read clocks RA and RB of the received digital data DA and DB are generated based on the word syncs WA and WB, respectively, the received digital data DA and D as in the conventional example are generated.
Even without using each PLL circuit corresponding to B, it is possible to always generate a read clock suitable for each of the received digital data DA and DB shifted by the phase difference φ. Further, in the configuration of the first embodiment of the present invention, since two PLL circuits are not used unlike the conventional example, it is possible to eliminate adverse effects such as intermodulation due to fluctuations in the oscillator of the PLL circuit. I have.

FIG. 4 shows the bit read clock generation circuits 5 and 1 of FIG. 1 for generating a bit read clock based on the reference clock and the word sync as described above.
5 shows a specific configuration example. FIG. 5 shows signal waveforms at various parts in the configuration of FIG.

In FIG. 4, a terminal 21 receives a word sync signal as shown in FIG. 5A from the word sync detection circuit 4 or 14 of FIG. 1, and a terminal 22 generates a reference clock signal of FIG. A reference clock as shown in FIG. The word sync via the terminal 21 is input to a data input terminal of a D-type flip-flop (D-FF) 23. The reference clock via the terminal 22 is connected to the clock inverting input terminal of the D-type flip-flop 23 and the D-type flip-flop 2
4 and the input terminal of the counter 26.

In the D-type flip-flop 23, FIG.
As shown in FIGS. 5A and 5B, the word sync is latched at the falling edge of the reference clock, for example, and therefore, the data output terminal of the D-type flip-flop 23 is used as shown in FIG. Output can be obtained. The output from the data output terminal of the D-type flip-flop 23 is
4 data input terminal and one input terminal of a two-input NAND (exclusive OR) circuit 25.

In the D-type flip-flop 24, FIG.
By the falling of the reference clock shown in FIG.
The output shown in FIG. 5C from the type flip-flop 23 is latched. Therefore, an output as shown in FIG. 5D is obtained from the data inversion output terminal of the D-type flip-flop 24. Will be. The D
The output from the data inversion output terminal of the type flip-flop 24 is input to the other input terminal of the two-input NAND circuit 25.

In the two-input NAND circuit 25, the output from the data output terminal of the D-type flip-flop 23 shown in FIG. 5C and the data inversion of the D-type flip-flop 24 shown in FIG. Exclusive OR with the output from the output terminal. As a result, the two-input NA
From the output terminal of the ND circuit 25, as shown in FIG. 5 (e), a signal that goes low only when the outputs of the D-type flip-flops 23 and 23 both go high is output. become. The output signal of the two-input NAND circuit 25 is input to the load inverting input terminal of the counter 26.

The counter 26 is a 1/4 frequency dividing counter. When the load inverting input terminal goes low, the start position is determined, and the counter output value becomes the value set by the preset value setting unit 28. Is reset to the count value 1 at the time of occurrence. The counter 2
The count output of No. 6 is output from the terminal 27 as a bit read clock (1/4 frequency divided output) shown in FIG.

According to the configuration of FIG. 4, two-stage D-type flip-flops 23 and 24 and two-input NAND circuit 2
5, since the timing after a lapse of a predetermined time from the rise of the word sync is set as the count start position of the 1/4 frequency dividing counter 26, (f) and (g) of FIG.
As shown in (1), it is possible to always generate a read clock suitable for received digital data, and to read data at a substantially central portion where the received digital data is stable.

Next, FIG. 6 shows a schematic configuration of a second embodiment to which the digital signal processing device of the present invention is applied.

Note that the configuration of the second embodiment is also the first embodiment.
Similarly to the above embodiment, the present invention is applied to a receiving portion of a digital signal transceiver that transmits and receives digital signals, or to a digital signal receiver device that receives only transmitted digital signals.

FIG. 6 shows an example in which two digital signals and a word sync of the same format transmitted from two transmitting devices are received, as in the examples of FIGS. 11 to 13 described above. Shows a configuration example of
The second embodiment of the present invention is applicable not only to receiving two digital signals and word syncs but also to receiving more digital signals and word syncs.

In FIG. 6, for example, one of the transmitters (101, 12) shown in FIGS.
1, 141), and a digital signal and a word sync transmitted therefrom are supplied.

On the other hand, the input terminal 41 has, for example, the other transmitter (102, 122, 142) shown in FIGS.
The digital signal and the word sync transmitted from are input.

Hereinafter, the digital signal transmitted from the transmitter and received by the configuration of FIG. 6 is referred to as received digital data, and the received digital data and the corresponding word sync are collectively referred to as a received signal.

The reception signal from the input terminal 31 is input to the reception signal processing circuit 32 and the word sync detection circuit 34, and the reception signal from the input terminal 41 is input to the reception signal processing circuit 42 and the word sync detection circuit 44. .

The word sync detection circuit 34 is connected to the input terminal 3
The word sync is detected from the received signal via the first unit 1, and the word sync is sent to the bit read clock generation circuit 35 and also sent to the PLL clock generation circuit 36.

The word sync detection circuit 44 detects a word sync from the received signal via the input terminal 41,
The word sync is used as a bit read clock generation circuit 4
Send to 5.

The PLL clock generation circuit 36 generates a PLL clock having a frequency sufficiently higher than the transmission bit rate of the digital signal sent from the transmitter, based on the word sync supplied from the word sync detection circuit 34. The PLL clock is supplied to the bit read clock generation circuits 35 and 45.

In the bit read clock generation circuit 35, the word sync from the word sync detection circuit 34 and P
On the basis of the PLL clock from the LL clock generation circuit 36, a bit read clock for reading, for example, the aforementioned 16 bits of the received digital data from the received signal input to the input terminal 31 is generated. More specifically, the bit read clock generation circuit 35 generates a frequency divided output (for example, １ ／ frequency) of the PLL clock by the frequency divider 38 as a bit read clock, and resets the frequency division. The divider 37 resets the frequency division operation of the frequency divider 38 at the switching timing of the word sync, thereby generating a frequency-divided output synchronized with the word sync, that is, a bit read clock synchronized with the word sync. The bit read clock generated by the bit read clock generation circuit 35 is sent to the reception signal processing circuit 32.

Similarly, in the bit read clock generation circuit 45, based on the word sync from the word sync detection circuit 44 and the PLL clock from the PLL clock generation circuit 36, for example, the received signal input to the input terminal 41 is converted to 16 bits. A bit read clock for reading the bits of the received digital data is generated. More specifically, the bit read clock generation circuit 45 generates a frequency-divided output (eg, 1/4 frequency) of the PLL clock by the frequency divider 48 as a bit read clock, and resets the frequency division. The divider 47 resets the frequency division operation of the frequency divider 48 at the word sync switching timing, thereby generating a frequency-divided output synchronized with the word sync, that is, a bit read clock synchronized with the word sync. The bit read clock generated by the bit read clock generation circuit 45 is sent to the reception signal processing circuit 42.

In the reception signal processing circuit 32, the input terminal 31
After reading the 16-bit received digital data bits based on the bit read clock generated by the bit read clock generation circuit 35 from the received digital signal input to and performing predetermined signal processing, The signal is transmitted from the terminal 33 to the subsequent configuration.

Similarly, in the reception signal processing circuit 42, based on the reception digital signal input to the input terminal 41, based on the bit read clock generated by the bit read clock generation circuit 45, the 16 bits of the reception digital data After performing the predetermined signal processing, the signal after the processing is transmitted from the terminal 43 to the subsequent configuration.

FIG. 7 shows the relationship between the word sync of the received signal and the received digital data, the PLL clock generated by the PLL clock generation circuit 36, and the bit read clock generated by the bit read clock generation circuits 35 and 45. Is shown. In the configuration of the second embodiment shown in FIG. 6, the word sync shown in FIG. 7A and the received digital data shown in FIG.
From the PLL clock generation circuit 36, P shown in FIG.
The LL clock is generated, and the bit read clock generation circuits 35 and 45 generate a bit read clock obtained by dividing the frequency of the PLL clock (1/4 frequency division).

In FIG. 7, the bit read clock is generated based on the word sync and the PLL clock. According to the bit read clock, data is read at the center of the received digital data.

In FIG. 8, two digital data DA and DB of the same format transmitted in a state where the two devices A and B are synchronized with each other have the configuration of the second embodiment. Digital data DA and DB when reaching the receiving device, and the digital data DA and DB
Word syncs WA, WB and word syncs WA, W
B shows bit read clocks RA and RB generated by the PLL clock. It should be noted that FIG.
8 (d) show the word sync WA and the digital system signal DA transmitted from one transmitting device A and reaching the receiving device, and FIGS. 8 (e) and 8 (h) show the other. FIG. 5 shows a word sync WB and a digital system signal DB transmitted from one transmitting device B and reaching the receiving device. 8 (b) and 8 (f) show the same PLL clock generated by the PLL clock generating circuit 36, and FIG. 8 (c) shows that the bit read clock generating circuit 35 uses the word sync WA and the PLL clock from the word sync WA and the PLL clock. The bit read clock generation circuit 45 uses the generated bit read clock RA as a word sync WB in FIG.
And a bit read clock RB generated from the PLL clock.

As can be seen from FIG. 8, even if digital data DA and DB of the same format are transmitted in a state where the two transmitting devices A and B are synchronized with each other,
At the time of reaching the receiving side device, a phase difference φ is generated between the received digital data DA and DB and the word syncs WA and WB.

In this case, in the conventional configuration, since the phase difference φ exists, each of the received digital data DA, DB
However, according to the configuration of the second embodiment of the present invention, the same one PLL clock generation circuit 36 is provided with one of the word sinks WA and WB (the present embodiment). In the embodiment, the PLL clock generated from the word sync WA) and the received digital data DA, DB
The bit read clocks RA and RB of the received digital data DA and DB are generated based on the respective word sinks WA and WB corresponding to the two received digital data DA and DB. , It is possible to always generate a suitable read clock for each of the received digital data DA and DB shifted by the phase difference φ without using two PLL circuits corresponding to. In the configuration of the second embodiment of the present invention, two PLL circuits are not used unlike the conventional example.
It is possible to eliminate adverse effects such as intermodulation due to fluctuations in the oscillator of the PLL circuit.

As described above, a specific configuration example of the bit read clock generation circuits 35 and 45 of FIG. 6 for generating a bit read clock based on the PLL clock and the word sync is the same as that of FIG. Can be used.

However, in the case of the second embodiment, the PLL clock generation circuit 36 shown in FIG.
Is supplied.

Hereinafter, the configuration of FIG. 4 applied to the second embodiment will be described with reference to a waveform diagram shown in FIG.

In the configuration of FIG. 4 applied to the second embodiment, a word sync as shown in FIG. 10A from the word sync detection circuit 34 or 44 of FIG. The terminal 22 receives a signal from the PLL clock generation circuit 36 shown in FIG. 6 as shown in FIG.
The L clock is input.

In the D type flip-flop 23, FIG.
As shown in (a) and (b) of FIG. 10, the word sync is latched at the falling edge of the PLL clock, for example, and an output as shown in (c) of FIG. 10 is output from the data output terminal.

In the D-type flip-flop 24, FIG.
The output shown in FIG. 10C from the D-type flip-flop 23 is latched by the falling edge of the PLL clock shown in FIG. 10B, and the output shown in FIG. Output from terminal.

In the two-input NAND circuit 25, the exclusive OR of the output of the D-type flip-flop 23 shown in FIG. 10C and the output of the D-type flip-flop 24 shown in FIG. Take. As a result, the output terminal of the two-input NAND circuit 25 outputs the D-type flip-flop 23 as shown in FIG.
And 23 are output only when both of the outputs go high.

The counter 26 outputs a bit read clock (1/4 frequency divided output) shown in FIG.

In the configuration of FIG. 4 applied to the second embodiment, similarly to the first embodiment, as shown in FIGS. 10F and 10G, the received digital data Therefore, it is possible to always generate a suitable read clock, and it is possible to read data at a substantially central portion where received digital data is stable.

In the first and second embodiments of the present invention, the method of generating the bit read clock of the received digital data based on the word sync has been described as an example. However, the method is included in the received digital data itself, for example. In that case, it is also possible to generate based on it.

[0082]

According to the digital signal processing apparatus of the present invention, a reference signal having a frequency sufficiently higher than a transmission bit rate of a plurality of digital signals is generated, and a synchronization signal of each of the plurality of digital signals is generated. By generating a read clock for each digital signal based on the reference signal and the reference signal, for example, in the case of simultaneously transmitting and receiving a plurality of digital signals of the same format in a synchronized state, This eliminates the need for a plurality of PLL circuits, reduces costs, eliminates adverse effects such as cross modulation, and enables data to be read well from each digital signal.

According to the digital signal processing apparatus of the present invention, by generating the preset reference signal, for example, a plurality of digital signals of the same format in a synchronized state can be transmitted and received simultaneously. In such a case, a plurality of PLL circuits corresponding to the plurality of digital signals are not required, the cost can be reduced, and adverse effects such as cross modulation can be eliminated. It is possible to read data well.

According to the digital signal processing apparatus of the present invention, a clock having a frequency sufficiently higher than the transmission bit rate of the plurality of digital signals is obtained from the synchronization signal of one of the plurality of digital signals. By generating, for example, in the case of simultaneously transmitting and receiving a plurality of digital signals of the same format in a synchronized state, a plurality of PLL circuits corresponding to the plurality of digital signals are not required, and the cost is reduced. It is also possible to eliminate adverse effects such as cross-modulation, and it is possible to read data from each digital signal satisfactorily. According to the digital signal processing device of the present invention, by starting the generation of the read clock after a lapse of a predetermined time from the synchronization timing of the synchronization signal, data can be read from each digital signal satisfactorily. Is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment to which a digital signal processing device of the present invention is applied.

FIG. 2 is a waveform diagram showing signal waveforms of main parts of the configuration of the first embodiment of FIG.

FIG. 3 is a block diagram showing a configuration of the first embodiment shown in FIG. 1. Even when there is a phase difference between two received digital data, it is possible to always generate a suitable read clock for each received digital data. FIG. 4 is a waveform diagram used to explain what can be done.

FIG. 4 is a circuit diagram showing a specific configuration example of a bit read clock generation circuit in the configuration of the first and second embodiments.

FIG. 5 is a waveform diagram showing signal waveforms at various parts of the bit read clock generation circuit of FIG. 4 applied to the first embodiment.

FIG. 6 is a block diagram showing a schematic configuration of a second embodiment to which the digital signal processing device of the present invention is applied.

FIG. 7 is a waveform chart showing signal waveforms of main parts of the configuration of the second embodiment of FIG. 6;

FIG. 8 is a block diagram showing the configuration of the second embodiment shown in FIG. 6. Even when there is a phase difference between two received digital data, it is possible to always generate a suitable read clock for each received digital data. FIG. 4 is a waveform diagram used to explain what can be done.

FIG. 9 is a waveform chart showing signal waveforms at various parts of the bit read clock generation circuit of FIG. 4 applied to the second embodiment.

FIG. 10 is a waveform diagram showing an example of a digital signal composed of 16-bit digital data and a word sync which is a synchronization signal transmitted and received with the digital signal.

FIG. 11 is a block diagram showing a conventional system configuration example in which a synchronization signal is generated on the receiver side, supplied to the transmitter side, and each transmitter transmits a synchronized digital signal of the same format to the receiver. is there.

FIG. 12 is a block diagram showing an example of a conventional system configuration in which one transmitter generates a synchronization signal and sends it to the other transmitter side, and each transmitter transmits a synchronized digital signal of the same format to a receiver. FIG.

FIG. 13 shows an example of a conventional system configuration in which an independent synchronization signal generator generates a synchronization signal and sends it to each transmitter side, and each transmitter transmits a synchronized digital signal of the same format to a receiver. It is a block diagram.

FIG. 14 is a diagram used to explain an example in which even when two digital signals of the same format synchronized with each other are transmitted from two transmitters, there is a phase difference between the two digital signals when the digital signals arrive at the receiver. .

[Explanation of symbols]

2, 12, 32, 42 ... received signal processing circuit, 4, 14,
34, 44... Word sync detection circuit, 5, 15, 35,
45: bit read clock generation circuit, 6: reference clock generation circuit, 7, 17, 37, 47: frequency dividing reset device, 8, 18, 38, 48: frequency dividing device, 23, 24: D type flip-flop, 25 ... 2-input NAND circuit, 2
6 1/4 frequency dividing counter, 28 preset presetter, 3
6. PLL clock generation circuit

Claims (4)

[Claims] 1. A digital signal processing device for receiving at least a plurality of digital signals having the same format and processing each digital signal, wherein a reference signal having a frequency sufficiently higher than a transmission bit rate of the plurality of digital signals is generated. Digital signal processing, comprising: a reference signal generating means for generating a digital signal; and a read clock generating means for generating a read clock for each digital signal based on a synchronization signal of each of the plurality of digital signals and the reference signal. apparatus. 2. The digital signal processing apparatus according to claim 1, wherein said reference signal generating means generates the preset reference signal. 3. The method according to claim 1, wherein the reference signal generating unit calculates a synchronization signal of one of the plurality of digital signals.
2. The digital signal processing device according to claim 1, wherein a clock having a frequency sufficiently higher than a transmission bit rate of the plurality of digital signals is generated. 4. The read clock generating means according to claim 1, wherein the read clock generating means starts generating the read clock after a lapse of a predetermined time from the synchronization timing of the synchronization signal. The digital signal processing device according to the item.