JP2001057561A - Common buffer type packet shaper - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a common buffer type packet shaper means that can cope with a high-speed channel by decreasing a packet read time interval for each flow such as a quality class configured in a common buffer. SOLUTION: In the adderss management for a common buffer, a plurality of output sequence chains having a write adderss register 20 and a read adderss register 30 are assigned to each flow such as quality class. The shaper is provided with a distribution pointer 22 that cyclicly distributes a packet of a corresponding flow to a plurality of output sequence chains to attain pipeline reading through the use of a plurality of the output sequence chains, a write adderss register selection circuit 21, a read pointer 32 that conducts cyclic reading from a plurality of the output sequence chains and a read adderss register selection circuit 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a packet shaper for controlling the quality of a packet signal (cell) used in an asynchronous transfer mode (hereinafter referred to as ATM) and an IP packet.

[0002]

2. Description of the Related Art Packet signals such as ATM cells and IP packets are multiplexed and switched asynchronously on a network by switching. Therefore, when these packets pass through a multiplexer or a switch, delay fluctuation occurs due to a difference in waiting time in a buffering portion. Delay fluctuations cause problems such as a reduction in the use efficiency of network resources and a deterioration in the quality of services requiring fixed bandwidth. As a means for solving these problems, a shaping device has been devised.

FIG. 4 shows a configuration of a packet shaper device for shaping a fixed-length packet (called a cell in the case of ATM). The packet shaper device 70 includes a transmission line terminator 72 for terminating a physical layer signal input from the input transmission line 71, a packet shaper 130 for buffering a packet for each flow such as a destination, a quality class, or a connection. It has a read control unit 73 that performs control such as band control and priority reading for packets, and a transmission line output unit 75 that terminates the upper layer and performs physical layer signal processing to output to the output transmission line 74.

Further, when handling variable length packets,
In some cases, a fixed-length packet dividing unit and a variable-length packet reproducing unit are arranged at the front and rear stages of the packet shaper, respectively.

[0005] As a buffering method of the packet shaper, efficient buffering becomes possible by using a common buffer that uses a packet buffer commonly between flows.

[0006] A packet shaper using a common buffer is disclosed in Japanese Patent Application Laid-Open No. 7-95211, "Traffic Shaping Apparatus". In this configuration, a logical queue is formed for each VC (virtual channel) of ATM cells on a common buffer, and cell delay fluctuation is suppressed by adjusting the reading interval from each logical queue. In Japanese Patent Application Laid-Open No. Hei 7-240752, "A switching path setting method for an ATM switch", a shaping function using a common buffer is arranged before and after an ATM switch. In this configuration, a logical queue for each quality class is configured on the common buffer, and read control for each quality class is realized. Regarding the conventional common buffer used in the packet shaper, the detailed configuration of the memory address management required for realizing it is not described.

[0007]

A common buffer is used to configure a logical queue for a plurality of output routes, a logical queue for each quality class, etc., configured in a buffer memory in order to manage an address configuration for realizing the common queue. It takes a certain amount of time to update the output order chain. That is, when the common buffer is used, the continuous reading interval of packets from the same logical queue is limited not by the access speed of the memory used but by the update time of the output order chain. FIG. 2 shows a common buffer address management configuration when one logical queue is assigned to each flow. A packet input from the input line 10 is a write address register (WA) corresponding to a corresponding flow among n flows from the header of the packet output from the header extraction unit 12.
6 (any of 6-1 to 6-n) is selected by the flow decoder 4, and the packet write address is sent to the buffer memory 1 '. The packet that has passed through the header extraction unit 12 is
The data is written to the packet storage unit 1'-1 in the buffer memory 1 'specified by the write address register (WA) 6 (any one of 6-1 to 6-n). At this time, the empty address read from the empty address buffer 8 is stored in the address pointer storage area 1'-2 (the designated packet storage unit 1 ').
-1) and the selected write address register (WA) 6 (any one of 6-1 to 6-n). The read address of the packet read from the buffer memory 1 'at each read time is determined by the read address register (RA) 7 (any of 7-1 to 7-n) corresponding to the flow. Address register (R
A) 7-1 to 7-n are determined according to the read algorithm of the read control unit 9. At the same time when the packet is read from the specified address, the address pointer of the same address is written to the read address register (RA) (any of 7-1 to 7-n) specified by the read control unit 9. Then, the address of the buffer memory from which the packet has been read is written to the empty address buffer 8.

FIG. 3 shows an example of the configuration of an output order chain using address pointers. Output order chain 20-1 corresponding to flow 1 is read address register (RA1)
The write address register (WA1) 6-1 includes a start address stored in the write address register (WA1) 6-1 and an end address stored in the write address register (WA1) 6-1. An output order chain 20-2 corresponding to another flow 2 is used to determine the start address stored in the read address register (RA2) 7-2 and the end address stored in the write address register (WA2) 6-2. Is made up of The above is an example of realizing a logical queue for each flow in the same buffer memory by configuring an output order chain for each flow.

Next, the packet output time interval of each flow in the configuration of FIG. 2 will be described. FIG. 7 shows a case where one output order chain 50-1 is assigned to each flow.
In this example, after giving an address to the buffer memory 1 ',
It is assumed that three timings are required for outputting the packet data and the address pointer and updating the read address register. As an example, when an output order chain corresponding to the flow 1 is considered, the read address register (R
A1) With respect to the address A11 given at the time T1 from 7-1, the packet data D11 and the address pointer A
12 is output from the buffer memory 1 at time T4. The content of the read address register (RA1) 7-1 is updated to A12, and thereafter, at time T5, the address A1 is updated.
When 2 is given to the buffer memory 1, the next packet data D12 is output at time T8. That is, the output interval of the packet data is four timing cycles (50-2).
Becomes

As described above, when the common buffer is used, the interval for continuously reading packets from the same logical queue is limited not by the access speed of the memory used but by the update time of the output order chain. this is,
This means that the packet shaper device cannot support input / output lines equivalent to the memory access speed, and if it is placed before or after a switch, it cannot support high-speed input / output lines. This means that high-speed link connection with a large-capacity switch becomes impossible.

An object of the present invention is to provide a common buffer packet shaper capable of supporting a high-speed input / output line. More specifically, it is an object of the present invention to provide a buffer packet shaper capable of reading the same flow packet stored in a common buffer at a high speed.

[0012]

A plurality of output order chains are assigned to one flow (buffering unit) such as an output line or a quality class. The plurality of logical queues having the plurality of output order chains are pipelined. Specifically, a distribution pointer for cyclically distributing packets for each flow to a plurality of output order chains is provided. Further, a read pointer is provided for each flow for cyclically selecting an output chain and performing reading so that the order of packets does not reverse. Thereby, before the update of one output order chain is completed, the next output order chain can be accessed. As a result, the output time interval of packets belonging to each flow can be reduced, and a common buffer corresponding to high-speed reading can be realized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a high-speed line-compatible common buffer type packet shaper 13 having n queue buffers in flow units. Here, flow refers to quality class,
Indicates a group unit such as destination and connection. This packet shaper includes a buffer memory 1, a flow decoder 40, an output decoder 5, an empty address buffer 8, a header extractor 12, an input line 100, an output line 110, a write address register (WA) 20, a WA selection circuit 21, a distribution pointer. 22. Read address register (RA)
30, RA selection circuit 31, and read pointer 32
Having. The buffer memory 1 has a packet storage unit 1-1 and an address pointer storage area 1-2 having the same address.

From the packet input from the input line 100, a header for flow identification is extracted by a header extracting unit 12. The flow decoder 40 decodes the flow according to the header of the packet output from the header extraction unit 12. WA selection circuit 21 corresponding to the decoded flow
Indicates m write address registers (20-x-1 to 20-x-m, where x is 1) according to the distribution pointer 22.
To n) cyclically. For example, flow 1
, The write address register WA1m (20-1-m) is cyclically selected from the write address register WA11 (20-1-1) by the distribution pointer 22-1. Selected write address register 2
The address stored in “0” is transmitted to the buffer memory 1. Packets that have passed through the header extraction unit 12 are written to the write address registers 20 (20-1-1 to 20-nm).
) Is written to the packet storage unit 1-1 in the buffer memory 1 specified in (1). At this time, the empty address read from the empty address buffer 8 is stored in the address pointer storage area 1-2 having the same address as the specified packet storage unit 1-1, and the selected write address register (WA) 20 (20). -1-1 to 20-nm)
Is written to. With the above configuration, packets belonging to the same flow are cyclically written to the m output order chains.

Next, a packet reading operation will be described. The read address of the packet read from the buffer memory 1 at each read time is set to m read address registers (R) provided for each flow with respect to the flows (1 to n) specified by the read control unit 73.
A) Instructed by selecting one of 30 (30-x-1 to 30-x-m, where x is 1 to n). The read control unit 73 instructs a flow to be read by a predetermined read algorithm, such as priority class control and band control. Here, the read address register 3 for each flow
The selection of 0 is performed by the RA selection circuit 31 so that the order of the packets is not reversed. That is, the address register is designated by the read pointer 32 so that the cyclic selection in the same order as that of the paired write address registers 20 is performed. The packet output from the packet storage unit 1-1 is output to the output line 110. At the same time that the packet is read, an address pointer stored at the same address is written to a read address register (RA) 30 (any of 30-1-1 to 30-nm) specifying the address. The address of the buffer memory after the completion of the packet reading is written to the empty address buffer 8.

Next, FIG. 5 shows details of the distribution processing at the time of packet writing, which is a feature of the present invention.

The distribution pointer 22 is an m-ary counter 22
Has zero. When a packet addressed to the own flow is input, the enable signal (en
b) 400 is input to the distribution pointer 22, and the m-ary counter 220 counts up. WA selection circuit 21
Selects one of the m WAs 20 by decoding the counter value 222. With the above configuration, when a packet corresponding to the own flow is input, m WAs 20 are cyclically selected.

FIG. 6 shows details of the packet reading process. The read pointer 32 has an m-ary counter 320. When the output decoder 5 is notified of the output timing of its own flow, the enable signal (enb) 401
Is input to the read pointer 32, and the m-ary counter 320 counts up only when there is a read packet in the corresponding flow. Whether or not there is a read packet in the flow is notified by remaining packet information 323. The remaining packet information 323 is calculated from the number of input packets and the number of output packets for each flow. Alternatively, the determination can be made based on a match / mismatch between the WA 20 and the RA 30 in the output order chain. The RA selection circuit 31 decodes the counter value 322 output from the read pointer 32 and selects one of the m RAs 30. With the above configuration, m RAs 30 are cyclically selected for each output of a packet corresponding to the own flow. Furthermore, the reset pointers 221 and 321 are input to the distribution pointer 22 and the read pointer 32 at the time of initialization, and the respective counter values are reset to zero.

Next, using the time chart shown in FIG.
The effect of shortening the packet output time interval for each flow will be described. FIG. 8 is a time chart in the case where a plurality of (four in this example) output order chains 51-a to 51-d are assigned to each flow to perform a pipeline. FIG.
Assume that it takes three timings to provide an address to the buffer memory 1 and output the packet data and the address pointer and update the read address register in the same manner as in the above. As an example, consider an output order chain focusing on one of the n flows in FIG. For example, at time T1, the read address register (RA11)
For the address Aa1 given from 30-1-1, the packet data Da1 and the address pointer Aa2 are output at time T4 (51-a). At time T2, the packet data Db is stored in the address Ab1 given from the read address register (RA12) 30-1-2.
1 and the address pointer Ab2 are output at time T5 (51-b). As described above, before the update of one output order chain is completed, the address of another output order chain can be successively given to the buffer memory 1, so that the output interval of the packet data is one timing cycle (51 -2).

Next, how the packets of the same flow are sequentially stored in a plurality of output order chains by the distribution pointer 22 and then the packets stored by the read pointer 32 are sequentially selected and output will be described. FIG. 9 logically shows a configuration in which four output order chains are respectively assigned to two flows for each quality class to form a pipeline for simplicity. Quality class indication added to the header of each packet (H: high priority, L:
In accordance with the low-priority order, the output order chains 53H and 53L corresponding to the quality class (53H is a high-priority queue and 53L is a low-priority queue). Then, the corresponding distribution pointers 22H, 22L for each output order chain group
Is cyclically distributed to four output order chains. Specifically, the high priority packet A (52H
-1), D (52H-4) and E (52H-5) are distributed by the distribution pointer 22H, and the low-priority packets B (52L-2) and C (52L-3) are distributed by the distribution pointer 22L. . For reading, the read pointers 32H and 32L and the selector 250 for each output order chain group are driven in accordance with the instruction of the read control unit 73, and the order of storage in the packet buffer for each flow (in this example, quality class unit) is determined. Reading is performed to save. The example of FIG. 9 shows an example in which two classes of strict-priority read control (a high-priority packet is output with priority and a low-priority packet is output only when there is no high-priority packet) are performed. Depending on the configuration of the unit, band control and the like can be performed. Further, the pipeline processing of the common buffer address according to the present invention can be applied not only to each quality class but also to various flows such as a connection level and a packet level of an upper layer.

[0021]

According to the present invention, cells belonging to the same flow can be continuously read from the common buffer at high speed, and a packet shaper corresponding to a high-speed line can be realized.

[Brief description of the drawings]

FIG. 1 is a common buffer type packet shaper for high-speed input / output lines according to the invention.

FIG. 2 is a configuration example of a general common buffer type packet shaper.

FIG. 3 is an explanatory diagram of an output order chain of a general common buffer type packet shaper.

FIG. 4 is a configuration example of a conventional general packet shaper device.

FIG. 5 illustrates a common buffer distribution processing unit according to the present invention.

FIG. 6 is a diagram illustrating a common buffer read processing unit according to the present invention.

FIG. 7 is a packet output time chart of a common common buffer type packet shaper.

FIG. 8 is a packet output time chart of the common buffer type packet shaper of the present invention.

FIG. 9 is an example of an address management operation of a common buffer according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Buffer memory, 40 ... Flow decoder, 5 ... Output decoder, 8 ... Empty address buffer, 12 ... Header extraction part, 20 ... Write address (WA) register, 21 ... W
A selection circuit, 22 ... distribution pointer, 30 ... read address (RA) register, 31 ... RA selection circuit, 32 ...
Read pointer, 73: read control unit, 100: input line, 110: output line.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Mitsuhiro Wada, Inventor Hitachi, Ltd. Communication Systems Division, Totsuka-cho, Yokohama-shi, Kanagawa Prefecture, Japan (72) Inventor Hiroaki Kasahara 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Co., Ltd. Communication Systems Division, Hitachi, Ltd. (72) Noboru Endo, Inventor, 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term, Central Research Laboratory, Hitachi, Ltd. 5K030 GA01 HA08 JA06 KA03 LC02 LC14 LE14

Claims (6)

[Claims] 1. A packet input line, a packet output line, a buffer memory for storing a packet input from the packet input line, and a buffer memory corresponding to a flow of the input packet. And writing means for writing a packet at an address of the packet, and reading means for reading a packet stored by designating an address on the buffer memory corresponding to the flow of the packet. A packet shaper to which a plurality of output order chains are assigned. 2. A packet input line, a packet output line, a buffer memory for storing variable-length packets input from the packet input line by dividing them into fixed-length packets, There are writing means for writing a fixed-length packet at a corresponding address on the buffer memory, and reading means for reading a fixed-length packet stored by designating an address on the buffer memory corresponding to the flow of the fixed-length packet. A packet shaper wherein a plurality of output order chains are assigned to each flow of an input variable-length packet. 3. The packet shaper according to claim 1, wherein said writing means includes a distribution pointer for switching an address selector each time a packet arrives, and a selection circuit for cyclically selecting a write address. A packet shaper comprising: a read pointer for instructing switching of an address selector every time a packet is read; and a selection circuit for cyclically selecting a read address. 4. The packet shaper according to claim 3, wherein said distribution pointer and said read pointer are:
m-ary counter means (m is the number of the address management means assigned to each packet flow). The m-ary counter means counts up every time a packet belonging to the packet flow is read or written, The packet shaper, wherein the selection circuit decodes the value of the m-ary counter and cyclically selects the write or read address. 5. The packet shaper according to claim 1, wherein said read means performs selection control in the same order as said write means paired with said read means. . 6. The packet shaper according to claim 1, wherein said read means is assigned to a flow before updating of one output order chain assigned to the flow is completed. A packet shaper for accessing a next output order chain.