JPH0677984A - Cell read control system for atm switch - Google Patents

Abstract

PURPOSE:To enable read control at an ATM switch with one kind of LSI chips by distributedly arranging a memory for managing the arrival order of cells for each cross point. CONSTITUTION:The cells inputted through an input highway are successively stored in cell buffers 1-1...1-N in the order of arrival. Based on required information from an information transmission network 4 and the correspondent outputs of FIFO memories 2-1...2-N for managing the arrival order of cells, cell read control parts 3-1...3-N respectively read the cells from the cell buffers. Thus, since the FIFO memory for managing the arrival order of cells is distributedly provided for each cross point, cell read control at the ATM switch is enabled with one kind of LSI chips.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell read control system in a crosspoint buffer type ATM switch.

[0002]

2. Description of the Related Art In an ATM switch, information is disassembled for each cell and information is exchanged based on self-routing. FIG. 12 shows a cross-point buffer type as one of the configurations of the ATM switch. This FIG.
As shown in, the crosspoint buffer type ATM switch has a structure in which the buffer 40 is placed at the crosspoint between the input highway and the output highway. Such a crosspoint buffer configuration is a high-speed switch
It has the features of adaptability to large capacity, expandability, and good repeatability of LSI.

FIG. 13 is a block diagram showing a conventional cell read control system in an ATM switch using this crosspoint buffer structure. In FIG. 13, 4
, 41-N are write address filters, and write address filters 41-I
(I = 1 to N; N is a natural number), when a cell is sent on the corresponding input highway, the information in the header part of the cell is read and then the cell is transferred to the corresponding cell saving FIFO memory 42-I. While sending out, the number of the corresponding input highway is sent to the arrival order management FIFO memory 43.

The cell saving FIFO memory 42-I stores cells sent from the corresponding write address filter 41-I in the order of arrival, and outputs the highway according to the instruction of the corresponding read address address filter 45-I. The cells are sent out in the order of arrival. The arrival order management FIFO memory 43 stores the input highway numbers sent from the write address filter 41-I in the order of arrival, and outputs them in the order of arrival at a timing such that the output highway is not congested. The arrival order management FIFO memory 43 constitutes a multiplexing control unit 44.

Read Address Address Filter 45
-I indicates that if the input highway number output from the arrival order management FIFO memory 43 corresponds to the corresponding input highway, the corresponding cell saving FIFO memory 42-
It instructs I to read one cell. With such a configuration, the following operation is performed.

When a cell is sent on the corresponding input highway, the write address filter 41-I reads the information in the header portion of the cell and then sends the cell to the corresponding cell saving FIFO memory 42-I. Along with the corresponding input highway number, F for arrival sequence management
Send to IFO memory 43. FIFO memory 4 for saving cells
2-I is a corresponding write address filter 41-
The cells sent from I are stored in the order of arrival.

On the other hand, the arrival order management FIFO memory 43
Stores the input highway numbers in the order of arrival and outputs the input highway numbers in the order of arrival at a timing such that the output highways are not congested by the cells output from the cell saving FIFO memory 42-I. The read address filter 45-I is the arrival order management FIFO memory 4
If the input highway number output from 3 is that of the corresponding input highway, the corresponding cell saving FIFO
The memory 42-I is instructed to read one cell.
Then, the cell saving FIFO memory 42-I reads one cell in the order of arrival according to the instruction from the corresponding read address filter 45-I.

As described above, the arrival order management FIFO memory 43 is provided for each output highway, and the arrival order of cells is centrally managed in this memory so that the output highway becomes congested when the communication channel is congested. We try not to lose information.

[0009]

However, in such a conventional cell read control system in an ATM switch, the order of arrival of cells is centrally managed by one memory for each output highway. An LSI used as a memory for managing the arrival order and an L used as a buffer at a cross point of an input highway and an output highway.
Two types of LSI chips, SI, must be used.

The present invention was devised in view of such a problem, and by disposing the memory for managing the arrival order of cells at each cross point in a distributed manner, it can be realized by only one type of LSI chip. It is an object of the present invention to provide a cell read control method for an ATM switch.

[0011]

FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, 1-I (I = 1 to N) is a cell buffer, and the cell buffer 1-I is an input. It is provided at a cross point between an input highway and an output highway so that cells from the highway are output to the output highway, and the cells input through the input highway are accumulated in the cell arrival order.

2-I is a FIFO memory.
The FO memory 2-I manages the order of arrival of cells to the corresponding cell buffer 1-I. 3-I is a cell read control unit, and this cell read control unit 3-I reads a cell from the corresponding cell buffer 1-I based on the output from the corresponding FIFO memory 2-I.

Reference numeral 4 denotes an information transmission network. This information transmission network 4
Connects the cell read control units 3-I and transmits required information (claim 1). As the information transmission network 4, the cell read control units 3-I may be connected by a token transmission network (Claim 2), or the cell read control units 3-I may be connected from the forward path and the return path. You may make it connect by the following information transmission network (Claim 3).

[0014]

In the above-described cell read control method in the ATM switch of the present invention, cells input through the input highway are accumulated in the cell buffer 1-I in the order of arrival.
Further, the order of arrival of cells between each cell buffer 1-I is F
It is managed by the IFO memory 2-I. Cell read control unit 3-I
Is the required information transmitted by the information transmission network 4 connecting between the cell read control units 3-I and the corresponding FIFO memory 2-I.
The cell is read from the corresponding cell buffer 1-I based on the output from (1).

When the cell read control units 3-I are connected to each other by the token transfer network as the information transfer network 4, the tokens are circulated in the token transfer network, and the cell read control unit 3-I causes the tokens to circulate. If the output of the corresponding FIFO memory 2-I is in the state of no transmission cell when receiving the token, the token is sent to the next cell read control unit 3-I, while the corresponding F
If the output of the IFO memory 2-I is in a state where there is a transmission cell, the cell read control unit 3-I waits until the cell read from the cell buffer 1-I at the preceding stage is completed, While reading the cell of
The cell is read from the corresponding cell buffer 1-I by the cell read control unit 3-I by sending the token to the next cell read control unit 3-I (claim 2).

When each cell read control unit 3-I is connected as an information transmission network 4 by an information transmission network consisting of a forward path and a return path, the cell read control section serving as a master is connected to the information transmission network 4. The cell read control that receives the response signal when the response signal is sent back from the last cell read control section to the master cell read control section after sequentially transmitting the request signal to the last cell read control section. When the cell is not planned to be read by the section 3-I, the response signal is returned to the cell read control section closer to the master cell read control section while the cell read control section 3-I receives the response signal. When reading is started by this cell read control unit 3-I, when the reading is started by this cell read control unit 3-I, the response signal further becomes the master. Cell read control close to the cell read control section By returning to the parts side, perform cell read from the cell buffer 1-I corresponding by cell read controller 3-I (claim 3).

[0017]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment FIG. 2 is a block diagram showing a first embodiment of the present invention. In FIG. 2, 10-1, ..., 10-4 are write address filters. The write address filters 10-1, ..., 10-4 read the information in the header portion of the cell when the cell is sent on the input highway in every cell cycle, and then read the cell buffer into the corresponding cell buffer. , 11-4 are sent to the corresponding FIFO memories 12-1, ..., 12-4.

Cell buffers 11-1, ..., 11-4
Is a corresponding write address filter 10-1 ,.
.... The cells sent from 10-4 are stored in the order of arrival, and the corresponding read control units 13-1, ..., 13-4 are stored.
In accordance with this instruction, the stored cells are read in the order of arrival. FIFO memory 12-1, ..., 12-
4 is a corresponding write address filter 10-1,
.., 10-4 and "0", which are written when a cell is not sent, are stored in the order of arrival and the corresponding read control units 13-1 ,. 4, the stored signals of "1" or "0" are read out in the order of arrival.

Read control units 13-1, ..., 13-4
Corresponds to the corresponding FIFO memory 12-1, ..., 12-
Based on the signal of "1" or "0" read out from the No. 4 and the corresponding signals from the token control units 14-1, ..., 14-4, the corresponding cell buffers 11-1 ,.
., 11-4 to instruct cell reading. The token control units 14-1, ..., 14-4 are connected to each other by a token transmission network, and the token control units 14-1, ..., 14-4 circulate through the token transmission network once every one cell cycle.

Reference numeral 15 is a token monitoring unit, and this token monitoring unit 15 is for detecting duplication and loss of tokens and restoring them. In addition, the FIFO memory 12-i,
By the read control unit 13-i and the token control unit 14-i,
A multiplex control unit 16-i (i is 1, 2, 3, 4 and the same applies hereinafter) is configured (however, when i = 1, the token monitoring unit 15 is also included in the multiplex control unit 16-1). FIG. 3 shows a diagram for explaining the multiplex control unit 16-i in detail.

In FIG. 3, reference numerals 17 and 18 denote buffer circuits. As shown in FIG.
Is a wired-OR with other multiple control units
Has been done. As a result, when "1" is sent from the write address filter 10-i, it is F
While being written to the IFO memory 12-i, nothing is sent from the write address filter 10-i, and
In another multiplexing control unit, when "1" is written in the FIFO memory, "0" is written in the FIFO memory 12-i.

Next, FIG. 4 is a diagram for explaining the read control unit 13-i and the token control unit 14-i in detail. As shown in FIG. 4, the read control unit 13-i controls the control logic 1
9, FIFO read register 20, read enable register 21
The token control unit 14-i includes a token transmission unit 22 and a token reception unit 23. The control logic 19 uses the FIFO read register 20 to
A FIFO is sent by sending a read command to the IFO memory 12-i.
A signal of "1" or "0" is read from the memory 12-i, and the cell is read through the read enable register 21 based on the signal of "1" or "0" and the signal sent from the token receiving unit 23. When a signal indicating that cell reading has been started is received from the cell buffer 11-i while a read enable signal is transmitted to the buffer 11-i, the token transmitting unit 22 is instructed to transmit a token to the next stage.

The token sending unit 22 sends the token to the next stage in accordance with the instruction of the control logic 19, and the token receiving unit 23 sends the token to the control logic 19 when it receives the token from the previous stage. FIG. 5 shows a diagram for explaining the token transmission network. As shown by the arrow in FIG. 5, the token transmission network includes each token control unit 14-
1, ..., 14-4 are connected to each other, and the token makes a round in the direction of the arrow in the token transmission network for one cell cycle.

With the above structure, the following operation is performed. It will be described with reference to FIG. FIFO memory 12-
The input highways corresponding to 1, ..., 12-4 are # 1, ..., # 4, respectively. First cell period t ₀ ~
Between t ₁ and input highway # 1 and input highway # 2
Since the cells have arrived only in the first address, the write address filters 10-1 and 10-2 are set in the corresponding FIFO memory 1
"1" is written to 2-1 and 12-2, and the cell is sent to the corresponding cell buffers 11-1 and 11-2.
On the other hand, since no cell has arrived at the input highway # 3 and the input highway # 4, the corresponding FIFO memory 12
“0” is written in -3 and 12-4.

[0025] Then, between the cell cycle t ₁ ~t _2, t ₂ ~
between t _3, t ₃ as well between ~t _4, if the arriving cell to the input highway #i, address write filter 10
-I writes "1" to the FIFO memory 12-i and sends the cell to the cell buffer 11-i, while the cell does not arrive at the input highway #i and arrives at another input highway, “0” is written in the FIFO memory 12-i. The cell buffer 11-i stores the cells sent from the corresponding write address filter 10-i in the order of arrival and stores them in the FIFO memory 12-i.
For i, signals of "1" or "0" are stored in the order in which they were written.

As described above, the cell buffers 11-1,
The cells stored in 11-4 are read as follows. Token receiving unit 2 of token control unit 14-i
3 receives the token from the previous stage, and notifies the control logic 19 to that effect. The control logic 19 is a FIFO
"1" or "0" for each cell cycle from the memory 12-i
If the information read from the FIFO memory 12-i is “1” when the notification that the token has been received is received from the token receiving unit 23, the information is read via the read enable register 21. Cell buffer 11-
Send a readable signal to i. When the cell buffer 11-i receives the read enable signal, it starts reading the cell in the next cell cycle. However, if there is another cell buffer being read, the cell buffer 11-i waits for the end of reading and then reads the cell. To start.

The token is the token control unit 14-i.
When the control logic 19 sends a readable signal to the cell buffer 11-i in the immediately preceding cell cycle after it is received by the token receiving unit 23, and the cell reading is not yet started. Waits for the cell reading to be started, and then is sent from the token transmission unit 22 to the next stage according to the instruction of the control logic 19. In other cases, the control logic 19 outputs the token reception unit 23. Upon receiving the notification that the token has been received, the token transmission unit 22 is instructed to immediately send the token to the next stage.

By arranging the memories for managing the cell arrival order in a distributed manner for each crosspoint in this way, the cells input from the input highway as shown in FIG. Can be output to the output highway. When the token monitoring unit 15 detects duplication or loss of tokens, the token monitoring unit 15 restores these states to normal states.

FIG. 7 is a time chart showing the movement of the above-mentioned tokens in accordance with FIG. In FIG. 7, the movement of the token is indicated by a thick line. The reading from the FIFO memory 12-i is performed every one cell cycle.
It may be performed every time the token makes one round, or may be performed at the clock next to the token.

(B) Description of Second Embodiment FIG. 8 is a block diagram showing a second embodiment of the present invention. In FIG. 8, write address filters 10-1 ,.
..., 10-4, cell buffers 11-1, ..., 11
-4, FIFO memory 12-1, ..., 12-4, read control section 13-1, ..., 13-4 are the first shown in FIG.
Since it is similar to the embodiment, detailed description is omitted.

Reference numeral 30 denotes a master section, which outputs a REQ signal (request signal) in synchronization with the cell cycle. , 31-4 are communication units, and the communication units 31-1, ..., 31-4 are connected to each other by an information transmission network, and the REQ signal ( The request signal) and the END signal (response signal) are transmitted one after another.

The FIFO memory 12-i, the read control unit 13-i, and the communication unit 31-i allow the multiplexing control unit 32--.
i is configured (however, if i = 1, the master unit 3
0 is also included in the multiplex control unit 32-1). The multiplex control units 32-1, ..., 32-4 are similar to the multiplex control units 16-1, ..., 16-4 in the first embodiment.
Wired-OR each other.

Next, the read control unit 13-i and the communication unit 31-
FIG. 9 is a diagram illustrating i in detail. As shown in FIG. 9, the communication unit 31-i includes a logic 33 and a differentiating circuit 3.
4, AND circuit 35, NOT circuit 36. Note that, in FIG. 9, the control logic 19, the FIFO read register 20, and the read enable register 21 are the same as those in the first embodiment, so a detailed description will be omitted.

FIG. 10 is a diagram for explaining the information transmission network and the signal flow in the information transmission network in the second embodiment. As shown in FIG. 10, the REQ signals output from the master unit 30 are multiplexed control units 32-1, ..., 32-4.
, 31-4 are transmitted one after another,
When it reaches the last multiplex control unit, that is, the multiplex control unit 32-4, this time it becomes an END signal and the communication of each multiplex control unit 32-1, ..., 32-4 in the reverse order of the REQ signal. The parts 31-1, ..., 31-4 are transmitted one after another and returned to the master part 30.

With the above configuration, the following operation is performed. It will be described with reference to FIG. FIFO memory 12-
The input highways corresponding to 1, ..., 12-4 are # 1, ..., # 4, respectively. First cell period t ₀ ~
Between t ₁ and input highway # 1 and input highway # 2
Since the cells have arrived only in the first address, the write address filters 10-1 and 10-2 are set in the corresponding FIFO memory 1
"1" is written to 2-1 and 12-2, and the cell is sent to the corresponding cell buffers 11-1 and 11-2.
On the other hand, since no cell has arrived at the input highway # 3 and the input highway # 4, the corresponding FIFO memory 12
“0” is written in -3 and 12-4.

[0036] Then, between the cell cycle t ₁ ~t _2, t ₂ ~
between t _3, t ₃ as well between ~t _4, write address filter if arriving cell to the input highway #i 10-
i writes "1" to the FIFO memory 12-i and sends the cell to the cell buffer 11-i, while the cell does not arrive at the input highway #i and arrives at another input highway, the FIFO “0” is written in the memory 12-i. The cell buffer 11-i stores the cells sent from the corresponding write address filter 10-i in the order of arrival and stores them in the FIFO memory 12-i.
Stores a signal of "1" or "0" in the written order.

As described above, the cell buffers 11-1,
The cells stored in 11-4 are read as follows. First, the master unit 30 outputs a REQ signal in synchronization with the cell cycle. Communication unit 31- of multiplexing control unit 32-i
In i, immediately after receiving the REQ signal, the REQ signal is sent to the next multiplex control unit, and at the same time, the control logic 19 of the read control unit 13-i is notified that the REQ signal has been received. The control logic 19 uses the FIFO in the immediately preceding cell cycle.
If the value read from the memory 12-i is "1", a readable signal is sent to the cell buffer 11-i via the readable register 21. The cell buffer 11-i starts reading unless there is another cell buffer being read.

When the REQ signal reaches the last multiplex control unit, that is, the multiplex control unit 32-4, it becomes an END signal and R
Although it returns to the master unit 30 via the route opposite to the EQ signal, at that time, the multiplex control unit 32-i controls the control logic 1
9 outputs a readable signal to the cell buffer 11-i, and if the reading is not started, waits for the reading start of the cell buffer 11-i and then sends the END signal to the next multiplex control unit. Send, but otherwise E
Immediately after receiving the ND signal, the END signal is sent to the next multiplex control unit.

As described above, also in the case of the second embodiment, by disposing the memories for managing the arrival order of cells at each cross point in a distributed manner, only one type of LSI chip is used, as shown in FIG. The cells input from the input highway can be output to the output highway in the order of arrival. FIG. 11 is a time chart showing the movements of the REQ signal and the END signal described above in accordance with FIG. In FIG. 11, the thick line with the downward arrow is the REQ signal, and the thick line with the upward arrow is the END signal. Since the method shown in the second embodiment described above simplifies the procedure, it can operate at high speed.

(C) Others In any of the methods of the first and second embodiments, when the cell buffer is configured to be shared by a plurality of input highways, the FI for arrival order management is stored in the cell buffer.
This can be realized by providing as many input highways as FO memories.

[0041]

As described above in detail, according to the cell read control method in the ATM switch of the present invention, the FIFO memory for managing the arrival order of cells is distributed and arranged at each cross point, so that the cell arrival in the past can be achieved. Two types of LSI chips, one for order management and one for cell evacuation, were required, but now it can be realized with only one type of LSI chip.
This is very effective in reducing manufacturing costs.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a multiplexing controller in detail.

FIG. 4 is a block diagram illustrating in detail a read control unit and a token control unit.

FIG. 5 is a diagram illustrating a token transmission network.

FIG. 6 is a diagram illustrating an operation of a FIFO memory.

FIG. 7 is a time chart showing the movement of tokens.

FIG. 8 is a block diagram showing a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating in detail a read control unit and a communication unit.

FIG. 10 is a diagram illustrating an information transmission network and a signal flow.

FIG. 11 is a time chart showing the movement of the REQ signal and the END signal.

FIG. 12 is a diagram showing a crosspoint buffer type ATM switch.

FIG. 13 is a block diagram showing a conventional example.

[Explanation of symbols]

 1-I, 11-i cell buffer 2-I, 12-i FIFO memory 3-I cell read control unit 4 information transmission network 10-i, 41-I write address filter 13-i read control unit 14-i token Control unit 15 Token monitoring unit 16-i, 32-i, 44 Multiplexing control unit 17, 18 Buffer circuit 19 Control logic 20 FIFO read register 21 Readable register 22 Token transmission unit 23 Token reception unit 30 Master unit 31-i Communication unit 33 logic 34 differentiating circuit 35 AND circuit 36 NOT circuit 40 buffer 42-I cell saving FIFO memory 43 arrival sequence management FIFO memory 45-I read address filter

Claims (3)

[Claims] 1. At each cross point of a plurality of input highways and a plurality of output highways, in order to output cells from the input highways to the output highways, cells input through the input highways are accumulated in the order of cell arrival. A equipped with cell buffers (1-1, ..., 1-N)
In the TM switch, cell buffers (1-1,
..., 1-N), a FIFO memory (2-1, ...,) that manages the arrival order of cells to the cell buffers (1-1, ..., 1-N).
2-N) and corresponding cell buffers (1-1, ..., 2) based on outputs from the FIFO memories (2-1, ..., 2-N).
1-N) to read cells from the cell read control unit (3-1,
, 3-N), the cell read control units (3-1, ..., 3-N) are connected by an information transmission network (4), and the information of the information transmission network (4) is connected. , The cell read control unit (3-1, ...
., 3-N) for each cell buffer (1-1, ...,
1-N), cell reading from
Cell read control method in ATM switch. 2. Each cell read control unit (3-1, ..., 3)
-N) is connected by a token transmission network that circulates between them, and the token transmission network circulates the tokens so that when the cell read control unit (3-1, ..., 3-N) receives the token, Corresponding FIFO memory (2-1, ..., 2
-N) indicates that there is no cell to be sent, the token is sent to the next cell read controller while the corresponding FIFO is sent.
If the output of the memory is in the state where there is a transmission cell, the cell read control unit waits until the cell read from the cell buffer at the previous stage is completed, and the cell is read from the cell buffer and the token is read to the next cell. By sending the data to the control unit, the cell read control unit (3-1, ..., 3-N) reads the cell from each cell buffer (1-1, ..., 1-N). ATM according to claim 1, characterized in that
Cell read control method in switch. 3. Cell read control units (3-1, ..., 3)
-N) is connected by an information transmission network (4) consisting of a forward path and a return path, and the information transmission network (4) is made to sequentially transmit a request signal from the master cell read control section to the last cell read control section. Then, when returning the response signal from the last cell read control unit to the cell read control unit serving as the master, the cell read control units (3-1, ..., Receiving the response signal).
If there is no plan to read the cell in 3-N), the response signal is returned to the cell read control unit side closer to the master cell read control unit while the cell read control unit (3-1) which has received the response signal.・ ・ ・ ・ ・ ・
If the cell is to be read at (3-N), the cell read control section (3-1, ..., 3-N) waits until the reading is started and then the cell read control section (3 -1, ...
., 3-N), the response signal is returned to the cell read control unit side closer to the master cell read control unit so that the cell read control unit (3-1, ... , 3-N) performs cell reading from each cell buffer (1-1, ..., 1-N).