JP2965385B2 - Data cell transfer method in multibus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to high-speed data cell transfer in an electronic switching system or the like.

[0002]

2. Description of the Related Art A broadband ISDN (hereinafter simply referred to as "B-IS") for multimedia communication of image / audio data, etc.
A conventional STM communication method (Synchronou) is used as a communication method for realizing “DN” (abbreviated as Broadband ISDN).
It has been studied to adopt an ATM communication system (Asynchronous Transfer Mode) instead of the s Transfer Mode (synchronous transfer mode).

In such an ATM communication system, fixed-length blocks (data cells) with a label (header) for call identification are allocated according to a required amount. In B-ISDN, from 64 kbps of voice information, 140 Mbps to several G
It becomes a super multi-speed communication network that handles up to bps class image media information.

Here, in order to handle such information on the basis of the conventional STM, one time slot may be allocated to a call of 64 kbps, but 140 Mbp is assigned.
2000 times for s class calls
You must assign more than one. Therefore, when the B-ISDN is realized by the STM, it is necessary to provide a relay system for each speed in order to simplify the control.

[0005] On the other hand, in the ATM, information may be processed in a cell unit without depending on a medium and a speed.
One relay system is sufficient, and ATM is likely to be the core technology of B-ISDN.

[0006]

However, the existing C-
In device technology such as MOS, the above-described A
The conditions specified in TM and B-ISDN cannot be sufficiently satisfied.

For this reason, it is conceivable to use a high-speed device such as a GaAs or HEMT device. However, it is difficult to realize the device at present because of the degree of integration and cost. Therefore, there is a need for a technology for improving the transfer speed and processing speed of ATM cells using existing device technology.

[0008]

The present invention relates to a so-called AT.
As a processing system in M, as shown in FIG. 1 which is a principle diagram, the bus 1 is configured as a multi-bus configuration, each bus 1 is slotted in units of ATM data cells, and an input / output memory corresponding to the number of buses 1 is provided. And an interface unit 4 provided with the switching unit 3.
And the input / output between the input / output memory 2 and the bus 1 is controlled by shifting the phase of the bus slot between the buses by a fixed time.

[0009]

According to the present invention, on the bus transmitting side, output memories 2 for the number of buses are provided, and switching means 3 for distributing data cells transmitted from the outside to the output memories 2 in the order of arrival are provided.
A bus arbiter 5 is provided which adjusts transmission to the buses 1 according to the accumulation state of each output memory 2 when transferring to the bus 1.

On the receiving side, a similar switching means 3 corresponding to the transmitting side is used to control the order of arrival for each bus.
have. By adopting such a configuration and shifting the phase within one slot in each bus 1 (see FIG. 2), a plurality of bus connections can be made without being aware of the inversion of the order of the data cells. Therefore, the existing CM
The cell transfer speed and the cell processing speed can be drastically improved by the device technology such as the OS. For example, assuming that the transfer capacity per bus is n, according to the multi-bus transfer method of the present invention, if the phase division within one slot is possible by m, an n × m information transfer speed can be realized.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments.
FIG. 2 shows the phase relationship of the bus slots in the present embodiment. As shown in FIG. 2, in the present embodiment, the phases of the bus slots are shifted by a predetermined time in a plurality of buses 1, and the transmission and reception of these Is controlled by the transmission interface unit 4a and the reception interface unit 4b, thereby realizing high-speed data transfer on a so-called multi-bus.

In the following, for convenience of explanation, the case where two buses are used will be described, but the principle is the same even if there are three or more buses. FIG. 3 is a block diagram illustrating a device configuration according to the embodiment of the present invention.

In this embodiment, as an example, the bus 1 is composed of a pair (BUS-A, BUS-B), and the transmission interface unit 4a is provided with a pair of output memories 22a, 2a.
2b, a write control unit 8 arranged on the data input side, and a read control unit 9 arranged on the bus 1 side.

On the other hand, in the receiving interface unit 4b, a pair of input memories 3 provided similarly to the transmitting side is provided.
2a, 32b, a write control unit 8 arranged on the bus side,
A read control unit 9 disposed on the data output side. Note that the reception interface unit 4b is provided with a gate unit 10 for controlling the timing of capturing data.

A bus arbiter 5 is connected to the end of the bus 1 on the transmission side, and both buses (BUS-A, BUS-A) are connected.
-B). In the present embodiment, as shown in the operation sequence of FIG. 5, a frame pulse (FP) is used as a signal indicating the head of a data cell and the head of a bus slot.

First, as shown in FIG. 4, in the transmission-side interface unit 4a, the frame pulse (FP) is used to control which of the output memories 22a and 22b stores the external attachment data cell. And the output memories 22a and 22b are switched by inputting the frame pulse (FP) as a CELLCYN signal to the clock of the first flip-flop 7a (switching means 3).

External data is input to the first flip-flop 7a as data, and the output from the first flip-flop 7a is distributed to the first output memory 22a and the second output memory 22b.

The frame pulse (FP) is input as a clock signal to the second flip-flop 7b, and an output (FIFOSEL signal) inverted for each frame pulse (FP)
Has a configuration in which the first gate 11 and the second gate 12 are alternately opened. In FIG. 5, OUTREQ (# 0, #
1) The signal is an output request signal for data output from each of the output memories 22a and 22b, and is input to the third flip-flop 7c. Of these, OUTREQ #
0 is the J input of the third flip-flop 7c and OUT
REQ # 1 functions as a K input.

In response to such an OUTREQ signal, a BUSACK signal is output from a control unit (not shown) for controlling the bus 1. In this embodiment, this BUSACK signal is input as a clock of the third flip-flop 7c. The output of the third flip-flop 7c is supplied to both output memories 22a and 22b by a cell transfer instruction signal (BUS-
OUTFIFOSEL signal).

In synchronization with the cell transfer instruction signal, the output memories 22a, 22b output the respective selectors 13a, 1a.
Data is output to 3b. The fourth flip-flop 7d and the fifth flip-flop 7e are for outputting a selection signal to the first selector 13a and the second selector 13b.
c is input as data, and the BUSA-ACK
A signal or a BUSB-ACK signal is input as a clock.

The selectors 13a and 13b selectively output the output of one of the output memories 22a and 22b by the selection signal to the first bus (BUS-A) or the second bus (BU).
SB).

In FIG. 5, the first to fourth cells received by the transmission interface unit 4a as INPUT CELL signals are shown.
Cell is BUSA-CELL (first bus 1a side) or B
This shows a state where the data is output to the USB-CELL (the second bus 1b side). In addition, in FIG.
C-9 indicates the order of data cells transmitted to both buses 1. In this figure, C-1 and C-2 are transmitted to the first bus (BUSA-CELL), and then C-3. 5 to the second bus (BUS-CELL), C-6 to the first bus 1a, and C-7 and C-8 to the first bus. The cells indicated by “other cells” between them indicate that the output from the other transmission interface unit 4a is transmitted to the bus 1.

FIG. 6 shows the configuration of the receiving interface unit 4b. Input memories 32a and 32b shown in FIG.
Has substantially the same configuration as the output memories 22a and 22b shown in FIG.

The cells received from the first bus (BUS-A) and the second bus (BUS-B) pass through a header check unit 14 and form a pair of input memories 32a and 32.
b.

Here, the header check unit 14 has an error check function for referring to the header of the cell to check whether a cell loss or the like has occurred. BUSALNOK and B
The USBLNOK signal is supplied to each input memory 32a,
It functions as a frame pulse (FP) to 32b and indicates the beginning of a data cell.

The input memories 32a and 32b are connected to the BUS
The stored information output instruction (FIFO0OUTREQ or FIFO) is issued by the ALNOK signal or the BUSBLNOK signal.
1OUTREQ).

The receiving flip-flop 7f has an OUTPUTTIMING signal as its clock input and an accumulated information output signal (F from the first input memory 32a as its J input.
IF0OUTREQ), and a stored information output signal (FIFO1OURE) from the second input memory 32b as a K input.
In response to Q), the cell transfer instruction signal (READDFOSEL) is distributed to the respective input memories 32a and 32b and output according to the state of the J input and the K input when the OUTPUTTIMING signal is input.

Outputs from the input memories 32a and 32b are sent to the outside through the reception selector 13c. The lower part of FIG. 5 shows the operation sequence on the receiving side.
It is assumed that the cell transmitted in the sequence on the upper transmission side is received by the reception side as it is.

According to the figure, the first bus 1a (BUS-
A) and the cells (C-1 to C-99) received from the second bus 1b (BUS-B) are sequentially sorted and stored in the first input memory 32a and the second input memory 32b by the reception flip-flop 7f. Then, the data is output to an external function block (not shown) in a state where the data is arranged in the order of arrival by the reception selector 13c , and processing such as the header of each data cell is performed.
You. At this time, as shown in FIG.
In the one-input memory 32a, C-3 and C-4 are the second input memos.
Are distributed in a state where they are shifted to
You. As a result, the transfer speed of the data cell is improved,
Considering the processing of data cells after
Distribute data cells to each memory in less time than
Does not catch up with subsequent processing,
Absent. Therefore, input / output memory
Time to shift the time when sorting to 32a, 32b
Is more inevitable than the processing time of the data cell header.
growing.

In the description of the embodiment, the JK flip-flop element 7 is used as the switching means 3. However, when three or more input / output memories 2 are used, a counter element or the like may be constituted as the switching means 3.

[0031]

According to the present invention, high-speed transfer of ATM cells is realized by using an existing device technology and making it a multi-bus, thereby realizing the B-ISDN technology.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an explanatory diagram showing a phase relationship between bus slots in the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a device configuration according to an embodiment.

FIG. 4 is a block diagram showing an internal configuration of an interface unit on a transmission side in the embodiment.

FIG. 5 is an explanatory diagram showing an operation sequence of a cell transfer method in the embodiment.

FIG. 6 shows an interface unit 4 on the receiving side in the embodiment.
Block diagram showing the internal configuration of

[Explanation of symbols]

 1 Bus 1a First bus 1b Second bus 2 Memory 3 Switching means (flip-flop 7a) 4 Interface unit 5 Bus arbiter 6 Memory switching units 7a to 7f Flip-flop element 8 Write control unit 9 Read control unit 10 Gate unit 11 First gate 12 Second gate 13a to 13c Selector 14 Header check unit 22a First Output memory 22b Second output memory 32a First input memory 32b Second input memory

Claims (5)

(57) [Claims] 1. A transfer system for transferring data cells consisting of a header and an information field as unit information, said slotted into data cell units, synchronous bus provided a plurality of respectively the transmitting side and the receiving side When the number input and output memory in corresponding to the number of the bus, the input and output memory and in tough Esu unit that includes a switching換手stage for selectively transferring the data cells to and from the bus When provided at the end of the bus of the transmitting side, each output note
Consists of a Basuabi data to adjust the transmission allocation of the data cells to each bus by Li accumulation state, the switching means in tough Esu unit on the transmission side, data from the outside
When a cell is received, the data cell is entered and exited in the order of arrival.
The bus arbiter stores the data stored in the input / output memories.
When outputting data cells to the bus,
The data is evenly distributed to each bus according to the memory storage status.
Control the cell to output and receive the data cell through the bus.
The switching means of the interface unit makes the data cell arrive at
A data transfer method in a multi-bus, wherein the data cells are sequentially sorted and stored in respective input / output memories . 2. The switching means according to claim 1, wherein
When sorting tassels to each of the input / output memories in the order of arrival
At least for the previous data cell
Shift by a time longer than the processing time of the cell header
So that the later data cell is output to the input / output memory.
2. The data bus transfer method according to claim 1, wherein the data cells are transferred on a multibus. 3. The receiving-side interface unit (4).
A memory switching section (3) as a switching means (3) for generating a frame pulse (FP) indicating the head of the data cell and the bus slot and switching the input / output memory (2) by the frame pulse (FP). 2. The data bus transfer method according to claim 1, further comprising the following step: 4. The memory switching section (6) is a flip-flop element (7) which receives a frame pulse (FP) as a clock input and inverts the output every pulse, and outputs the flip-flop element (7) according to an output from the flip-flop element (7). 4. The data cell transfer system according to claim 3, wherein two input / output memories are switched. 5. The frame pulse (FP) determines a reference bus slot as a reference timing, and generates a reference frame pulse (FP) in synchronization with the head portion.
4. The method according to claim 3, wherein a frame pulse (FP) in each bus phase is sequentially generated at a time difference from the reference frame pulse (FP).