JPH0382244A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To attain inter-processor communication in which an abort rate of a buffer reservation priority cell is '0' by reserving a buffer so as to send a cell and aborting a general cell without being accommodated in the buffer as required. CONSTITUTION:Buffer circuits 17, 18 of an ATM(Asynchronous Transfer Mode) switch 11 reserve a buffer with a capacity requested based on the information of buffer capacity secure request for each port (line). When the residual capacity after reserved buffer capacity is excluded is occupied at the arrival of a general cell, the cell is aborted and when a reserved priority cell arrives on the other hand, it is stored unconditionally in the buffer. Thus, inter-processor communication is attained in which an abort rate of a buffer reservation priority cell is '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-processor communication system for performing data communication between processors, and particularly to an inter-processor communication system using ATM switches.

[Conventional technology]

Inter-processor communication systems that perform data communication between processors include, for example, a method using a bus and a ring method using an optical loop. Among these methods, methods using paths have disadvantages in that the line length cannot be increased and multiple connections cannot be made. Furthermore, the ring method has the drawbacks that the delay time increases when a large number of connections are made, and that if a problem occurs in one location, the entire system is affected.

Therefore, as a countermeasure to these shortcomings, ATM (
^5ynchronous Transfer Mod
e) An interprocessor communication system using switches is being considered.

[Problem to be solved by the invention]

Communication systems using ATM switches perform data communication using cells (packets), so the destination can be determined based on the header, and mechanical connection control is not required as with conventional crossbar switches. do not. For this reason,
The above-mentioned problems regarding line length limitations, limitations on the number of connected units, and delay times do not occur. However, A.T.
Due to the operating principle of self-routing by the M switch hardware, multiple cells are concentrated on one outgoing line,
Collisions may occur. For this reason, various countermeasures against collisions have been proposed, and methods of avoiding collisions using buffers are becoming common.

In the method using this buffer, cells that cannot be accommodated in the buffer are discarded. The capacity of the buffer is limited by hardware design and manufacturing, and cannot be made as large as desired. Therefore,
Statistically, 10-9 to 10-” for all cells
Discarding levels is now allowed.

In normal data communication between users, sufficient communication quality can be maintained even at such a level of discard rate. However, in inter-processor communication, a cell discard rate of "0" is required, and there is a problem in that the existing ATM switch itself cannot realize an inter-processor communication system.

[Means to solve the problem]

In the present invention, (i) a request for securing a buffer capacity of a port corresponding to a destination processor is received from a processor that is about to transmit a cell, and a buffer for the requested amount is reserved; When a general cell arrives as a cell other than a cell, if the capacity of this general cell is larger than the remaining buffer amount after excluding the reserved buffer amount, this general cell is discarded, while it is discarded as a reserved cell. (ii) an ATM switch having a buffer circuit configured to unconditionally accumulate buffer reservation priority cells when they arrive and reduce the reserved buffer amount accordingly;
When there is a request from the processor to reserve buffer capacity, the usage status of the ATM switch buffer is monitored, and when the requested buffer amount or more is empty, the buffer is reserved in the buffer circuit and after the reservation is completed. The inter-processor communication system is provided with a buffer control circuit that returns a signal indicating that the buffer capacity has been secured to the processor that has made this request.

In other words, in the present invention, a buffer of the requested capacity is reserved in the buffer circuit of the ATM switch based on the information on the buffer capacity reservation request for each port (line), and when a general cell arrives, the remaining capacity excluding the reserved buffer capacity is reserved. If the capacity is full, the cell is discarded, while if a reserved priority cell arrives, it is stored in the buffer unconditionally.

In addition, a buffer control circuit is installed to monitor the usage status of the ATM switch's buffer in response to a request from the central processor to reserve a buffer. At the same time, after the reservation is completed, a signal (ACK signal) indicating that the buffer capacity has been secured is sent to the central processor.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows an overview of an inter-processor communication system in an embodiment of the present invention. On the left side of the diagram of the ATM switch circuit 11, there is a central switch that sends out cells.
The first central processor is typically the processor (CP).
Processor 12 is displayed. Further, on the right side of the diagram of the ATM switch circuit 11, second and third central processors 13 and 14 are representatively shown as central processors that receive cells.

The ATM switch circuit 11 is composed of a self-routing ATM switching circuit 16 that accepts and accepts each cell 15, and a plurality of buffer circuits 17 and 18 arranged on the output side thereof in correspondence with the ATM switch output ports.

In this inter-processor communication system, a buffer control circuit 21 is arranged to control the buffer within the ATM switch circuit 11. This buffer control circuit 21 includes a buffer usage status monitor and management table 22,
It is composed of a control circuit (CTL) 23. In this system, the first central processor 12 that sends out cells receives a buffer capacity reservation request signal 2 at the time of sending out cells.
5 to the control circuit 23 in the buffer control circuit 21. When the buffer request is secured, the control circuit 23 sends an ACK (acknowledgement) signal 2 indicating this.
6 is sent out. The control circuit 23 is adapted to supply a buffer control signal 27 to each buffer circuit 17, 18 based on the contents of the buffer usage status monitor and management table 22.

In the inter-processor communication system configured as above, the first
A case will be described in which the central processor 12 communicates with the second central processor 13.

FIG. 2 is for explaining the operation of the central processor. The first central processor 12 is
Prior to communication, a buffer capacity reservation request signal 25 is transmitted to the buffer control circuit 21 (step in FIG. 2). Then, an ACK signal 26 indicating that the buffer request has been secured is received from the buffer control circuit 21. (Step ■).When the ACK signal 26 is received (Y)
, the first central processor 12 sends out the reserved cells (buffer reservation priority cells) in the amount reserved in this manner (steps (2), (2)). This ends the control of the first central processor 12.

FIG. 3 shows the operation of the buffer control circuit in response to this. The buffer control circuit 21 controls the buffer capacity from the first central processor 12! Reservation request signal 2
5 (step ■ in Figure 3), the output port (line) in the buffer usage status monitor and management table 22 is received.
Check the usage status of the corresponding one (step ■
).

In this case, since communication is performed to the second central processor 13, the usage status of the buffer circuit 17 is checked.

In this example, the corresponding buffer usage shown in the buffer usage monitor and management table 22 is “58”.
It is.

Maximum usage amount and current usage amount of buffer circuit 17 “58”
If the difference satisfies the requested amount (step ■; Y), the buffer control circuit 21 instructs the buffer circuit 17 to update its capacity to the value obtained by subtracting the requested capacity from the maximum capacity. ■), then sends back an ACK signal 26 to the first central processor 12 (
Step ■).

After that, the buffer control circuit 21 monitors whether the type of passing cells of the buffer circuit 17 is a buffer reservation priority cell (step ■). Then, if these are buffer reservation priority cells, each time a cell passes The buffer control circuit 21 is configured to communicate the capacity of the buffer circuit 17 (step ■).The buffer control circuit 21 performs countermeasures such as cancellation for a long-term pending case in which it only reserves a buffer and does not send a buffer reservation priority cell (step ■). ), or when the amount of buffer capacity reservation requests is too large for the maximum capacity of the buffer circuit 17.If all reserved cells complete passage (step >, the control of the buffer control circuit 21 ends.

FIG. 4 shows the flow of the operation of the iffer circuit. In this embodiment, the buffer circuit 17 sets its own buffer amount to the buffer capacity value designated by the buffer control circuit 21. Thereafter, the type of cell is checked (step ■) each time a cell is received (step ■ in Figure 4).If a cell other than a buffer reservation priority cell, that is, a general cell is received (N), the cell type is checked at that time. Compare step ■) with the buffer capacity value of
On the other hand, if the capacity of the buffer circuit 17 exceeds the capacity of the buffer circuit 17 (step ■; Y), the general cell is discarded (step ■).

On the other hand, if the buffer reservation priority cell is received in step (3) in FIG. 4 (Y), this cell is unconditionally stored in the buffer circuit 17 and output to the second central processor 13. (Step ■〉.

The buffer for the incoming reservation is secured, so
This is because it is possible to process all buffer reservation priority cells without exceeding the maximum value of the buffer circuit 17.

The buffer circuit 17 subtracts the reserved buffer amount each time the buffer reservation priority cell passes;
The current buffer capacity value that can be used by the general cell is added (step ■).

In the embodiment described above, the output buffer type ATM switch 11 is shown in which the buffer circuits 17 and 18 are present at the subsequent stage of the ATM switching circuit 16.
It goes without saying that the present invention can also be applied to an input buffer system arranged at the front stage or a common buffer system common to all ports.

〔Effect of the invention〕

As described above, according to the present invention, cells are transmitted by reserving a buffer, while general cells are discarded as necessary without being accommodated in the buffer, so that the discard rate for buffer reservation priority cells is "0". This has the effect of enabling inter-processor communication. In other words, in an inter-processor communication system using ATM switches, which have the characteristics of unlimited line length, multiple connections, and short delay times, we have developed an inter-processor communication system that eliminates the only drawback of ``cell discard.'' The effect is that it can be realized.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention. Of these, Fig. 1 shows the system configuration country showing an overview of the inter-processor communication system, and Fig. 2 shows the control of the central processor that transmits cells. Fig. 3 is a flowchart showing the control operation of the buffer control circuit; Fig. 4 is a flowchart showing the control operation of the buffer control circuit;
The figure is a flowchart showing the control operation of the buffer circuit. 11... ATM switch, 12... (sending side) first central processor, 13... (receiving side) second central processor, 15. ...Cell, 16...ATM switching circuit, 17.1g
... Buffer circuit, 21 ... Buffer control circuit, 22 ... Buffer usage status monitor and management table, 25 ... Buffer capacity reservation request signal, 26.・
...ACK signal.

Claims (1)

[Scope of Claims] A request for securing buffer capacity of a port corresponding to a destination processor is received from a processor attempting to transmit a cell, a buffer for the requested amount is reserved, and a cell for which this reservation has been made is performed. When a general cell arrives as a cell other than the reserved one, if the capacity of this general cell is larger than the remaining buffer amount after excluding the reserved buffer amount, this general cell is discarded, while it is discarded as a reserved cell. An ATM switch having a buffer circuit that stores buffer reservation priority cells unconditionally when they arrive and reduces the reserved buffer amount accordingly, and a processor that stores information about the buffer capacity. When there is a request to reserve the buffer, the usage status of the buffer of the ATM switch is monitored, and when the requested buffer amount or more becomes empty, the buffer is reserved in the buffer circuit, and after the reservation is completed, the request is received. An inter-processor communication system comprising: a buffer control circuit that returns a signal indicating that buffer capacity has been secured to a processor that has received a buffer.