US5978379A
(en)
|
1997-01-23 |
1999-11-02 |
Gadzoox Networks, Inc. |
Fiber channel learning bridge, learning half bridge, and protocol
|
US7430171B2
(en)
|
1998-11-19 |
2008-09-30 |
Broadcom Corporation |
Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
|
US6509773B2
(en)
*
|
2000-04-28 |
2003-01-21 |
Broadcom Corporation |
Phase interpolator device and method
|
JP4542286B2
(ja)
*
|
2001-06-06 |
2010-09-08 |
富士通株式会社 |
並列信号自動位相調整回路
|
US6934869B1
(en)
*
|
2001-09-12 |
2005-08-23 |
Big Bear Networks, Inc. |
Method and apparatus for eliminating dead zone in phase locked loops using binary quantized phase detectors
|
US7110485B2
(en)
*
|
2002-09-26 |
2006-09-19 |
Stmicroelectronics, Inc. |
System and method for clock synchronization of multi-channel baud-rate timing recovery systems
|
US7224951B1
(en)
*
|
2003-09-11 |
2007-05-29 |
Xilinx, Inc. |
PMA RX in coarse loop for high speed sampling
|
US20060067452A1
(en)
*
|
2004-09-24 |
2006-03-30 |
Intel Corporation |
Clock and data recovery circuit
|
US7421050B2
(en)
*
|
2004-10-14 |
2008-09-02 |
Agere Systems Inc. |
Parallel sampled multi-stage decimated digital loop filter for clock/data recovery
|
US7751521B2
(en)
|
2004-11-16 |
2010-07-06 |
Electronics And Telecommunications Research Institute |
Clock and data recovery apparatus
|
KR100706605B1
(ko)
|
2004-11-16 |
2007-04-12 |
한국전자통신연구원 |
클럭 및 데이터 복원 장치
|
US8081706B2
(en)
*
|
2005-08-24 |
2011-12-20 |
Altera Corporation |
Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry
|
JP5521366B2
(ja)
*
|
2009-03-19 |
2014-06-11 |
日本電気株式会社 |
制御回路及び回路間通信方法
|
US7863960B2
(en)
*
|
2009-04-30 |
2011-01-04 |
International Business Machines Corporation |
Three-dimensional chip-stack synchronization
|
JP5401164B2
(ja)
*
|
2009-05-01 |
2014-01-29 |
ザインエレクトロニクス株式会社 |
受信装置
|
US9577816B2
(en)
|
2012-03-13 |
2017-02-21 |
Rambus Inc. |
Clock and data recovery having shared clock generator
|
JP6019704B2
(ja)
|
2012-04-24 |
2016-11-02 |
住友電気工業株式会社 |
光送受信装置
|
US20130285720A1
(en)
*
|
2012-04-26 |
2013-10-31 |
Rafel Jibry |
Multiple channel phase detection
|
US9374216B2
(en)
|
2013-03-20 |
2016-06-21 |
Qualcomm Incorporated |
Multi-wire open-drain link with data symbol transition based clocking
|
US9313058B2
(en)
|
2013-03-07 |
2016-04-12 |
Qualcomm Incorporated |
Compact and fast N-factorial single data rate clock and data recovery circuits
|
US9363071B2
(en)
|
2013-03-07 |
2016-06-07 |
Qualcomm Incorporated |
Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
|
US9755818B2
(en)
|
2013-10-03 |
2017-09-05 |
Qualcomm Incorporated |
Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
|
US9735948B2
(en)
|
2013-10-03 |
2017-08-15 |
Qualcomm Incorporated |
Multi-lane N-factorial (N!) and other multi-wire communication systems
|
US9203599B2
(en)
|
2014-04-10 |
2015-12-01 |
Qualcomm Incorporated |
Multi-lane N-factorial (N!) and other multi-wire communication systems
|
US9385859B2
(en)
*
|
2013-12-27 |
2016-07-05 |
Realtek Semiconductor Corp. |
Multi-lane serial data link receiver and method thereof
|
JP6303513B2
(ja)
*
|
2014-01-14 |
2018-04-04 |
富士通株式会社 |
マルチレーンリタイマ回路およびマルチレーン伝送システム
|
JP6303823B2
(ja)
*
|
2014-05-30 |
2018-04-04 |
富士通株式会社 |
受信回路
|
US10084623B1
(en)
*
|
2014-11-19 |
2018-09-25 |
Fmax Technologies, Inc. |
Multichannel CDR with sharing of adaptation hints and learning
|