JP2001057391A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which is capable of restraining a gate electrode of a MISFET(Metal-Insulator-Semiconductor Field Effect Transistor) from increasing in resistance attendant on a reduction in its width. SOLUTION: A first N-type polycrystalline silicon film 7a1 included in the gate electrode 7a of an N-channel MISFET Qn is set different in impurity concentration from a first P-type polycrystalline silicon film 7b1 included in the gate electrode 7b of a P-channel MISFET Pn. By this setup, a first polycrystalline silicon film of a tie region L1 located between the first N-type polycrystalline silicon film 7a1 and the first P-type polycrystalline silicon film 7b1 is set at 1×1020 cm-3 in impurity concentration so as to be less increased in resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a semiconductor integrated circuit device having a semiconductor device employing a self-aligned-silicide technology. Technology.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor integrated circuit devices increases, MISFETs (Metal Insulator Semiconductors) have been developed.
r Field Effect Transistor) is miniaturized according to the scaling rule, the thickness of the gate electrode is thin, and the impurity concentration of the semiconductor region forming the source and drain is low. Therefore, the resistance of the conductive film forming the gate electrode and the resistance of the semiconductor region forming the source and drain are increased, and the MISFE
There is a problem that high-speed operation cannot be obtained even if T is reduced in size.

Therefore, in a fine MISFET, a salicide technique for forming a low-resistance silicide film by self-alignment on the surface of a conductive film constituting a gate electrode, for example, a polycrystalline silicon film and a semiconductor region constituting a source and a drain is studied. Have been.

Incidentally, a salicide technique using titanium (Ti) is described in, for example, VMI (VLSI).
Multilevel Interconnection Conference. Low Sheet
Resistance Ti Salicide Process using Amorphous-Si
Clad and Ge Pre-amorphization for 0.1 μm CMOS Gat
e PP195-200, 1998).

[0005]

In the Ti salicide technology, it has been pointed out that the problem that the sheet resistance of the gate electrode of the MISFET increases as the gate electrode becomes thinner (fine wire effect). One of the causes of the fine wire effect is disconnection at the Ti silicide grain boundary due to aggregation. When the length (gate length) of the gate electrode is shortened, the disconnected portion crosses the gate electrode and forms an underlayer of the Ti silicide film. When the resistance of the polycrystalline silicon film located becomes dominant or the contact resistance increases, the resistance of the gate electrode increases.
The disconnection at the Ti silicide grain boundary is prevented by, for example, a method of suppressing heat treatment applied to the Ti silicide film to suppress aggregation.

However, according to the study by the present inventors, even if the heat treatment applied to the Ti silicide film is suppressed,
It became clear that it was difficult to completely prevent disconnection at the Ti silicide grain boundary due to aggregation.

Further, in a gate electrode to which a dual gate process is applied, when impurities are implanted into a polycrystalline silicon film constituting the gate electrode by ion implantation, n
N at the connection point (connection region) between the p-type region and the p-type region
Since the type impurity and the p-type impurity are implanted, if the implantation amounts of both are equal, the connecting region is effectively a non-doped region. When a region where the Ti silicide film is broken by the aggregation overlaps with the polycrystalline silicon film in the non-doped region, the contact resistance between the Ti silicide film and the polycrystalline silicon film greatly increases, and the non-doped polycrystalline silicon film is removed. Causes the resistance of the gate electrode to increase by one digit or more from the design value.

For example, the width (gate width) of the gate electrode is set to 0.1.
2 μm, gate electrode height 0.2 μm, disconnection width of Ti silicide film 0.05 μm, resistivity of polycrystalline silicon film 1
In the case of 0 Ω · cm, 125 k
Ω increases.

Further, when the resistance of the gate electrode is greatly increased, when the semiconductor device is operated at a high frequency, the charge and discharge of the gate electrode become insufficient, causing a malfunction of the semiconductor device.

It is an object of the present invention to provide a technique capable of suppressing an increase in resistance due to thinning of a gate electrode of a MISFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention is characterized in that a region into which an n-type impurity is introduced and a p
A region into which a type impurity is introduced, wherein the resistance of the electrode formed of the conductive film is reduced by a silicide film provided on the upper surface of the electrode, and the impurity concentration of the connection region is reduced. ^{Is set} to 1 × 10 ²⁰ cm ⁻³ or more.

(2) A semiconductor integrated circuit device according to the present invention is provided with a region in which an n-type impurity is introduced and a region in which a p-type impurity is introduced with a connecting region interposed between conductive films of the same layer,
The resistance of the electrode formed of the conductive film is reduced by a silicide film provided on the upper surface of the electrode, and the length of the connecting region is shorter than the grain size of the silicide film. is there.

(3) In the semiconductor integrated circuit device of the present invention, a region into which an n-type impurity is introduced and a region into which a p-type impurity is introduced are provided with a connecting region interposed between conductive films of the same layer.
The resistance of the electrode formed of the conductive film is reduced by a silicide film provided on the upper surface of the electrode, and the width of the connecting region is equal to the width of the region into which the n-type impurity is introduced or It is relatively thicker than the width of the region into which the p-type impurity has been introduced.

(4) In the semiconductor integrated circuit device of the present invention, a region into which an n-type impurity is introduced and a region into which a p-type impurity is introduced are provided with a connecting region interposed between conductive films of the same layer,
The low resistance of the electrode formed of the conductive film is achieved by a silicide film provided on the upper surface of the electrode, and the silicide film is also formed on the side wall of the conductive film in the connection region. It is.

(5) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device according to (2), (3) or (4), the connecting region may be formed as an effective non-doped region or 1 × 10 ²⁰ cm. ^The semiconductor region has an impurity concentration of ^-3 or more.

(6) In the semiconductor integrated circuit device of the present invention, in the semiconductor integrated circuit device of (3), the width of the connecting region is 0.2 μm or more.

(7) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device according to any one of the above (1) to (4), the impurity concentration of the connection region is changed to the impurity concentration of the region into which the n-type impurity is introduced. And relatively low or equivalent to the impurity concentration of the region into which the p-type impurity has been introduced.

(8) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device according to any one of (1) to (4), the region into which the n-type impurity is introduced is an n-channel MISFE.
The gate electrode of T is formed, and the region into which the p-type impurity is introduced forms the gate electrode of the p-channel MISFET.

(9) In the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device according to any one of (1) to (4), the conductive film is formed of at least two polycrystalline silicon films. .

(10) In the method of manufacturing a semiconductor integrated circuit device of the present invention, an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation, and the other side of the conductive film is ion-implanted. When the p-type impurity is introduced, the dose of the ion implantation of the n-type impurity and the dose of the ion implantation of the p-type impurity are 1 × 10 ¹⁵
The ion implantation of the n-type impurity and the ion implantation of the p-type impurity are overlapped with each other with a difference of not less than cm ⁻² .

(11) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation, and the other side of the conductive film is ion-implanted. When the p-type impurity is introduced, the boundary between the first resist film used as a mask when introducing the n-type impurity and the second resist film used as a mask when introducing the p-type impurity substantially coincides with each other. The first resist film and the second resist film.

(12) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation, and the other side of the conductive film is ion-implanted. When the p-type impurity is introduced, the width of the conductive film in the connecting region located between the region where the n-type impurity is introduced and the region where the p-type impurity is introduced is
The width of the conductive film in the region into which the n-type impurity is introduced or the width of the conductive film in the region into which the p-type impurity is introduced are processed to be relatively thick.

(13) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation, and the other side of the conductive film is ion-implanted. When introducing a p-type impurity, a step of forming an electrode composed of the conductive film, a step of forming a sidewall spacer on a side wall of the electrode, a step of introducing an n-type impurity and a step of forming a p-type impurity Removing the sidewall spacers on the sidewalls of the electrodes in the connecting region located between the region into which the n-type impurity is introduced and the region into which the n-type impurity is introduced by a self-alignment method. A step of forming a silicide film on the upper surface of the electrode and the upper surface and the side wall of the electrode in the connection region.

(14) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (10), (11) or (12), wherein the upper surface of the electrode formed of the conductive film is provided. Then, a silicide film is formed by a self-alignment method.

According to the above means, the n-channel type MI
By making the impurity concentration of the conductive film forming the gate electrode of the SFET different from that of the conductive film forming the gate electrode of the p-channel MISFET, the impurity concentration in the connection region is about 1 × 10 ²⁰ cm ⁻³ or more. , The resistivity of the conductive film in the connection region can be reduced, and the gate electrode of the n-channel MISFET and the p-channel MIS
It is possible to suppress an increase in resistance in a connection region between the FET and the gate electrode.

According to the above means, the n-channel MI
By shortening the length of the connection region between the gate electrode of the SFET and the gate electrode of the p-channel MISFET,
Even if aggregation occurs in the Ti silicide film in the connection region, the possibility that this disconnection will occur on the connection region is reduced, and the gate electrode of the n-channel MISFET and the p-channel MI
An increase in resistance in a region where the SFET is connected to the gate electrode can be suppressed.

According to the above means, the n-channel MI
The width of the connection region between the gate electrode of the SFET and the gate electrode of the p-channel type MISFET is
By making the layout relatively thicker than the gate length of the ET or the gate length of the p-channel MISFET on the layout, the probability that the Ti silicide film is completely disconnected even if aggregation occurs in the Ti silicide film in the connection region is reduced. , So that the n-channel type MISF
An increase in resistance in a connection region between the gate electrode of the ET and the gate electrode of the p-channel MISFET can be suppressed.

According to the above means, the n-channel MI
Ti on the side wall of the conductive film constituting the connection region between the gate electrode of the SFET and the gate electrode of the p-channel type MISFET
By providing a silicide film and making the width of the connecting region relatively larger than the width of the conductive film forming the gate electrode of the n-channel MISFET or the p-channel MISFET, the surface of the conductive film forming the connecting region is formed. Even if agglomeration occurs in the provided Ti silicide film, it is possible to reduce the probability that the Ti silicide film is completely disconnected, whereby the n-channel MISFET gate electrode and the p-channel MISFET gate electrode The increase in resistance in the connection region can be suppressed.

[0030]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 FIG. 1 shows a complementary metal oxide semiconductor (CMOS) according to an embodiment of the present invention.
1 shows a plan view and a cross-sectional view of a main part of a semiconductor substrate showing a device. 1A is a plan view of a main part, FIG. 1B is a cross-sectional view of the main part taken along line AA ′ of FIG. 1A, and FIG. 1C is a BB ′ of FIG. It is principal part sectional drawing in a line. In the figure, Qn is an n-channel type MISFE
T and Qp are p-channel MISFETs.

The n-channel type MISFET Qn is formed in an active region surrounded by an element isolation groove 2a formed on the semiconductor substrate 1, and a p-type well 3 is formed in the active region. An insulating film, for example, a silicon oxide film 2b is buried inside the element isolation groove 2a to form an element isolation region. n on the surface of the channel type MISFETQn the p-type well 3 is the source by a pair of n ⁺ -type semiconductor region 4,
A drain is formed, and a Ti silicide film 5 a formed by a salicide technique is formed on the surfaces of the pair of n ⁺ -type semiconductor regions 4.

A gate insulating film 6 made of a silicon oxide film is formed on the p-type well 3 between the pair of n ⁺ -type semiconductor regions 4 of the n-channel type MISFET Qn. Polycrystalline silicon film 7a ₁ and 2n
A gate electrode 7a is formed by a laminated film made of type polycrystalline silicon film 7a _2.

_On the upper layer of the _second n-type polycrystalline silicon film 7a2, a T film formed in the same step as the Ti silicide film 5a is formed.
An i-silicide film 5b is provided, and a sidewall spacer 8 made of a silicon oxide film is provided on a side wall of the gate electrode 7a.
Is provided.

[0036] The first 1n-type polycrystalline silicon film 7a ₁ and second 2n-type polycrystalline silicon film 7a _2, and n-type impurities are introduced, the impurity concentration of the 1n-type polycrystalline silicon film 7a ₁ is about 6 × It is about 10 ²⁰ cm ^-3 . The 2n-type polycrystalline impurity concentration of the silicon film 7a ₂ is relatively low compared to the first 1n-type polycrystalline impurity concentration of the silicon film 7a _1, the impurity concentration so as not to inhibit the resistance of the Ti silicide film 5b Is set.

Similarly, a p-channel type MISFET Qp
Is formed in an active region surrounded by an element isolation groove 2a formed on the semiconductor substrate 1, and an n-type well 9 is formed in the active region. An insulating film, for example, a silicon oxide film 2b is buried inside the element isolation groove 2a to form an element isolation region. Although not shown, a source and a drain are formed by a pair of p ⁺ -type semiconductor regions on the surface of the n-type well 9 of the p-channel type MISFET Qp.
Further, a Ti silicide film 5a formed by a salicide technique is formed on the surfaces of the pair of p ⁺ -type semiconductor regions.

On the n-type well 9 between the pair of p ⁺ -type semiconductor regions of the p-channel type MISFET Qp, a gate insulating film 6 made of a silicon oxide film is further formed. crystalline silicon film 7b ₁ and the gate electrode 7 in the 2p-type polycrystalline made of a silicon film 7b ₂ laminated film
b.

_On the upper layer of the _second p-type polycrystalline silicon film 7b2, a T film formed in the same step as the Ti silicide film 5a is formed.
i silicide film 5b is provided, and a sidewall spacer 8 made of a silicon oxide film is provided on a side wall of gate electrode 7b.
Is provided.

A p-type impurity is introduced into the first p-type polycrystalline silicon film 7b ₁ and the second p-type polycrystalline silicon film 7b ₂ , and the impurity concentration of the _first p-type polycrystalline silicon film 7b ₁ is about 4 ×. It is about 10 ²⁰ cm ^-3 . The 2p-type polycrystalline impurity concentration of the silicon film 7b ₂ is relatively low compared to the first 1p-type polycrystalline impurity concentration of the silicon film 7b _1, the impurity concentration so as not to inhibit the resistance of the Ti silicide film 5b Is set.

Here, the first n-type polycrystalline silicon film 7a ₁
When the connecting region L ₁ provided between the first 1p-type polycrystalline silicon film 7b _1, and the 2n-type polycrystalline silicon film 7a ₂ between the first 2p-type polycrystalline silicon film 7b ₂ connecting area L _Two are provided. As described later, the first 1n-type polycrystalline silicon film n-type impurity introduced into 7a ₁ and p-type impurities introduced to the 1p-type polycrystalline silicon film 7b _1,
Since being introduced overlapped in connecting region L ₁ located between them, the effective impurity concentration in the connecting area L ₁ is the first 1n-type polycrystalline silicon film 7a ₁ and the 1p-type polycrystalline silicon film 7b about 2 × 1 is an impurity concentration difference ₁
It becomes 0 ²⁰ cm ^-3 .

Further, an interlayer insulating film 11 is formed above the n-channel type MISFET Qn and the p-channel type MISFET Qp.
A contact hole 12a reaching the Ti silicide film 5a on the n ⁺ type semiconductor region 4 constituting the source and drain of the channel type MISFET Qn and the p channel type MIS
A contact hole 12b reaching the Ti silicide film 5a on the p ⁺ type semiconductor region 10 constituting the source and drain of the FET Qp is opened. Although not shown,
T on the gate electrode 7a of the n-channel MISFET Qn
i-silicide film 5b and p-channel MISFET Q
A contact hole reaching the Ti silicide film 5b on the p gate electrode 7b is also provided.

The wiring layer 14 forms the source and drain of the n-channel MISFET Qn via the plug 13 embedded in the contact holes 12a and 12b.
^It is connected to the Ti silicide film 5a on the ⁺ type semiconductor region 4 and the Ti silicide film 5a on the p ⁺ type semiconductor region constituting the source and drain of the p-channel type MISFET Qp.

A method of manufacturing a CMOS device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 2, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is prepared. next,
This semiconductor substrate 1 is thermally oxidized to form a film having a thickness of 0.01 on its surface.
A thin silicon oxide film 15 having a thickness of about μm is formed, and then a chemical vapor deposition (Chemical Vapor Deposition) is formed thereon.
A silicon nitride film 16 having a thickness of about 0.1 μm is deposited by a CVD method, and then the silicon nitride film 16, the silicon oxide film 15 and the semiconductor substrate 1 are sequentially dry-etched using a resist pattern as a mask, thereby forming an element isolation region. A device isolation groove 2a having a depth of about 0.35 μm is formed in the semiconductor substrate 1 of FIG.

Next, after removing the silicon nitride film 16 by wet etching using hot phosphoric acid, as shown in FIG. 3, the silicon oxide film 2b deposited on the semiconductor substrate 1 by the CVD method is etched back or Chemical mechanical polishing (Chemic
An element isolation region is formed by polishing using a CMP (Al Mechanical Polishing) method to leave the silicon oxide film 2b inside the element isolation groove 2a. Subsequently, the semiconductor substrate 1 is annealed at about 1000 ° C.
The silicon oxide film 2b embedded in a is densified (baked).

Next, the n-channel MIS of the semiconductor substrate 1
Boron for forming a p-type well 3 is ion-implanted in a region for forming the FET Qn, and a p-channel MISFET is formed.
Phosphorus for forming an n-type well 9 is ion-implanted in a region for forming Qp. The boron is implanted, for example, at an implantation energy of 200 keV and a dose of 2 × 10 ¹³ cm ⁻² , and the phosphorus is implanted, for example, at an implantation energy of 500 keV.
The implantation is performed at a dose of 3 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 4, the semiconductor substrate 1 is thermally oxidized to form a gate insulating film 6 on each surface of the p-type well 3 and the n-type well 9 with a thickness of about 4 nm. Thereafter, a first-layer polycrystalline silicon film 17 is deposited on the semiconductor substrate 1 by a CVD method.

Next, as shown in FIG. 5, after covering the n-type well 9 with the patterned resist film 18, the n-type well 9 is transferred to the first polycrystalline silicon film 17 in the region where the n-channel MISFET Qn is formed. Impurities, for example, 6 × 10 ¹⁵ c
Ions are implanted at a dose of m ^-2 to form a _first n-type polycrystalline silicon film 7a1.

Next, after removing the resist film 18,
As shown in FIG. 6, after covering the p-type well 3 with a patterned resist film 19, a p-channel MISFET is formed.
Qp is the p-type impurity into the first layer polycrystalline silicon film 17 of the region formed, to form a second 1p-type polycrystalline silicon film 7b ₁ is ion implanted at a dose of e.g. 4 × 10 ¹⁵ cm ^-2.

[0051] Here, the n-type impurity and the p-type impurity is ion-implanted into the first layer polycrystalline silicon film 17, the first 1n-type polycrystalline silicon film 7a ₁ and the 1p-type polycrystalline silicon film 7b ₁ is also introduced into the connecting area L ₁ located between the by the impurity concentration of the n-type impurity and the p-type impurity is different, the impurity concentration of the connecting region L ₁ becomes about 2 × 10 ²⁰ cm ^-3 approximately .

Next, after removing the resist film 19,
As shown in FIG. 7, a second polycrystalline silicon film 20 is deposited on the semiconductor substrate 1 by the CVD method. Thereafter, the second-layer polycrystalline silicon film 20 and the first-layer polycrystalline silicon film 17 are sequentially etched using the resist pattern as a mask.
A gate electrode 7a of an n-channel type MISFET Qn composed of a laminated film composed of the _first polycrystalline silicon film 20 and the first n-type polycrystalline silicon film 7a1, the second polycrystalline silicon film 20 and the first p-type polycrystalline silicon Membrane 7b
P-channel type MI constituted by a laminated film composed of ₁
It is processed into the gate electrode 7b of the SFET Qp.

Next, as shown in FIG. 8, a silicon oxide film deposited on the semiconductor substrate 1 by CVD is subjected to RIE (Reacti
The silicon oxide film is left on the side wall of the stacked film composed of the processed second-layer polycrystalline silicon film 20 and the first-layer polycrystalline silicon film 17 by anisotropic etching using a ve ion etching method. The spacer 8 is formed.

Next, as shown in FIG. 9, after the n-type well 9 is covered with a patterned resist film 21, an n-type impurity, for example, phosphorus is introduced into the p-type well 3 and the source of the n-channel MISFET Qn is introduced. Forming the high-concentration n ⁺ -type semiconductor region 4 constituting the drain and simultaneously introducing the n-type impurity into the second-layer polycrystalline silicon film 20 to form a part of the gate electrode 7a of the n-channel MISFET Qn. forming a first 2n-type polycrystalline silicon film 7a ₂ to.

Next, after the resist film 21 is removed, as shown in FIG. 10, the p-type well 3 is covered with a patterned resist film 22, and p-type impurities, for example, boron fluoride are introduced to introduce p-type impurities. Channel type MISFET Qp
Source, and at the same time to form a high-concentration p ⁺ -type semiconductor region constituting the drain, the second layer polycrystalline silicon film 20 by introducing the p-type impurity, p-channel type MISFET
Forming a first 2p-type polycrystalline silicon film 7b ₂ that constitutes a part of the gate electrode 7b of qp.

[0056] Here, the n-type impurity and the p-type impurity to the second layer polycrystalline silicon film 20 is ion-implanted, and the 2n-type polycrystalline silicon film 7a ₂ and the 2p-type polycrystalline silicon film 7b ₂ Is also introduced into the connection region L2 located between the _two .

Next, a Ti film having a thickness of about 30 to 50 nm is formed on the semiconductor substrate 1 by sputtering or CVD.
After being deposited thereon, a heat treatment of about 600 to 700 ° C. is performed on the semiconductor substrate 1 in a nitrogen atmosphere, and then the unreacted Ti film is removed. Thereafter, a heat treatment of about 850 ° C. is performed on the semiconductor substrate 1 for lowering the resistance, so that the source of the n-channel type MISFET Qn, as shown in FIG.
Surface of n ⁺ type semiconductor region 4 constituting the drain and p
A Ti silicide film 5a is formed on the surface of the p ⁺ type semiconductor region constituting the source and drain of the channel type MISFET Qp, and at the same time, a T silicide film is formed on the upper surface of the second polycrystalline silicon film 20.
An i-silicide film 5b is formed.

Next, after an interlayer insulating film 11 is formed on the semiconductor substrate 1, the interlayer insulating film 11 is etched using the resist pattern as a mask to form contact holes 12a, 12a.
b is opened. Next, a metal film, for example, a tungsten film is deposited on the interlayer insulating film 11 and the surface of the metal film is flattened by, for example, a CMP method, so that the metal film is buried in the contact holes 12a and 12b to form a plug 13. After the formation, the metal film deposited on the interlayer insulating film 11 is etched to form the wiring layer 14, whereby the CMOS device shown in FIG. 1 is almost completed.

As described above, according to the first embodiment, n
Of the 1p-type polycrystalline silicon film 7b ₁ that constitutes a part of the 1n-type polycrystalline silicon film an impurity concentration of 7a ₁ and p-channel type MISFETQp gate electrode 7b constituting a part of the gate electrode 7a of the channel MISFETQn by making the impurity concentration, the second 1n-type polycrystalline silicon film 7a ₁ and the second 1p-type polycrystalline silicon film 7b ₁
Is set to about 2 × 10 ²⁰ cm ⁻³ in the first-layer polycrystalline silicon film 17 in the connection region L ₁ . 1
The resistivity of the first-layer polycrystalline silicon film 17 having an impurity concentration of × 10 ²⁰ cm ⁻³ or more is 10 ⁻³ Ωcm or less. For example, the width of the gate electrodes 7a and 7b is 0.2 μm and the height is 0.2 μm.
If the disconnection width is 2 μm, the disconnection width is 0.05 μm, and the resistivity of the first-layer polycrystalline silicon film 17 is 10 ⁻³ Ωcm, the first-layer polycrystalline silicon film 17 in the connection region L ₁ has a 12.5-μm thickness.
(= 10 ⁻³ × 0.05 × 10 ^{−4 /(0.2×0.2)×}
10 ⁻⁸ ) Ω resistance, and an increase in the resistance value of the first-layer polycrystalline silicon film 17 in the connection region L ₁ can be suppressed low.

(Embodiment 2) FIG. 12 and FIG.
FIGS. 9A and 9B are a main part plan view and a main part cross-sectional view of a semiconductor substrate for describing a method of manufacturing a CMOS device according to another embodiment of the present invention. FIGS.

First, as shown in FIG. 4, a first-layer polycrystalline silicon film 17 is deposited on the semiconductor substrate 1 by the CVD method in the same manufacturing method as in the first embodiment.

Next, as shown in FIG. 12A, after the n-type well 9 is covered with the patterned resist film 23, the first polycrystalline silicon film 17 in the region where the n-channel MISFET Qn is formed is formed. N-type impurities, for example, 4
Ions are implanted at a dose of × 10 ¹⁵ cm ^-2 to form a _first n-type polycrystalline silicon film 7a1. The resist film 23
Then, as shown in FIG. 12B, after covering the p-type well 3 with the patterned resist film 24,
A p-type impurity is added to the first polycrystalline silicon film 17 in the region where the p-channel MISFET Qp is formed, for example, by 4 × 1
Ions are implanted at a dose of 0 ¹⁵ cm ^-2 to form a _first p-type polycrystalline silicon film 7b1. Here, the resist film 23 and the resist film 24 are arranged such that the boundary between the resist film 23 and the resist film 24 substantially coincides with each other.

Next, after removing the resist film 24,
Second layer polycrystalline silicon film 2 on semiconductor substrate 1 by CVD method
Deposit 0. Thereafter, the gate electrode 7a of the n-channel type MISFETQn constituted by second-layer polycrystalline silicon film 20 and the 1n-type polycrystalline silicon film 7a _1,
P-channel type MISF constituted by second-layer polycrystalline silicon film 20 and the 1p-type polycrystalline silicon film 7b ₁
The gate electrode 7b of ETQp is processed, and then the sidewall spacer 8 is formed.

Next, as shown in FIG. 13A, after covering the n-type well 9 with a patterned resist film 25, an n-type impurity is introduced to
At the same time as forming the high-concentration n ⁺ -type semiconductor region 4 constituting the source and drain of n, the second polycrystalline silicon film 2
0 into the n-channel type MISF
Forming a first 2n-type polycrystalline silicon film 7a ₂ constituting a part of the gate electrode 7a of ETQn.

Next, after removing the resist film 25,
As shown in FIG. 13B, the p-type well 3 is covered with a patterned resist film 26, and then a p-type impurity is introduced to form a high-concentration p ⁺ -type semiconductor forming the source and drain of the p-channel MISFET Qp. At the same time as the formation of the region, the p-type impurity is introduced into the second-layer polycrystalline silicon film 20 to form a second p-type polycrystalline silicon film 7b ₂ forming a part of the gate electrode 7b of the p-channel MISFET Qp.
To form Here, the resist film 25 and the resist film 26 are arranged such that the boundary between the resist film 25 and the resist film 26 substantially coincides with each other.

FIG. 13C is a cross-sectional view of a principal part of the semiconductor substrate taken along line CC ′ after removing the resist film 26 in FIG. 13B. It is formed in a connecting region L ₁ between the _first n-type polycrystalline silicon film 7 a ₁ and the first p-type polycrystalline silicon film 7 b ₁ formed in the first polycrystalline silicon film 17, and in the second polycrystalline silicon film 20. connecting region L ₂ between the first 2n-type polycrystalline silicon film 7a ₂ and the 2p-type polycrystalline silicon film 7b ₂ is provided minimal narrowly.

Thereafter, in the same manner as in the manufacturing method described with reference to FIG.
A device is formed.

As described above, according to the second embodiment, 1
A connection region L ₁ between the _first n-type polycrystalline silicon film 7 a ₁ and the first p-type polycrystalline silicon film 7 b ₁ formed on the first polycrystalline silicon film 17, and a second polycrystalline silicon film 20
The second n-type polycrystalline silicon film 7a ₂ formed in
Since it is provided a minimum narrow connecting region L ₂ of the type polycrystalline silicon film 7b _2, even if disconnection Ti silicide film 5b, this disconnection is likely to occur on the connecting area L _1, L ₂ Lower. Thereby, the gate electrodes 7a, 7
The defect occurrence rate at which the resistance of b increases can be reduced.

[0069] In the second embodiment, although the first 1n-type polycrystalline silicon film impurity concentration and the 1p type 7a ₁ polycrystalline silicon film 7b and the impurity concentration of ₁ same, one of the impurity concentration other If the resist film 23 and the resist film 24 overlap each other without being coincident with each other, a low-concentration impurity region is formed without forming a non-doped region. Increase can be suppressed.

(Embodiment 3) FIG. 14 is a layout diagram of a gate electrode of a CMOS device according to another embodiment of the present invention.

As shown in the figure, an n-channel type MISFE
TQn gate electrode 7a and p-channel MISFET Q
The width of the region connected to the p gate electrode 7b is relatively thicker than the gate length. That is, the n-channel type MI formed on the first polycrystalline silicon film 17 is formed.
An n-channel MISFET Qn formed in the connecting region L ₁ between the _first n-type polycrystalline silicon film 7a ₁ of the SFET Qn and the first p-type polycrystalline silicon film 7b ₁ of the p-channel MISFET Qp, and the second-layer polycrystalline silicon film 20 the 2n-type polycrystalline silicon film 7a ₂ and p-channel type MIS of
The connecting region L ₂ between the first 2n-type polycrystalline silicon film 7b ₂ of FETQp, a region having a disconnection hard width at the grain boundaries of the Ti silicide film 5b.

The impurity concentration of the _first n-type polycrystalline silicon film 7a1 forming a part of the gate electrode 7a of the n-channel MISFET Qn is
The impurity concentration may be set to be equal to or relatively higher than the impurity concentration of the _first p-type polycrystalline silicon film 7b1 forming a part of the p gate electrode 7b.

As described above, according to the third embodiment, by increasing the width of the connection regions L ₁ and L ₂ , the probability that the resistance of the gate electrodes 7 a and 7 b increases can be reduced. For example, the aggregation generation density when the width of the connecting region is 0.2 μm is about 0.1 particles / μm, but by setting the width of the connecting region to 0.25 μm or more, the occurrence rate of aggregation can be reduced to 1/15. If it is 0.35 μm or more, the occurrence of aggregation can be almost completely suppressed.

(Embodiment 4) FIG. 15 is a plan view and a sectional view of a main part of a semiconductor substrate showing a gate electrode of a CMOS device according to another embodiment of the present invention. FIG.
5 (a) is a plan view of a main part, FIG. 15 (b) is a cross-sectional view of the main part along line DD 'in FIG. 15 (a), and FIG. 15 (c).
FIG. 3 is a sectional view of an essential part taken along line EE ′ of FIG.

A sidewall spacer 8 is provided on the side wall of the gate electrode 7a of the n-channel MISFET Qn and on the side wall of the gate electrode 7b of the p-channel MISFET Qp. However, the n-channel MISFE
TQn gate electrode 7a and p-channel MISFET Q
Sidewall spacers 8 are provided on the side walls of the stacked film including the second-layer polycrystalline silicon film 20 and the first-layer polycrystalline silicon film 17 in the connection regions L ₁ and L ₂ connected to the p gate electrode 7 b.
Is not provided, and the Ti silicide film 5
The Ti silicide film 5c of the same layer as that of the gate electrode b is formed, and the widths of the connection regions L ₁ and L ₂ between the gate electrode 7a of the n-channel MISFET Qn and the gate electrode 7b of the p-channel MISFET Qp are effectively increased. .

Next, the manufacturing method of the fourth embodiment will be described with reference to FIG.
This will be briefly described with reference to FIG.

First, in Embodiment 1, FIG.
10, the high-concentration n ⁺ -type semiconductor region 4 constituting the source and drain of the n-channel MISFET Qn is formed, and at the same time, the second n-type semiconductor region constituting a part of the gate electrode 7a is formed. Type polycrystalline silicon film 7
a ₂ is formed to form a high-concentration p ⁺ -type semiconductor region forming the source and drain of the p-channel type MISFET Qp, and at the same time, a second portion forming a part of the gate electrode 7b.
forming a p-type polycrystalline silicon film 7b _2.

Note that the impurity concentration of the _first n-type polycrystalline silicon film 7a1 forming a part of the gate electrode 7a of the n-channel MISFET Qn is
The impurity concentration may be set to be equal to or relatively higher than the impurity concentration of the _first p-type polycrystalline silicon film 7b1 forming a part of the p gate electrode 7b.

Next, as shown in FIG. 16, after the region where the n-channel MISFET Qn is formed and the region where the p-channel MISFET Qp are formed are covered with a patterned resist film 27, the n-channel MISFE is formed.
The sidewall spacers 8 provided on the side walls of the stacked film including the second-layer polycrystalline silicon film 20 and the first-layer polycrystalline silicon film 17 in the connection regions L ₁ and L ₂ between the TQn and the p-channel type MISFET Qp are removed. I do.

Thereafter, as shown in FIG. 15, the surface of the n ⁺ type semiconductor region 4 constituting the source and drain of the n channel type MISFET Qn and the p channel type MISFET Qn
A Ti silicide 5a is formed on the surface of the p ⁺ type semiconductor region constituting the source and drain of the ETQp, and a Ti silicide film 5b is formed on the surface of the second-layer polycrystalline silicon film 20 at the same time. Further, n-channel MISFETs Qn and p
Connection regions L ₁ and L ₂ with channel type MISFET Qp
The Ti silicide film 5 is formed on the side wall of the stacked film including the second-layer polycrystalline silicon film 20 and the first-layer polycrystalline silicon film 17.
c is formed.

As described above, according to the fourth embodiment, n
Since the widths of the connection regions L ₁ and L ₂ between the gate electrode 7a of the channel MISFET Qn and the gate electrode 7b of the p-channel MISFET Qp are effectively increased by the Ti silicide film 5c, the resistance of the gate electrodes 7a and 7b increases. Probability can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0083]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the n-channel type MISFE
Since the resistivity of the conductive film in the connection region located between the gate electrode of T and the gate electrode of the p-channel type MISFET can be reduced, and the increase in resistance in the connection region can be suppressed. An increase in resistance due to thinning can be suppressed.

According to the present invention, the n-channel MI
By shortening the length of the connection region between the gate electrode of the SFET and the gate electrode of the p-channel MISFET,
Even if aggregation occurs in the Ti silicide film in the connection region, the possibility of this disconnection occurring on the connection region is reduced, and an increase in resistance in the connection region can be suppressed.
It is possible to suppress an increase in resistance due to thinning of the gate electrode of the SFET.

According to the present invention, the n-channel MI
The width of the connection region between the gate electrode of the SFET and the gate electrode of the p-channel type MISFET is made relatively thicker on the layout than the gate length, or a Ti silicide film is provided on the side wall of the conductive film forming the connection region. By making the width of the connection region relatively larger than the gate length, the T region provided on the surface of the conductive film constituting the connection region is formed.
Even if agglomeration occurs in the i-silicide film, it is possible to reduce the probability that the Ti-silicide film is completely disconnected, thereby suppressing an increase in resistance in the connection region. Can be suppressed from increasing due to thinning of the wire.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of a main part of a semiconductor substrate showing a CMOS device according to a first embodiment of the present invention;

FIGS. 2A and 2B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, showing the method for manufacturing the CMOS device according to the first embodiment of the present invention;

FIGS. 3A and 3B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the first embodiment of the present invention;

FIGS. 4A and 4B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the first embodiment of the present invention;

5A and 5B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, showing the method for manufacturing the CMOS device according to the first embodiment of the present invention;

6A and 6B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the first embodiment of the present invention;

7A and 7B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, showing the method for manufacturing the CMOS device according to the first embodiment of the present invention;

8A and 8B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the first embodiment of the present invention;

FIGS. 9A and 9B are a main part plan view and a main part cross-sectional view of the semiconductor substrate showing the method for manufacturing the CMOS device according to the first embodiment of the present invention;

10A and 10B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the first embodiment of the present invention;

11A and 11B are a main part plan view and a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the CMOS device according to the first embodiment of the present invention;

FIG. 12 is a plan view and a cross-sectional view of main parts of a semiconductor substrate showing a method for manufacturing a gate electrode of a CMOS device according to a second embodiment of the present invention;

FIG. 13 is a plan view and a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a gate electrode of a CMOS device according to a second embodiment of the present invention;

FIG. 14 is a layout diagram of a gate electrode of the CMOS device according to the third embodiment of the present invention;

FIG. 15 is a plan view and a cross-sectional view of a main part of a semiconductor substrate showing a gate electrode of a CMOS device according to a fourth embodiment of the present invention.

16A and 16B are a main part plan view and a main part sectional view of a semiconductor substrate showing a method for manufacturing a gate electrode of a CMOS device according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2a isolation trench 2b silicon oxide film 3 p-type well 4 n ⁺ -type semiconductor regions 5a titanium silicide film 5b titanium silicide film 5c titanium silicide film 6 gate insulating film 7 a gate electrode 7a gate electrode 7a ₁ second 1n-type polycrystalline Silicon film 7a ₂ Second n-type polycrystalline silicon film 7b Gate electrode 7b ₁ First p-type polycrystalline silicon film 7b ₂ Second p-type polycrystalline silicon film 8 Sidewall spacer 9 N-type well 11 Interlayer insulating film 12a Contact hole 12b Contact hole Reference Signs List 13 plug 14 wiring layer 15 silicon oxide film 16 silicon nitride film 17 first layer polycrystalline silicon film 18 resist film 19 resist film 20 second layer polycrystalline silicon film 21 resist film 22 resist film 23 resist film 24 resist film 25 resist film 26 Resist 27 resist film L ₁ connecting region L ₂ connecting region Qn n-channel type MISFET Qp p-channel type MISFET

Continued on the front page (72) Inventor Fumio Otsuka 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Kenichi Kikushima 3-16-6 Shinmachi, Ome-shi, Tokyo 4M104 AA01 BB01 BB18 BB25 BB28 CC01 CC05 DD02 DD37 DD63 EE03 EE06 FF14 FF21 GG09 GG14 HH14 HH16 5F048 AA01 AC03 BB06 BB07 BB08 BB13 BB18 BE03 BF04BF05

Claims (10)

[Claims] 1. A semiconductor device comprising: a conductive film having the same layer and a connecting region interposed therebetween;
A semiconductor integrated circuit device provided with a region into which a p-type impurity is introduced and a region into which a p-type impurity is introduced, wherein a resistance of an electrode formed of the conductive film is reduced by a silicide film. An impurity concentration of the connection region is 1 × 1
A semiconductor integrated circuit device having a ^{diameter of} 0 ²⁰ cm ^-3 or more. 2. A conductive film of the same layer having n
A semiconductor integrated circuit device provided with a region into which a p-type impurity is introduced and a region into which a p-type impurity is introduced, wherein a resistance of an electrode formed of the conductive film is reduced by a silicide film. A semiconductor integrated circuit device, wherein the length of the connection region is shorter than the grain size of the silicide film. 3. A conductive film of the same layer, n
A semiconductor integrated circuit device provided with a region into which a p-type impurity is introduced and a region into which a p-type impurity is introduced, wherein a resistance of an electrode formed of the conductive film is reduced by a silicide film. A semiconductor integrated circuit device, wherein the width of the connection region is relatively larger than the width of the region into which the n-type impurity is introduced or the width of the region into which the p-type impurity is introduced. 4. A conductive film of the same layer, n
A semiconductor integrated circuit device provided with a region into which a p-type impurity is introduced and a region into which a p-type impurity is introduced, wherein a resistance of an electrode formed of the conductive film is reduced by a silicide film. A semiconductor integrated circuit device, wherein a silicide film is formed on a side wall of the conductive film in the connection region. 5. The semiconductor integrated circuit device according to claim 2, wherein the connection region is an effective non-doped region or a semiconductor region having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more. A semiconductor integrated circuit device characterized by the above-mentioned. 6. The semiconductor integrated circuit device according to claim 3, wherein the width of the connection region is 0.2 μm or more. 7. A semiconductor integrated circuit device in which an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation and a p-type impurity is introduced into the other side of the conductive film by ion implantation. Providing a difference of 1 × 10 ¹⁵ cm ⁻² or more between the dose of the ion implantation of the n-type impurity and the dose of the ion implantation of the p-type impurity; A method of manufacturing a semiconductor integrated circuit device, wherein the ion implantation of the p-type impurity is overlapped. 8. A semiconductor integrated circuit device, wherein an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation, and a p-type impurity is introduced into the other side of the conductive film by ion implantation. A method wherein a boundary between a first resist film used as a mask when introducing the n-type impurity and a second resist film used as a mask when introducing the p-type impurity substantially coincides with each other.
A method for manufacturing a semiconductor integrated circuit device, wherein the first resist film and the second resist film are disposed. 9. Manufacturing of a semiconductor integrated circuit device in which an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation and a p-type impurity is introduced into the other side of the conductive film by ion implantation. A width of a conductive film in a connecting region located between the region into which the n-type impurity is introduced and the region into which the p-type impurity is introduced, by changing the width of the conductive film in the region into which the n-type impurity is introduced. Membrane width or p
A method for manufacturing a semiconductor integrated circuit device, comprising processing a semiconductor film to be relatively thicker than a width of a conductive film in a region into which a type impurity is introduced. 10. Manufacturing a semiconductor integrated circuit device in which an n-type impurity is introduced into one side of a conductive film provided on a semiconductor substrate by ion implantation and a p-type impurity is introduced into the other side of the conductive film by ion implantation. A method of forming an electrode composed of the conductive film; (b) a step of forming a sidewall spacer on a side wall of the electrode; and (c) a method of forming the n-type impurity. Removing the sidewall spacer on the side wall of the electrode in the connection region located between the region into which the p-type impurity is introduced and the region into which the p-type impurity is introduced;
(d) forming a silicide film on the upper surface of the electrode in the region where the n-type impurity is introduced and the region where the p-type impurity is introduced by the self-alignment method, and on the upper surface and the side wall of the electrode in the connection region; A method for manufacturing a semiconductor integrated circuit device, comprising: