JP2001056918A - Recording disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a recording disk device capable of suppressing a clock signal frequency which is required for the asynchronous sampling of the servo control information at a comparatively low level. SOLUTION: A polyphase clock 46 is produced by a polyphase clock producing circuit 45 in a servo control system of the recording disk device. By a synchronizing circuit 25, this polyphase clock signal is latched on the basis of an input data pulse 35, and on the basis of this latch result, the decision is made by expressing the phase of the input data pulse in terms of the phase of the polyphase clock signal, and a sampling clock signal is selected from the polyphase clock signal in accordance with this decision result. Then the synchronization is executed by the selected clock signal. Consequently, the synchronized sampling with the N-fold accuracy is realized by the polyphase clock signal of the M phase of the frequency with the N/M-fold speed, and the synchronization of a comparatively higher speed servo is signal accurately realized in a short period by a small scaled circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a recording disk device such as a magnetic disk device, and more particularly to clock synchronization of servo control information for tracking servo read from a recording disk.

[0002]

2. Description of the Related Art An information track is formed on a recording disk of a magnetic disk device such as a hard disk device, and the track has a data area and a servo area. In the servo area, servo control information such as cylinder position information and information indicating a deviation from the center position of the cylinder is recorded. The magnetic head reads out their position information from the servo area. The read position information is converted into a signal pulse by a signal processing unit, for example, and is supplied to the servo control circuit as a detection pulse of the servo control information. The servo control circuit controls the position of the head based on the information of the input detection pulse.

In order to make the servo control circuit recognize the detection pulse, the detection pulse is synchronized by asynchronous sampling with a sampling clock signal whose speed is several times (or ten and several times) the signal frequency. I have.

[0004]

However, when the servo area is reduced to increase the data area, the signal frequency of the servo control information in the servo area is increased accordingly. Then, in order to guarantee a certain sampling accuracy, the frequency of the sampling clock signal must be increased according to the signal frequency of the servo control information.
For example, when the signal frequency of the servo control information is 10 MHz, the frequency of the sampling clock signal is 80 MHz in order to increase the sampling accuracy to 8 gradations (8 times). Generating such a high-frequency clock signal requires high cost.

It is an object of the present invention to provide a servo control technique capable of keeping the frequency of a clock signal required for asynchronous sampling of servo control information relatively low.

Another object of the present invention is to provide a recording disk device such as a magnetic disk device which can reduce the cost for asynchronous sampling of servo control information.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] In a servo control system of a recording disk device such as a magnetic disk device, a multi-phase clock signal is supplied from a ringing oscillator or the like constituting a VCO (voltage controlled oscillator) of a PLL (phase locked loop) synthesizer. Then, the multi-phase clock signal is latched by the input data pulse. The phase of the input data pulse is detected from the latch result, and one clock signal is selected from the multi-phase clock signal to be used as a synchronous clock for sampling the data pulse. The input data pulse is latched by the selected synchronization clock to obtain a synchronized data output.

In this configuration, when the input data pulse is sampled with N times accuracy, it has conventionally been necessary to generate a clock signal at N times speed with respect to the signal frequency of the data pulse. On the other hand, in the above-mentioned means, for example, an M-phase multi-phase clock signal is generated from the ring oscillator of the VCO (if the ring oscillator is differential, it can be realized in an M / 2-stage configuration), and the frequency is raised too much. Instead, only the number of phases of the clock signal is increased, so that N-times-precision synchronized sampling can be realized with a clock signal having a frequency of N / M times. Conventionally, a clock having a frequency of N times the signal frequency (or data speed) of the servo control information was required. However, it is possible to achieve the same sampling accuracy by using a clock having a frequency of N / M times. High-speed servo signal synchronization can be realized with high accuracy in a short time by a small-scale circuit. An ultra-high-speed sampling clock is not required, and the cost for asynchronous sampling of servo control information in the recording disk device can be reduced.

[2] The entire recording disk device will be described in more detail. A recording disk device such as a magnetic disk device includes a head for reading / writing a disk-shaped recording disk having an information track, a head actuator for moving the head, and a head for driving the head to read / write the information track. And a signal processing means for information read by the read / write circuit and information to be written by the read / write circuit, and data of servo control information included in the information read by the read / write circuit A pulse generating unit for generating a pulse, a synchronizing unit for synchronizing a data pulse output from the pulse generating unit with a clock signal and outputting the same, and the head based on the synchronization data output from the synchronizing unit. Servo control means for following the information track. The servo control information is stored in a servo area paired with a data area of the information track,
For example, the information includes information indicating the position of the cylinder and information indicating a deviation from the center position of the cylinder. The synchronizing means includes a plurality of second phases having mutually different phases from the first clock signal.
A multi-phase clock generation circuit for generating a clock signal of the second type, a cook selection circuit for receiving the second clock signal, selecting one of the second clock signals, and outputting the selected one of the second clock signals; A phase detection circuit that forms a selection signal; and a synchronization output circuit that synchronizes the data pulse with a second clock signal selected by the clock selection circuit and outputs the synchronization data. Thus, when sampling a data pulse with N times the precision of the frequency of the data pulse, the frequency of the second clock signal for sampling is represented by the following formula: N for the frequency of the pulse
/ M times. Therefore, relatively high-speed servo signal synchronization can be achieved with a small-scale circuit in a short period of time and with high accuracy.
Since an ultra-high-speed sampling clock is not required, the cost for asynchronous sampling of servo control information in the recording disk device can be reduced.

The phase detection circuit includes, for example, a clock latch circuit that latches the second clock signal of the plurality of phases in synchronization with a predetermined change of the data pulse, and a plurality of bits of data latched by the clock latch circuit. A phase determining circuit that determines the phase of the data pulse by converting the phase of the data pulse into the phase of the second clock signal based on the second clock signal and the second clock signal according to the phase determined by the phase determining circuit. And a calculation circuit for a selection signal to be selected.

The phase detection circuit further includes, for example, a selection latch circuit that latches a selection signal output from the arithmetic circuit and provides the selection signal to the selection circuit and the arithmetic circuit. When the second clock signal selected by the selection signal fed back from the selection latch circuit and the second clock signal corresponding to the phase determined by the phase determination circuit are equal to each other, A second clock signal selected by the selection signal fed back from the selection latch circuit and a second clock signal corresponding to the phase determined by the phase determination circuit. If the signal does not match, a new clock signal having a unit phase difference in the direction of the phase determined by the phase determination circuit with respect to the second clock signal selected by the selection signal fed back from the selection latch circuit. A selection signal for selecting the second clock signal is generated. According to this, the phase difference between the currently selected second clock signal and the newly selected second clock signal is limited to a unit phase difference between the second clock signals even at the maximum. Therefore, it is possible to easily prevent a situation where the cycle of the second clock signal temporarily becomes too long or too short when the second clock signal is switched. In order to generate a latch timing of the selection signal by the latch circuit for that,
A latch control circuit is provided, and the latch control circuit receives, for example, the second clock signal of the plurality of phases and a selection signal of the selection latch circuit, and the selection signal responds to a currently selected second clock signal. The latch timing may be generated with a constant phase difference.

The multi-phase clock generation circuit may be constituted by a PLL synthesizer having a control oscillator in a feedback loop, for example. The controlled oscillator has output nodes at different locations of the oscillation loop for generating the multi-phase second clock signals. A multi-phase clock signal having a desired frequency can be generated relatively easily.

[0015]

FIG. 2 shows an entire magnetic disk drive according to an example of the present invention. The magnetic disk device 1 shown in FIG. 1 has a plurality of magnetic disks 2 concentrically fixed to a spindle, and the spindle is driven to rotate by a disk motor 3. The read / write head 4 stores a pair of a read MR element (MRH) and a write inductance element (INDH) on the magnetic disk 2.
Have every. FIG. 2 typically shows one pair of an MR element (MRH) and an inductance element (INDH). The read / write circuit 5 includes a bias circuit for driving the MR element (MRH), a read amplifier for amplifying information read by the MR element (MRH), a write amplifier for driving the inductance element (INDH), and a control logic thereof. Have.

The read / write head 4 is supported by a head actuator 6. The servo circuit 7 controls rotation of the disk motor 3 and tracking control of the read / write head 4 with respect to the head actuator 6.
Do.

A signal processing circuit 8 such as a digital signal processor performs filtering and decoding of a signal read from the read / write circuit 5 and coding of write data via the read / write circuit 5.

Control of the read-dry circuit 5, the signal processing circuit 8 and the servo circuit 7 is performed by a control circuit 9.
The control circuit 9 includes a CPU (central processing unit), a RAM (random access memory) serving as a work area of the CPU or a temporary storage area for data, and a C (not shown).
It has a ROM (read only memory) storing a PU operation program, a serial interface, a parallel interface, a D / A converter, and the like. For example, the control circuit 9 is configured by a single-chip microcomputer. The control circuit 9 includes an external host device 10
It controls the magnetic disk device 1 as a whole according to commands supplied from the host device and controls the transfer of control information and data to and from the host device 10.

FIG. 3 illustrates an information format of a disc. A plurality of tracks are formed concentrically on each disk 2. As illustrated in FIG. 3, servo areas 11 and data areas 12 are alternately assigned to each track. The servo area 11 has a preamble, a servo mark, a gray code, and burst data. The preamble is data corresponding to a waiting time until read data is stabilized. The servo mark is information indicating the start of a subsequent gray code. The gray code is information indicating the position of the cylinder on the disk 2. The burst data is information indicating a deviation from the center position of the cylinder. The gray code and the burst data are used as substantial servo control information.

FIG. 1 mainly shows the signal processing circuit 8 and the servo circuit 7 in relation to tracking control.

First, a data read / write system in the signal processing circuit 8 will be described. A read signal 21R from the magnetic disk 2 is output from the read / write circuit 5. The read signal 21R is the servo control information read from the servo area 11 and the data signal read from the data area 12. The read signal 21R is gain-adjusted by an AGC (auto gain control) circuit 22 and supplied to an active filter 23. The active filter 23 performs high-frequency noise removal and waveform shaping.
That is, the active filter 23 has a low-pass filter (low-pass) function of cutting high-frequency components and a function of differentiating a low-pass signal. The low-pass component is converted into a digital signal by an ADC (analog-to-digital converter) 28, which is supplied to a code decoder 31 via a FIR (finite impulse response) filter 29 and a Viterbi decoder 30, and is included in the read signal 21R. The reproduction of the data signal is performed. The write data is encoded by the encoder 32, the write timing is adjusted by the write compensator 33, and the write data is supplied to the read / write circuit 5 as a write signal 21W. The write-system operation clock signal 43W is generated by the write synthesizer 43 to which the reference clock signal 47 is input. The read-system operation clock signal 44R is generated by a read PLL circuit 44 to which the output of the write synthesizer 43 is input.

Next, the servo control system will be described. First, a gray code detection system will be described. The signal processing circuit 8
, The differential signal of the low-pass component by the active filter 23 is supplied to the peak pulse detection circuit 24.
The peak pulse detection circuit 24 is a pulse generation unit that detects peaks as the maximum and minimum points of the input signal and generates a pulse for each detected peak. This pulse becomes the data pulse 35 of the servo control information. Servo circuit 7
Inputs the data pulse 35. The servo circuit 7 has a synchronization circuit 25, and the peak pulse detection circuit 24
The data pulse 35 output from the synchronous clock signal 3
The data is output to the gray code detection circuit 26 as the synchronization data 39 synchronized with 8. The gray code detection circuit 26
The gray code is detected from the synchronization data 39 supplied thereto and supplied to the servo control logic 40. Although details will be described later, the synchronization circuit 25 performs the synchronization by using a multi-phase cook signal 46 generated by the servo clock synthesizer 45. Servo clock synthesizer 4
5 generates a multi-phase cook signal 46 based on the reference clock signal 47.

The servo circuit 7 has an accumulator 41 and a clock selection circuit 42 as a processing system for burst data. The accumulator 41 is the ADC
The burst data in the servo area 11, which has been converted into a digital signal by 28, is integrated and given to the servo control logic 40. The clock selection circuit 42 selects the synchronous clock 38 at the time of servo control, and
And an operation clock for the accumulator 41, and during a read operation, a read system clock signal 44R is selected and the DAC
28 operation reference clock.

The servo control logic 40 recognizes the target position of the cylinder to which the read / write head 2 is to follow based on the synchronization data 39 output from the synchronization circuit 25, and outputs the target position from the accumulator 41. The deviation amount from the target cylinder position is grasped from the integration result, and the head actuator 6 is controlled so that the read / write head 4 follows the track of the target cylinder.
Control.

FIG. 4 exemplifies the synchronization circuit 25 and the servo clock synthesizer 45.

The servo clock synthesizer 45 includes a prescaler 51 as a variable frequency divider, a frequency phase comparison circuit 52, a loop filter 53, and a voltage controlled oscillator (VC
O), the output clock signal of the voltage controlled oscillator 54 is fed back to the prescaler 51, synchronized with the phase of the reference clock signal 47, and the frequency of the frequency defined by the prescaler 51 with respect to the reference clock signal 47. A phase clock signal 46 is generated. Although not particularly limited, the multi-phase clock signal 46 has M phases.

The synchronization circuit 25 comprises a data pulse generation circuit 60, a phase detection circuit 61, a sampling clock selection circuit 62, and a synchronization output circuit 63. The sampling clock selection circuit (clock selection circuit) 62 receives the multi-phase clock signal 46, selects one of them, and outputs it. The data pulse generation circuit 60 outputs the data pulse 35 with the pulse width thereof adjusted to a prescribed pulse width, for example, a pulse width for the RZ encoding method. The phase detection circuit 61 detects the phase of the data pulse 35A output from the data pulse generation circuit 60 and forms a selection signal for the sampling clock selection circuit 62. The synchronization output circuit 63 outputs the synchronization data 39 by synchronizing the data pulse 35A with the clock signal 38 selected by the sampling clock selection circuit 62.

FIG. 5 shows an example of the voltage controlled oscillator 54. Although not particularly limited, the voltage controlled oscillator 54 includes four differential input / output amplifiers 71 to 74, and outputs the inverted output of the preceding amplifier to the non-inverting input terminal of the next amplifier and the non-inverting input terminal of the preceding amplifier. A ring oscillator having two feedback loops is formed by sequentially connecting the output of the final-stage amplifier 74 to the input of the first-stage amplifier 71 while sequentially connecting the output to the inverting input terminal of the next-stage amplifier. The operating power of the amplifiers 71 to 74 is controlled by a frequency control current (frequency control voltage) 75, whereby the frequency and phase of the outputs of the differential input / output amplifiers 71 to 74 are controlled. The multi-phase clock signal 46 is formed by buffering the differential outputs of the respective differential input / output amplifiers 71 to 74, and becomes eight-phase clock signals CKPH1 to CKPH8 sequentially shifted in phase by a unit phase difference. Assuming that the period of each of the clock signals CKPH1 to CKPH8 is T, the unit phase is T / 8.

As will be described later in detail, it is better to increase the number of phases of the multiphase clock signal 46 in order to increase the synchronization accuracy of the synchronization circuit 25. This is because the unit phase becomes smaller. To increase the number of phases of the multi-phase clock signal 46, the voltage-controlled oscillator 5
It is sufficient to increase the operating frequency by increasing the number of serial stages of the differential input / output amplifiers 4 and increase the operating frequency. However, if all of them depend on the servo clock synthesizer 45, the cost will increase, or the servo clock synthesizer 45 will be replaced by a clock generation circuit of another circuit. In some cases, the operating frequency cannot be increased due to restrictions on diversion. At this time, as illustrated in FIG. 6, a voltage control oscillator 54A that generates an L (L <M) -phase multiphase clock signal 46A is employed, and the L-phase multiphase clock signal 46A is frequency-divided. A frequency dividing circuit 64 for generating an M-phase multiphase clock signal 46 may be provided, and the M-phase multiphase clock signal 46 of the frequency dividing circuit 64 may be supplied to the sampling clock selection circuit 62. Although not particularly shown, the frequency dividing circuit 64 can be constituted by a known multi-stage connected logic gate circuit, as long as the frequency dividing ratio of M / L is set.

FIG. 7 shows a detailed example of the phase detection circuit 61 and the synchronization output circuit 63. The phase detecting circuit 61 synchronizes with the predetermined change (for example, a rising change) of the data pulse 35A to generate the multi-phase clock signal CKP.
H1 to CKPH8 are latched, and 8-bit data D1 is latched.
To D8. In the subsequent stage, a phase determination circuit 90, an arithmetic circuit 91,
A latch circuit 92 and a latch control circuit 93 are provided.

The phase determination circuit 90 is provided with a plurality of bits of data D1 latched by the clock latch circuits 81 to 88.
ＤD8, the phase of the data pulse 35A is converted into the phase of the multiphase clock signals CKPH1 to CKPH8 for determination. That is, the latch data D1 to D8 of the clock latch circuits 81 to 88 change from “1” (High = high level) to “0” (Low =
Low level). For example, if CKPH8 = "1" and CKPH7 = "0" at time t0 in FIG. 8, D8 = "1" and D7 = "0", and the position of the upper bit (D8 Only the position) is set to “1” (E8 = “1”) so that the phase determination circuit 9
0 outputs 8-bit data (phase determination data) E1 to E8.

The sampling clock selection circuit 62 selects one of the multi-phase clocks CKPH1 to CKPH8 according to the selection signals S1 to S8 output from the latch circuit 92. The selection signals S1 to S8 are multiphase clocks CKPH
1 to CKPH8 are instructed to make a selection on a one-to-one basis, and one of them is set to the selection level "1".

The operation circuit 91 receives the phase judgment data E1 to E8 from the phase judgment circuit 90 and the selection signals S1 to S8 from the latch circuit 92. The arithmetic circuit 91
When the multi-phase clock signal selected by the selection signals S1 to S8 fed back from the latch circuit 92 is equal to the multi-phase clock signal determined by the determination data E1 to E8, the equal multi-phase clock signal Are output so that the selection signals S1 to S8 are selected. The arithmetic circuit 9
1 indicates that the multi-phase clock signal selected by the selection signals S1 to S8 returned from the latch circuit 92 does not match the multi-phase clock signal determined by the phase determination data E1 to E8. A new multi-phase clock signal having a unit phase difference in the direction of the phase determined by the phase determination circuit 90 with respect to the multi-phase clock signal selected by the selection signals S1 to S8 fed back from the circuit 92 is selected. The selection signals S1 to S8 are output. For example,
When the selection signals S1 to S8 are selecting the multi-phase clock CKPH1, the phase determination data E1 to E8 are
= "1" and the clock signal CKPH by E7 = "0"
8, the clock signal C is output by S8.
The selection signals S1 to S8 are formed so as to select KPH8. Also, the selection signals S1 to S8 are multi-phase clocks CKP
In a state where H1 is selected, the phase determination data E1
When E8 to E8 indicate the clock signal CKPH7 by E7 = "1" and E6 = "0", the selection signal S1 is selected so that the clock signal CKPH8 is selected by S8.
To S8. In the state where the selection signals S1 to S8 select the multi-phase clock CKPH1, if the phase determination data E1 to E8 indicate the clock signal CKPH2 by E2 = "1" and E1 = "0", S
2 to select the clock signal CKPH2,
The selection signals S1 to S8 are formed.

The latch control circuit 93 generates a latch timing signal 94 of the selection signals S1 to S8 by the latch circuit 92. The latch control circuit 93 receives the multi-phase clock signals CKPH1 to CKPH8 and the selection signals S1 to S8 output from the latch circuit 92, and the selection signal is fixed with respect to the currently selected multi-phase clock signal. The latch timing signal 94 is enabled at the timing when the unit phase difference (T / 8) has elapsed since the falling edge of the latch timing signal 94, for example.

The synchronous output circuit 63 includes, but not limited to, two edge trigger type latch circuits 95 and 96 for latching data at the rising edge of a clock terminal. The data pulse 35A is applied to the clock terminal of the preceding latch circuit 95, the "1" signal is supplied to the data input terminal, and the data output terminal is coupled to the data input terminal of the next latch circuit 96. The synchronous clock 38 is supplied to a clock terminal of the latch circuit 96, and synchronized data 39 is obtained at a data output terminal thereof. The latch circuit 95 is reset by the change of the signal obtained by inverting the synchronization data 39 by the inverter 97 from "1" to "0", whereby the data output terminal is forced to "0".

FIG. 8 exemplifies the operation timings of the phase detection circuit 61 and the synchronization output circuit 63. The eight-phase clock signals CKPH1 to CKPH8 obtained from the servo clock synthesizer 45 are each T / 8 with respect to the period T.
Out of phase. In the example of FIG. 8, the clock signal C is first used as the synchronous clock (sampling clock).
KPH1 is selected. Data pulse 3 at time t0
When 5A rises and changes, the 8-phase clock signal C
The logic value data of KPH1 to CKPH8 are latched by the clock clutch circuits 81 to 88. The phase determination circuit 90 receives the data D1 to D8, converts the phase of the data pulse 35A into the phase of the eight-phase clock signals CKPH1 to CKPH8, and determines them, thereby generating phase determination data E1 to E8. In the case of FIG. 8, the phase determination data E1 to E8 are E8 =
“1” means that the phase of CKPH8 is the conversion determination phase. The latch circuit 92 issues an instruction to select the clock signal CKPH1 according to the selection signals S1 to S8 of S1 = "1". The clock signal CKPH1 specified by this is the clock signal C of the conversion determination phase.
The operation circuit 91 differs from KPH8 in that the phase difference between them is the unit phase T / 8, so that the arithmetic circuit 91 selects new clock signals CKPH8 based on S8 = "1".
8 is output. Although not particularly limited, here, the time t
A period T or more, for example, 9T /
It takes eight hours. Therefore, the synchronous clock is switched from the clock signal CKPH1 to the clock signal CKPH8 at the latch timing of the time t2 by the latch control circuit 93. As described above, the switching timing is set to the “0” period in the current synchronous clock, and the “1” period is not abnormally lengthened during switching.

The data sampling timing of the synchronous output circuit 63 is the rising edge of the synchronous clock signal. The latch circuit 95 latches “1” in synchronization with the rise of the data pulse at time t0. The latch data "1" is latched by the latch circuit 96 at the data sampling timing at time t1, and the synchronization data is set to "1". , When the synchronization data is set to “1”,
The latch circuit 95 has been reset to the “0” output state. At the next data sampling timing (time t3), the latch circuit 96 latches the output “0” of the latch circuit 95 in the reset state. Hereinafter, the synchronization data is generated in the same manner.

9 and 10 show details of the operation of the arithmetic circuit 91. As described above, the arithmetic circuit 91 performs one clock switch only for one gradation corresponding to the unit phase T / 8. In the example of FIG. 9, since the difference between the detection phase and the initial selection clock is one gradation, the next selection clock is switched to CKPH8 which is the detection phase. In the second phase comparison in FIG. 9, the same selected clock is maintained because the detected phase and the previous selected clock are the same.

In the case of FIG. 10, in the first phase comparison, the difference between the detected phase and the initially selected clock is two gradations (T / 8/2).
Times). Therefore, as a result of the first phase comparison, the clock to be selected next is switched by only one gradation in the detection phase direction, and CKPH8 is selected. In the second phase comparison shown in FIG. 10, since the difference between the detected phase and the initial selected clock is one gradation, the next selected clock is the detected phase CKPH7.
It is said.

As described above, by switching the clock in units of one gradation, the generation of the switching timing, in other words, the control of the latch timing of the latch circuit 92 is not complicated, and as described above, It is possible to easily prevent the "1" period from being abnormally long or short at the time of switching.

FIG. 11 is a block diagram of a computer device 100 on which the magnetic disk device 1 is mounted.
In the computer device 100, the microprocessor 101 is not particularly limited, but the system bus 10
2 through the PCI (Peripheral Component Interconnec
t) It is connected to the bus controller 103. The P
An internal bus (PCI bus) 104 conforming to the PCI bus standard is connected to the CI bus controller 103. The internal bus 104 has I as a peripheral controller.
A DE interface controller 105 and another interface controller 106 are connected. The magnetic disk device 1 is coupled to the IDE (Integrated Device Electronics) interface controller 105 via an interface cable. Said I
The DE interface controller 105 also controls the interface between the magnetic disk device 1 and the internal bus 104. The microprocessor 101, PCI bus controller 103, internal bus 104, IDE interface controller 105, and other interface controllers 106 constitute a processor board 110. The other interface controller 106 is, for example, a graphic accelerator or a Centronics interface controller for a parallel interface. Other interface controller 106
Other peripheral circuits 10 such as a display and a printer
7 is connected.

According to the magnetic disk device described above, the following functions and effects can be obtained.

(1) When a data pulse is sampled with N times the precision of the frequency of the data pulse, the frequency of the second clock signal for sampling is M, where the number of phases of the second clock signal 46 is M. In this case, the frequency is N / M times the frequency of the data pulse. Therefore, relatively high-speed synchronization of servo signals can be achieved with a small-scale circuit in a short period of time and with high accuracy, an ultra-high-speed sampling clock is not required, and the cost for asynchronous sampling of servo control information in a recording disk device is reduced. It is possible to keep it low.

(2) If the number of clock phases is increased by further dividing the multi-phase clock signal obtained from the ring oscillator of the voltage controlled oscillator 45 as shown in FIG. The improvement can be realized relatively easily.

(3) A multi-phase clock generation circuit is constituted by a PLL synthesizer, and the multi-phase clock signal is generated from different output nodes of an oscillation loop of a ring oscillator constituting the voltage-controlled oscillator to thereby obtain a desired frequency. The multi-phase clock signal can be generated relatively easily.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, the multi-phase clock signal may be generated using means other than the ring oscillator, for example, using a delay element. The multi-phase clock generation circuit is not limited to a PLL synthesizer. Further, there may be an error in the unit phase difference between the multi-phase clock signals. Further, the storage disk may be a magneto-optical disk or an optical disk.

[0048]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the servo control system of the recording disk device, a multi-phase clock is generated by a multi-phase clock generation circuit, and the synchronization circuit latches the multi-phase clock signal based on the input data pulse, and Based on the determination, the phase of the input data pulse is converted into the phase of the multi-phase clock signal, and the sampling clock signal is selected from the multi-phase clock signal according to the determination result, and the synchronization is performed with the selected clock signal. Synchronous sampling with N-fold accuracy can be realized with an M-phase multi-phase clock signal having an N / M-times frequency. Therefore, relatively high-speed servo signal synchronization can be realized with a small-scale circuit in a short period of time and with high accuracy. Since an ultra-high-speed sampling clock is not required, the cost for asynchronous sampling of servo control information in the recording disk device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram mainly showing a relationship between a signal processing circuit and a servo circuit and tracking control.

FIG. 2 is a block diagram showing the entirety of a magnetic disk drive according to an example of the present invention.

FIG. 3 is a format diagram showing an example of an information format of a magnetic disk.

FIG. 4 is a block diagram illustrating a synchronization circuit and a servo clock synthesizer;

FIG. 5 is a logic circuit diagram illustrating an example of a voltage controlled oscillator.

FIG. 6 is a block diagram showing another example in which a frequency dividing circuit for dividing an M-phase multi-phase clock signal to generate an N-phase multi-phase clock signal is provided in the configuration of FIG. 4;

FIG. 7 is a block diagram illustrating a detailed example of a phase detection circuit and a synchronization output circuit.

FIG. 8 is a timing chart showing operation timings of the phase detection circuit and the synchronization output circuit.

FIG. 9 illustrates a case where a difference between a detected phase and an initially selected clock phase is one gradation in a case where one clock switching is performed only for one gradation of a unit phase as an operation of an arithmetic circuit included in the phase detection circuit. It is operation | movement explanatory drawing.

FIG. 10 shows a case where a difference between a detected phase and an initially selected clock phase is two gradations in a case where one clock switching is performed only by one gradation of a unit phase as an operation of an arithmetic circuit included in the phase detection circuit. It is operation | movement explanatory drawing.

FIG. 11 is a block diagram showing an example of a computer device equipped with the magnetic disk device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Magnetic disk device 2 Magnetic disk 4 Read / write head 5 Read lao and circuit 6 Head actuator 7 Servo circuit 8 Signal processing circuit 9 Control circuit 11 Servo area 12 Data area 24 Peak pulse detection circuit 25 Synchronization circuit 35, 35A Data pulse 38 Synchronous clock 39 Synchronized data 40 Servo control logic 45 Servo clock synthesizer 46 Polyphase clock signal 47 Reference clock 54 Voltage controlled oscillator 60 Data pulse generation circuit 61, 61A Phase detection circuit 62, 62A Sampling clock selection circuit 63 Synchronization output circuit 64 minutes Circuits 71 to 74 Differential input / output amplifiers CKPH1 to CKPH8 Multiphase clock signals 81 to 88 Clock latch circuit 90 Phase determination circuit 91 Operation circuit 92 Latch circuit 93 Latch control circuit 94 Latch control signal D1 to D8 Clock latch data E1 to E8 Phase determination data S1 to S8 Selection signal

Claims (7)

[Claims] 1. A read / write head for a disk-shaped recording disk having an information track, a head actuator for moving the head, and a read / write for driving the head to read / write to the information track. A circuit, signal processing means for information read by the read / write circuit and information to be written by the read / write circuit, and a pulse for generating a data pulse of servo control information included in the information read by the read / write circuit Generating means, synchronizing means for synchronizing and outputting a data pulse output from a pulse generating means with a clock signal, and causing the head to follow the information track based on synchronized data output from the synchronizing means. A servo control unit, wherein the synchronization unit is a first clock signal. A multiphase clock generation circuit for generating a second clock signal of a different phase phases to each other, and enter the second clock signal,
A cook selection circuit for selecting and outputting one of them, a phase detection circuit for forming a selection signal for the clock selection circuit based on the phase of the data pulse, and a second clock signal selected by the clock selection circuit A synchronous output circuit for synchronizing the data pulse and outputting the synchronized data. 2. The clock detection circuit according to claim 1, wherein the phase detection circuit latches the second clock signal of the plurality of phases in synchronization with a predetermined change of the data pulse, and a plurality of bits of data latched by the clock latch circuit. A phase determining circuit that determines the phase of the data pulse by converting the phase of the data pulse into the phase of the second clock signal based on the second clock signal and the second clock signal according to the phase determined by the phase determining circuit. 2. The recording disk device according to claim 1, further comprising an operation circuit for selecting a selection signal. 3. The phase detection circuit further includes a selection latch circuit that latches a selection signal output from the arithmetic circuit and provides the selection signal to the selection circuit and the arithmetic circuit. When the second clock signal selected by the feedback selection signal is equal to the second clock signal corresponding to the phase determined by the phase determination circuit, a selection signal for selecting the same second clock signal is generated. If the second clock signal generated and selected by the selection signal fed back from the selection latch circuit does not match the second clock signal corresponding to the phase determined by the phase determination circuit, the selection is performed. A new second clock signal having a unit phase difference in the direction of the phase determined by the phase determination circuit with respect to the second clock signal selected by the selection signal fed back from the latch circuit. 3. The recording disk device according to claim 2, wherein a selection signal for selecting the second clock signal is generated. 4. A latch control circuit for generating a latch timing of the selection signal by the latch circuit, wherein the latch control circuit converts the second clock signal of the plurality of phases and a selection signal of the selection latch circuit. 4. The recording disk apparatus according to claim 3, wherein said latch timing is generated with a predetermined phase difference from a second clock signal which is inputted and selected by a selection signal. 5. The PLL synthesizer having a control oscillator in a feedback loop, wherein the multi-phase clock generation circuit comprises:
The recording according to any one of claims 1 to 4, wherein the control oscillator has output nodes for generating the second clock signals of the plurality of phases at different positions in an oscillation loop. Disk device. 6. The multi-phase clock generation circuit includes a PLL synthesizer having a control oscillator in a feedback loop and a frequency divider, wherein the control oscillator has an output node that generates an m-phase clock signal at a different position in the oscillation loop. The frequency divider divides the m-phase clock signal to generate an n-phase second signal.
5. The recording disk device according to claim 1, wherein the recording disk device outputs a clock signal of: 7. The servo control information is stored in a servo area paired with a data area of the information track, and includes information indicating a cylinder position and information indicating a deviation from a cylinder center position. 7. The recording disk device according to claim 1, wherein: