JPH10241307A - Digital servo signal processor, disk medium reproducing device and disk medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the accuracy of a servo position error signal without raising the number of bits of an analog/digital converter. SOLUTION: An analog full-wave rectifier circuit 50 and an analog switch 52 are connected to the output of the analog filter 2 of a signal processing circuit and the input of an analog/digital converter 3 is changed over by the analog switch 52. As a result, after a burst signal passes the analog full-wave rectifier circuit 50 to be converted into the signal subjected to a full-wave rectification, it is inputted to the analog/digital converter 3 to be converted into a digital signal having no sign. Besides, the signal other the burst signal is inputted to the analog/digital converter 3 without being passed through the full-wave rectifier 50 to be converted into a digital signal having a sign.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a servo signal processing apparatus, and more particularly, to a method for converting a servo signal into a digital signal using an analog-to-digital converter for data signal processing in a disk medium such as a magnetic disk or a magneto-optical disk. The present invention relates to a digital servo signal processing device, a disk medium reproducing device, and a disk medium that perform dynamic processing.

[0002]

2. Description of the Related Art Conventionally, as a servo signal processing device for a magnetic disk, a burst signal of a servo signal is processed using an analog circuit, and thereafter, the analog signal is processed by an analog-to-digital converter provided in a hard disk controller. An analog servo signal processing device that converts the burst signal into a digital signal and processes the digital signal is used.

In recent years, digital processing of a signal processing (data signal processing) circuit of a magnetic disk has been widely used. In particular, PRML (Partial Response Maximum Likeli
hood) is being used. In such a data signal processing method, a data signal processing circuit including an analog-to-digital converter and a digital signal processing circuit is used. First, a data signal is converted into a digital signal using an analog-to-digital converter, and then the digital signal is processed by a digital signal processing circuit.

Therefore, in recent years, the analog-to-digital converter and the digital signal processing circuit provided in the data signal processing circuit are also used for servo signal processing. Attempts have been made to increase efficiency, increase reliability, increase speed, and reduce the cost of magnetic disk drives.

A conventional digital servo signal processing apparatus for digitally processing a servo signal using an analog-to-digital converter and a digital signal processing circuit provided in a data signal processing circuit will be described below.

FIG. 22 is a schematic configuration diagram of a conventional digital servo signal processing device, and FIG. 23 is a diagram showing a servo signal processed by the conventional digital servo signal processing device shown in FIG. 22 and output when the servo signal is processed. FIG. 3 is a diagram for explaining main signal timings.

First, before describing the conventional digital servo signal processing device shown in FIG. 22, the configuration of a servo signal processed by the digital servo signal processing device will be described.

As shown in FIG. 23, the servo signal 150 is used for timing reproduction and AGC (Automatic Gain Coding).
a timing reproduction unit 151 which is a pattern for pulling in a servo signal, a servo address mark 152 for generating a timing for processing a servo signal, and a gray code 153 on which data such as a track number and a head number is written. The gap 154 and burst signals 155a and 155b (hereinafter, referred to as head position error signals) serving as head position error signals.
(Also simply referred to as a burst signal 155).

Next, a conventional digital servo signal processing device shown in FIG. 22 will be described.

A conventional digital servo signal processing apparatus has a VGA (Variable Gain Amp) 101 as shown in FIG.
, Analog filter 102, analog-to-digital converter 103, digital filter 104, and maximum likelihood decoder 1
05, a data decoder 106, and an input / output circuit 107
And

The VGA 101 is a magnetic disk (not shown)
This is a variable gain amplifier for keeping the signal amplitude level of the analog signal (servo signal and data signal) read out from the constant.

The analog filter 102 is a VGA 101
Is subjected to noise removal and waveform equalization.

The analog-to-digital converter 103 quantizes the output signal of the VGA 101 sent via the analog filter 102 and converts it into a digital signal.

The digital filter 104 equalizes the waveform of the output signal (digital signal) of the analog-to-digital converter 103.

The maximum likelihood decoder 105 is a digital filter 1
Analog-to-digital converter 10 sent via
3 is binarized.

The data decoder 106 is the maximum likelihood decoder 1
If the signal binarized in 05 is a data signal, the signal is decoded.

The input / output circuit 107 is a data decoder 1
06 and a gray code of a servo signal decoded by a servo decoder 109 described later,
The data is transmitted to the hard disk controller 108.

Further, the conventional digital servo signal processing apparatus shown in FIG. 22 uses a servo decoder 109 and a servo address mark detection circuit 11 for processing servo signals.
0, a sequencer 111, and an absolute value circuit 113, an adder 11
4, a latch circuit 117, and a register 112.

The servo address mark detection circuit 110
The signal binarized by the maximum likelihood decoder 105 is the servo signal 15
If 0, the servo address mark 152
Is detected. Then, a servo address detection signal 116 is output at the timing when the servo address mark is detected.

The servo decoder 109 decodes the gray code 153 based on the servo address detection signal 116 output from the servo address mark detection circuit 110.

The sequencer 111 generates a burst signal processing gate 118 for specifying the timing of burst signal processing based on the servo address detection signal 116 detected by the servo address mark detection circuit 110.

The absolute value circuit 113 includes the digital filter 1
When the output signal of the analog-to-digital converter 3 transmitted through the signal line 04 is a burst signal 155a or 155b,
The output signal is subjected to absolute value processing to obtain unsigned data.

The adder 114 and the latch circuit 117
It is used to add the outputs of the absolute value circuit 113.

The start of addition of the output of the absolute value circuit 113 and the end of addition are determined by the sequencer 111.
Is controlled by the burst signal processing gate 118 generated in the above.

The register 112 stores the data of the latch circuit 117 after the addition by the adder 114 and the latch circuit 117 is completed. The data stored in the register 112 is processed by the hard disk controller 108 and the microcomputer 115 as servo positioning information.

Next, servo signal processing by the conventional digital servo signal processing device having the above configuration will be described.

The servo signal 100 is processed through a VGA 101, a filter 102, an analog / digital converter 103, and a digital filter 104.

Of these, the servo address mark 152
Are binarized by the maximum likelihood decoder 5 and detected by the servo address mark detection circuit 110. When detecting the servo address mark 152, the servo address mark detection circuit 110 outputs a servo address mark detection signal 116.

The servo decoder 109 receives the servo address mark detection signal 116 and
3 and generates a burst signal processing gate 118 for specifying the timing at which the sequencer 111 performs burst signal processing.

Further, the burst signal 155 is
1. After passing through an analog filter 102, it is sampled by an analog-to-digital converter 103 and converted into a digital signal. After passing through the digital filter 104, this signal is converted into unsigned data by the absolute value circuit 113, and then added by the adder 114 and the latch circuit 117. The timing for starting and ending the addition is determined by the sequencer 11.
1 is controlled by the burst signal processing gate 118 generated.

After the addition is completed, the data of the latch circuit 117 is stored in the register 112 as a servo position error signal.
Is written to. This data is used as servo positioning information by the hard disk controller 108, microcomputer 1
15 is processed.

A method of converting a burst signal into a digital signal through the same analog-to-digital converter as in data processing, digitally performing absolute value processing and addition, and processing servo positioning information is described in Kevin D. Fisher, US Pat. 5,38
4,671 (especially FIG. 6).

[0033]

In the conventional digital servo signal processing device shown in FIG. 22, in order to improve the accuracy of the servo positioning information stored in the register 112, the addition is performed by the adder 114 and the latch circuit 117. It is effective to increase the quantization accuracy (number of bits) of the burst signal.

In the above-described conventional digital servo signal processing apparatus, the burst signal is quantized by the analog-to-digital converter 103, and then the sign bit is deleted by the absolute value circuit 113 to be converted into unsigned data. I have.

For this reason, the number of bits of the burst signal added by the adder 114 and the latch circuit 117 becomes the number of bits obtained by subtracting the sign bit (1 bit) from the resolution of the analog-to-digital converter 103. There is a problem that the resolution of the converter 103 cannot be used efficiently.

In the above-described conventional digital servo signal processing device, the burst signal is output from the analog-to-digital converter 1
The signal is converted into a discrete-time digital signal by an adder 114 and added by an adder 114 and a latch circuit 117. For this reason, there is also a problem that the result of the addition varies depending on the sampling start timing of the burst signal in the analog-to-digital converter 103.

In the conventional analog servo signal processing device, by setting the integration time of the burst signal to be an integral multiple of the cycle of the burst signal, a constant value can be obtained regardless of the timing of starting the addition of the burst signal. it can.

On the other hand, in the above-mentioned conventional digital servo signal processing apparatus, even when the burst signal sample time is set to an integral multiple of the burst signal period, the added value varies due to a shift in the sample timing, and the servo position is changed. The accuracy of the error signal is reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital servo signal capable of improving the accuracy of a servo position error signal without increasing the number of bits of an analog-to-digital converter. An object of the present invention is to provide a processing device, a disk medium reproducing device, and a disk medium.

Specifically, it is an object of the present invention to increase the quantization accuracy of a burst signal for specifying a servo position error signal without increasing the number of bits of an analog-to-digital converter.

It is another object of the present invention to suppress the result of addition of the burst signal due to the fluctuation of the sampling start timing of the burst signal, that is, the variation of the servo position error signal.

[0042]

According to a first aspect of the present invention, there is provided an analog-to-digital converter for sequentially sampling servo signals and data signals read from a disk medium and converting the signals into digital signals. A digital servo signal processing device that determines servo positioning information based on a burst signal included in the servo, which is converted into a digital signal by the analog-to-digital conversion means, wherein the analog-to-digital conversion means includes: When the signal read from the disk medium is the burst signal, the signal is converted to an unsigned digital signal, and when the signal is other than the burst signal, the signal is converted to a signed digital signal. Features.

Here, the sign is a sign indicating positive or negative.

The servo signal is a signal used for determining a relative positional displacement between the disk medium and reading means such as a head or a pickup for reading a signal from the disk medium.

The servo signal includes a timing reproducing section used to synchronize the sample timing of the analog-to-digital converter with the servo signal, a servo address mark for specifying the servo signal processing timing,
It includes a gray code on which a track number of a disk medium is written and a burst signal for obtaining a position error of the reading means.

According to the first aspect of the present invention, since the burst signal is converted into an unsigned digital signal by the above configuration, the quantization accuracy of the burst signal is improved by the number of code bits (1 bit). Can be. Further, a circuit for processing the absolute value of the burst signal quantized by the analog-to-digital conversion means is not required.

In the first aspect of the present invention, further, when the signal read from the disk medium is the burst signal, the signal is further converted to the analog signal via the full-wave rectifier. Path switching means for inputting to the digital conversion means and for inputting the signal to the analog-to-digital conversion means without passing through the full-wave rectification means in the case of a signal other than the burst signal.

In this case, the sign of the burst signal input to the analog-to-digital converter is always the same. Therefore, for example, even when the input range of the burst signal in the analog-to-digital converter is set to 0 to + B,
Not only the information of the positive part but also the information of the negative part of the burst signal can be effectively utilized for generating the servo position error signal.

According to a second aspect of the present invention, there is provided an analog-to-digital converter for sequentially sampling a servo signal or a data signal read from a disk medium and converting the signal into a digital signal. A digital servo signal processing device that determines servo positioning information based on a burst signal included in the servo, wherein the sample period of the burst signal in the analog-to-digital converter is other than the burst signal. It is characterized in that a sampling cycle switching means for switching a sampling cycle of the analog-to-digital conversion means so as to be shorter than a sampling cycle of the servo signal is provided.

According to the second aspect of the present invention, the sample period of the burst signal can be shortened without changing the sample period of the servo signal other than the burst signal. As a result, the number of samples of the burst signal can be increased, and variation in the result of adding the burst signal due to a change in the sample start timing can be suppressed.

In the second aspect of the present invention, the sample period switching means is arranged so that the sample period of the burst signal is asynchronous with the burst signal and the sample periods of the servo signals other than the burst signal are changed. The sample period may be switched so as to synchronize with the servo signal.

In this way, when sampling the burst signal, the distribution of the quantization error of each sample can be made uniform, whereby the variation in the addition result of the burst signal can be further suppressed.

According to a third aspect of the present invention, there is provided an analog-to-digital converter for sequentially sampling a servo signal or a data signal read from a disk medium and converting the signal into a digital signal. A digital servo signal processing device for determining servo positioning information based on a burst signal included in the servo converted into a digital signal, wherein the digital signal converted by the analog-to-digital It is characterized in that it comprises a period conversion unit for converting the signal into a signal longer than the sample period of the conversion unit.

According to the third aspect of the present invention, by providing the period conversion means, the sampling period of the analog-to-digital conversion means can be set without considering the case where a servo signal other than a burst signal is sampled. it can. Therefore, by shortening the sampling period of the analog-to-digital conversion means, the number of samples of the burst signal can be increased, and variation in the result of addition of the burst signal due to variation in the sample start timing can be suppressed.

Further, a fourth aspect of the present invention provides a disk medium on which a burst signal is recorded at a frequency offset from the frequency of a servo signal other than the burst signal, reading means for reading an analog signal from the disk medium, An analog-to-digital conversion unit that converts a servo signal or a data signal read from the disk medium into a digital signal, and a burst signal included in the servo, which is sequentially sampled and converted into a digital signal by the analog-to-digital conversion unit, is added. Calculating means, based on the digital signal converted by the analog-to-digital conversion means,
Decoding means for decoding a gray code included in the servo signal, calculation means for obtaining positioning information of the servo based on the addition result obtained by the arithmetic means, and the gray code obtained by the decoding means; Position control means for controlling the position of the reading means on the disk medium based on the servo positioning information obtained by the calculation means, wherein the analog-to-digital conversion means samples the burst signal. A disc medium reproducing apparatus characterized in that, in the case of performing the operation, the operation is performed in synchronization with a servo signal other than the burst signal.

According to the fourth aspect of the present invention, the analog-to-digital conversion means samples the burst signal recorded at a frequency offset from the frequency of another servo signal at a sample period synchronized with the other servo signal. Therefore, the burst signal can be sampled asynchronously.

For this reason, when the burst signal is sampled, the distribution of the quantization error of each sample can be made uniform, whereby the variation in the result of adding the burst signal can be further suppressed.

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital servo signal processing device for a magnetic disk according to an embodiment of the present invention.

First, before describing the digital servo signal processing device for a magnetic disk according to the present embodiment, the configuration of the servo signal processed by the device and the case where the servo signal is processed by the device will be briefly described. I do.

FIG. 2 is a diagram for explaining servo signals processed by the digital servo signal processing device shown in FIG. 1 and timings of main signals output when processing the servo signals.

As shown in FIG. 2, the servo signal 150
For timing reproduction and AGC (Automatic Gain Control)
l) Timing playback unit (Se
rvoAGC / Timing) 151 and a servo address mark (Servo Marc / Timing) for generating a timing for processing a servo signal.
k) 152, a Gray code 153 in which data such as a track number and a head number are written, a gap (GAP) 154, and a burst signal (A Burst, B Burst) serving as a head position error signal 155a, 15
5b. Since the servo signal shown in FIG. 2 has the same configuration as the servo signal shown in FIG. 23 described in the related art, the description is given using the same reference numerals as the servo signal shown in FIG.

FIG. 16 is a diagram showing a format on a magnetic disk used in the apparatus of this embodiment shown in FIG.

As shown in FIG. 16, the magnetic disk 650
There are servo areas 1102, 1105, 1108,... On which servo information such as track and position information is recorded.
Are formed radially and at regular intervals. A DC erase area is formed before or after, or before or after, the servo areas 1102, 1105, 1108,.... Here, the DC erase area refers to the magnetic disk 6
This is an area on which nothing is recorded.

In the example shown in FIG.
, DC erase regions 1101, 1104, 1107,... Are formed before 2, 1, 105, 1108,. Also, tracks 1109, 1110,... Are formed on the magnetic disk 650 along concentric circles.

Here, for example, when reading or writing data from the track 1110 on the magnetic disk 650, the head 651 must be moved onto the track 1110.

Therefore, when moving the head 651 from an arbitrary position onto the track 1110, first, the hard disk controller (not shown)
, 01, 1104, 1107,... Are detected, and the locations of the servo areas 1102, 1105, 1108,. Then, the timing for reading the servo area is obtained from this, and a servo gate indicating the start of servo processing is output to the digital servo signal processing device shown in FIG.

In response, the digital servo signal processing device shown in FIG. 1 reads out data written in the servo area. Next, the hard disk controller calculates a distance difference between the current position of the head 651 and the target track 1110 based on the read data of the servo area.
Then, using the voice coil motor 653, the head 6
51 is moved by the calculated distance difference.

By repeating this, the head 651 is moved to a desired track, and the data written on the track is read and written.

Next, a digital servo signal processing device for a magnetic disk according to the present embodiment will be described.

As shown in FIG. 1, the digital servo signal processing device for a magnetic disk according to the present embodiment has a VGA (Variabl
e Gain Amp) 1, analog filter 2, analog-to-digital converter (A / D) 3, digital (FIR) filter 4, maximum likelihood decoder 5, data decoder 6, and input / output circuit (I / O) 7.

The VGA 1 is a variable gain amplifier for keeping the signal amplitude level of analog signals (servo signals and data signals) read from a magnetic disk (not shown) constant.

The analog filter 2 removes noise and equalizes the waveform of the output signal of the VGA 1.

The analog-to-digital converter 3 quantizes the output signal of the VGA 1 sent via the analog filter 2 and converts it into a digital signal.

The analog-to-digital converter 3 outputs a burst start signal 2 output from a sequencer 11 described later.
According to No. 8, the conversion of the input signal is switched from a signed digital signal to an unsigned digital signal, and the dynamic range is set to be switched from + A to -A to 0 to + B.

Here, A is the analog-to-digital converter 3
Is a value determined in advance in accordance with the amplitude of the analog signal (excluding the burst signal of the servo signal) input to. B is a value determined in advance according to the amplitude of the burst signal.

The digital filter 4 equalizes the waveform of the output signal (digital signal) of the analog-to-digital converter 3.

The maximum likelihood decoder 5 binarizes the output signal of the analog-to-digital converter 3 sent via the digital filter 4.

When the signal binarized by the maximum likelihood decoder 5 is a data signal, the data decoder 6 decodes the signal.

The input / output circuit 7 sends the data decoded by the data decoder 6 and the gray code decoded by the servo decoder 9 described later to the hard disk controller 8.

As shown in FIG. 1, the digital servo signal processing device for a magnetic disk according to the present embodiment comprises a servo decoder 9, a servo address mark (SAM) detection circuit 10, a sequencer 11
And

When the signal binarized by the maximum likelihood decoder 5 is a servo signal 150, the servo address mark detection circuit 10 detects a servo address mark 152 from the signal. Then, the servo address signal 16 is output at a timing corresponding to the detection of the servo address mark 152.

The servo decoder 9 outputs the servo address signal 1 output from the servo address mark detection circuit 10.
6, the Gray code 153 is decoded.

The sequencer 11 generates a burst signal processing gate 18 and a burst start signal 28 for specifying the timing of processing the burst signal 155 based on the servo address signal 16 output from the servo address mark detection circuit 10.

Further, as shown in FIG. 1, the digital servo signal processing device for a magnetic disk according to the present embodiment includes an adder 14 and a latch circuit 17 for processing a burst signal.
, A resistor 12, a full-wave rectifier 50, and an amplifier 51.
, Analog switch 52, and timing reproduction loop 7
0.

The adder 14 is provided for the analog-to-digital converter 3
And the digital signal of the burst signal 155 output from the latch circuit 17 is added. The latch circuit 17
The addition result of the adder 14 is latched. Therefore, the adder 14 and the latch circuit 17 calculate the sum of the digital data of the burst signal quantized by the analog-to-digital converter 3.

The start of addition and the end of addition in the adder 14 and the latch circuit 17 are controlled by a burst signal processing gate generated by the sequencer 111.

After the addition by adder 14 and latch circuit 17 is completed, register 12 stores the data of latch circuit 17. The data stored in the register 12 is used as servo positioning information by the hard disk controller 8.
And the microcomputer 15.

The full-wave rectifier 50 performs full-wave rectification on the analog signal sent through the filter 2.

The amplifier 51 amplifies the output of the full-wave rectifier 50.

The analog switch 52 is connected to the sequencer 11
According to the burst start signal 28 generated in the above, the input path to the analog-to-digital converter 3 is changed to a filter 2-analog switch 52-analog-digital converter 3, and a filter 2-full-wave rectifier 50-amplifier 51-analog switch. 52-Switch to one of the analog-to-digital converters 3.

Specifically, when the burst start signal 28 is output from the sequencer 11 (in FIG. 2, when the burst start signal 28 is High), the analog switch 52 is connected to the input path to the analog-to-digital converter 3. To the filter 2, the full-wave rectifier 50, the amplifier 51, the analog switch 52, and the analog-to-digital converter 3.

On the other hand, when the burst start signal 28 is not output from the sequencer 11, the analog switch 5
2 switches the input path to the analog-to-digital converter 3 to the filter 2, the analog switch 52, and the analog-to-digital converter 3.

As shown in FIG. 1, the timing recovery loop 70 includes a phase comparator 20, a loop filter 21, a digital / analog converter (DAC) 22, a voltage controlled oscillator (VCO) 23, and a frequency divider ( 1 / k) 53, a switch 54, and a register 24.

The phase comparator 20 generates a phase difference signal (digital signal) based on the output signal of the digital filter 4. This phase difference signal is a signal for synchronizing the sample period of the analog-to-digital converter 3 with the analog signal input to the analog-to-digital converter 3, and is input to the digital-to-analog converter 22 via the loop filter 21. Is done.

The phase comparator 20 includes a sequencer 11
Does not operate in the state where the burst start signal 28 is output from. That is, the timing reproduction loop 70 is opened.

The register 24 stores a table indicating a relationship between the phase difference signal and an analog signal for specifying a clock generation timing in the voltage controlled oscillator 23 described later.

More specifically, a table showing a relationship between a phase difference signal in the data signal processing mode and an analog signal corresponding to a clock for synchronously sampling the data signal input to the analog-to-digital converter 3; An analog signal corresponding to a frequency that is 1 / (frequency division ratio of frequency divider 53) times the clock for synchronously sampling the phase difference signal in the servo signal processing mode and the servo signal input to analog-to-digital converter 3 Is stored.

In addition, when the timing reproduction loop 70 is open, 1/1 of the clock for synchronously sampling the servo signal input to the analog-to-digital converter 3 is used.
An analog signal corresponding to a frequency obtained by giving an offset to a frequency twice (frequency division ratio of the frequency divider 53), that is, a frequency for asynchronously sampling the servo signal input to the analog-to-digital converter 3 is stored. .

The digital-to-analog converter 22 converts the input phase difference signal into a corresponding analog signal according to the table stored in the register 24. Thereby, a control signal for the voltage controlled oscillator 23 is generated.

The voltage-controlled oscillator 23 outputs a clock signal according to the control signal generated by the digital-to-analog converter 22.

The frequency divider 53 divides the frequency of the clock signal output from the voltage controlled oscillator 23. The clock signal output from the frequency divider 53 is used as a timing clock of a digital circuit such as the digital filter 4, the maximum likelihood decoder 5, or the data decoder 6.

Here, when the frequency division ratio of the frequency divider 53 is 1 / k, it is preferable that k = integer.

The switch 54 converts one of the output clock signal of the frequency divider 53 and the output clock signal of the voltage controlled oscillator 23 into an analog-to-digital signal as a clock signal for specifying the sampling period of the analog-to-digital converter 2. Input to the container 3.

Specifically, when the digital servo signal processing apparatus of the present embodiment is in the servo signal processing mode, when the burst start signal 28 is output from the sequencer 11 (in FIG. 2, the burst start signal is high). Case)
Inputs the output clock signal of the voltage controlled oscillator 23 to the analog-to-digital converter 3.

On the other hand, when the burst start signal 28 is not output from the sequencer 11, the output clock signal of the frequency divider 53 is input to the analog-to-digital converter 3.

When the digital servo signal processing device of this embodiment is in the data processing mode, the output clock signal of the voltage controlled oscillator 23 is
To enter.

Incidentally, the servo signal is usually recorded on the magnetic disk at a frequency not more than 1/2 of the highest frequency of the data signal.

Therefore, the maximum oscillation frequency of the voltage controlled oscillator 23 is set so as to be a frequency for sampling the highest frequency of the data signal by the analog-to-digital converter 3, and the frequency division ratio of the frequency divider 53 is set to 1 /. When set to 2, the switch 54 can input a clock signal having a sample period corresponding to the frequency of each of the data signal and the servo signal (excluding the burst signal) to the analog-to-digital converter 3. Further, as the clock signal for specifying the sampling period of the burst signal, a clock signal having a frequency twice as high as that of sampling a servo signal other than the burst signal can be input to the analog-to-digital converter 3.

Next, the operation of the digital servo signal processing device for a magnetic disk of the present embodiment shown in FIG. 1 will be described with reference to FIG.
This will be described with reference to FIG.

First, the operation in the data processing mode will be described.

The digital servo signal processing device according to the present embodiment enters the data processing mode when the hard disk controller 8 does not output the servo gate 29.

In the data processing mode, the sequencer 11 does not output the burst start signal 28. Therefore, the analog switch 52 is connected to the filter 2 -the analog switch 52-as an input path to the analog-to-digital converter 3.
The analog-to-digital converter 3 has been selected. Therefore, a data signal read from a disk medium (not shown) is input to the analog-to-digital converter 3 via the VGA 1, the filter 2, and the analog switch 52.

Next, the analog-to-digital converter 3 quantizes the received data signal into a digital signal.

At this time, since the sequencer 11 has not output the burst start signal 28, the analog-to-digital converter 3 converts the received data signal into a signed digital signal.

Since the hard disk controller 8 does not output the servo gate signal 29, the switch 54 is in a state where the output clock of the voltage controlled oscillator 22 is selected. Therefore, the analog-to-digital converter 3
The data signal is synchronously sampled using the output clock of the voltage controlled oscillator 22 controlled by the timing reproduction loop 70 as a sample clock.

Next, the data signal converted to a signed digital signal by the analog-to-digital converter 3 is subjected to waveform equalization by the digital filter 4 and then converted to binary data by the maximum likelihood decoder 5. Is done.

Then, the data is decoded by the data decoder and then transmitted to the hard disk controller 8 via the input / output circuit 7 for processing.

In the data processing mode, the servo decoder 9 and the servo address mark detection circuit 10 do not operate.

Next, the operation in the servo signal processing mode will be described.

When the hard disk controller 8 shifts from the data processing mode to the servo signal processing mode,
Servo gate 2 which is a control signal in the servo signal processing mode
9 is generated. The digital servo signal processing device for a magnetic disk according to the present embodiment starts the servo signal processing at the timing when the hard disk controller 8 outputs the servo gate 29.

At the start of the servo signal processing, the sequencer 11 does not output the burst start signal 28 as shown in FIG. Therefore, the analog switch 52 is connected to the filter 2 -the analog switch 52 -the analog-to-digital converter 3 as an input path to the analog-to-digital converter 3.
Is selected.

In this state, the timing reproducing section 151, the servo address mark 152, and the gray code 153 of the servo signal 150 are sequentially input to the VGA 1, and are input via the analog filter 2 and the analog switch 52.
It is input to the analog-to-digital converter 3.

Since the sequencer 11 is not outputting the burst start signal 28, the analog-to-digital converter 3 converts the input timing reproduction unit 151, servo address mark 152, and gray code 153 into signed signals, respectively. Convert to digital signal.

The switch 54 is in the servo signal processing mode, and the burst start signal 2
8 is not output, the output clock signal of the frequency divider 53 is input to the analog-to-digital converter 3.

Therefore, the analog-to-digital converter 3
According to a sample clock obtained by dividing the output clock signal of the voltage controlled oscillator 23 controlled by the timing recovery loop 70 by the frequency divider 53, the timing recovery unit 15
1, synchronously sample the servo address mark 152 and the gray code 153.

Next, the timing reproducing unit 15 converted into a digital signal with a sign by the analog / digital converter 3
1, the servo address mark 152, and the gray code 153 are sequentially waveform-equalized by the digital filter 4, and then converted to binary data by the maximum likelihood decoder 5.

Next, the servo address mark detection circuit 1
When the servo address mark 152 is detected from the data binarized by the maximum likelihood decoder 5, 0 outputs a servo address mark detection signal 16 to the hard disk controller 8, the servo decoder 9, and the sequencer 11.

As shown in FIG. 2, the servo decoder 9 starts decoding the data binarized by the maximum likelihood decoder 5 into a gray code 153 at the timing when the servo address mark detection signal 16 is received. . Then, the decoded gray code 153 is sent to the hard disk controller 8 via the input / output circuit 7.

The sequencer 11 operates the built-in counter at the timing when the servo address mark detection signal 16 is received, and generates the burst start signal 28 and the burst signal processing gate 18 at the timing as shown in FIG.

When the burst start signal 28 is generated (in FIG. 2, the burst start signal is high), the analog switch 52 switches the input path to the analog-to-digital converter 3 from the filter 2 to the analog switch 52 From the digital converter 3, a filter 2-a full-wave rectifier 50-
Switching is made to the amplifier 51, the analog switch 52, and the analog / digital converter 3.

Thus, the burst signal 155 is full-wave rectified by the analog full-wave rectifier circuit 50 and
After being amplified by 1, through the analog switch 52,
It is input to the analog-to-digital converter 3.

When the sequencer 11 outputs the burst start signal 28, the analog-to-digital converter 3 switches the dynamic range from 0 to + B.
When converting an input signal to an unsigned digital signal. Therefore, the burst signal 155 is converted into an unsigned digital signal.

Here, it is preferable that the amplifier 51 be set in advance to an amplification factor that can effectively utilize the dynamic range 0 to + B of the analog-to-digital converter 3.

The switch 54 is in the servo signal processing mode, and the sequencer 11
Is output, the output clock signal of the voltage controlled oscillator 23 is input to the analog-to-digital converter 3.

At this time, the phase difference comparator 20 opens the timing reproduction loop 70. In response to this, the digital-to-analog converter 22 controls the oscillation frequency of the voltage-controlled oscillator 23 so as to change the oscillation frequency from 1 / (division ratio) times the frequency of the sample signal lock of the servo signal to an offset frequency. Output a signal.

As a result, the analog-to-digital converter 3
Is 1 / the frequency of the output clock signal of the frequency divider 53.
The burst signal 155 is asynchronously sampled according to a sample clock whose frequency is twice as high and whose frequency is offset from the sample clock of the servo signal.

As shown in FIG. 2, while the sequencer 11 is outputting the burst start signal 28, the burst signal 155 sequentially sampled and quantized by the analog-to-digital converter 3 is added to the adder 14 and the latch circuit. 17 is added. The addition ends when the burst start signal 28 falls.

The result of this addition is written to the register 12 as a servo position error signal. This data is processed by the hard disk controller 8 and the microcomputer 15 as servo positioning information.

In this embodiment, when the analog signal read from the magnetic disk is the servo signal 150, the burst signal 155 is transmitted to the full-wave rectifier 50 and the amplifier 5.
1 to the analog-to-digital converter 3. Therefore, the sign of the burst signal input to the analog-to-digital converter 3 is always the same.

FIG. 2 shows a waveform 150a of the servo signal input to the analog-to-digital converter 3. As described above, the burst signal input to the analog-to-digital converter 3 has full-wave rectified waveforms 156a and 156b.

Therefore, in this embodiment, the burst signal 1
While 55 is input to the analog-to-digital converter 3, the analog-to-digital converter 3 converts the input signal into an unsigned digital signal.

By doing so, the quantization accuracy of the burst signal by the analog-to-digital converter can be improved by the number of code bits as compared with the conventional digital servo signal processing device. Further, a circuit (absolute value processing circuit 113 shown in FIG. 22) for performing absolute value processing on the quantized burst signal becomes unnecessary.

In this embodiment, the burst signal 15
While 5 is input to the analog-to-digital converter 3, the dynamic range of the analog-to-digital converter 3 is set to -A to + A.
From 0 to + B, and the burst signal 15 which has been full-wave rectified by the full-wave rectifier 50 by the amplifier 51.
5 is amplified with an amplification factor such that the dynamic range of the analog-to-digital converter 3 can be effectively used.

By doing so, the resolution of the burst signal can be substantially improved.

For example, as in a conventional digital servo signal processing device, a burst signal is converted to a dynamic range -A
When quantization is performed at + A, the dynamic range used to quantize the amplitude of the burst signal (absolute value of the burst signal) is 0-A, which is half of that. Therefore,
The amplitude of the burst signal is quantized with half the resolution of the analog-to-digital converter.

On the other hand, in the present embodiment, the burst signal 155 that has been full-wave rectified by the full-wave rectifier 50 is amplified with an amplification factor that can effectively use the dynamic range 0 to + B of the analog-to-digital converter 3. Therefore, the amplitude of the burst signal can be quantized using all the resolutions of the analog-to-digital converter.

Further, in the present embodiment, servo signals and data signals other than burst signals are supplied to the full-wave rectifier 5.
0 and the signal is input to the analog-to-digital converter 3 without passing through the amplifier 51. At this time, the dynamic range of the analog-to-digital converter 3 is set to -A to + A,
These analog signals are quantized into signed digital signals.

Therefore, according to the present embodiment, it can be used for both data processing and servo signal processing.

In this embodiment, for the burst signal, the output clock from the voltage controlled oscillator 23 is directly input to the analog-to-digital converter 3, and the timing reproduction loop 70 is opened to open the oscillation of the voltage controlled oscillator 23. The frequency is controlled so as to oscillate at a frequency offset from a frequency of 1 / divide ratio of the sample clock of the servo signal (output clock of the frequency divider 53).

By doing so, the burst signal 15
5 can be sampled asynchronously, and the number of samples of the burst signal can be reduced compared with the case where a clock for sampling a servo signal other than the burst signal (output clock of the frequency divider 53) is used as a sample clock of the burst signal. hand,
It can be increased to the reciprocal times the division ratio.

As a result, the number of samples of the burst signal can be increased without changing the sample period of the servo signals other than the burst signal, and the variation of the result of adding the burst signals due to the fluctuation of the sample start timing can be suppressed. . In addition, when the burst signal is sampled, the distribution of the quantization error of each sample can be made uniform, and variation in the result of adding the burst signal can be suppressed. The detailed reason for this will be described later.

Next, the main components of the present embodiment will be described in detail with reference to the drawings.

First, the full-wave rectifier 50 will be described with reference to FIG.

FIG. 3 is a circuit diagram of the full-wave rectifier 50 shown in FIG.

As shown in FIG. 3, the full-wave rectifier 50 includes a voltage-current conversion block 701 and a current-mode full-wave rectification block 702.

The voltage-current conversion block 701 includes a differential MO
It comprises S transistors 717 and 718, a resistor 720, a current source 719, and MOS transistors 710 to 716 forming a current mirror circuit. As a result, the voltage / current conversion block 701 outputs the differential currents 731 and 732 proportional to the input voltage Vin.

The current mode full-wave rectifier block 702 includes a current source 730, a bias 733, MOS transistors 728 and 729 forming a current mirror circuit, and a MOS transistor 72 forming a current mode full-wave rectifier circuit.
1 to 726. Here, the current value of the current source 730 is designed to be sufficiently smaller than the current value of the current source 719.

In the full-wave rectifier 50 having the above configuration, the differential current 731 flows from the voltage-current conversion block 701 to the current-mode full-wave rectification block 702, and the differential current 732 flows from the current-mode full-wave rectification block 702 to the voltage-current conversion block. When the current flows to 701, the MOS transistor 722 turns off and the differential current 731 stops flowing. On the other hand, the differential current 732 continues to flow through the MOS transistor 723.

On the contrary, the differential current 732 is supplied from the voltage / current conversion block 701 to the current mode full-wave rectification block 70.
2, the differential current 731 flows from the current mode full-wave rectification block 702 to the voltage-current conversion block 701,
The MOS transistor 723 turns off and the differential current 732 stops flowing. On the other hand, the MOS transistor 722 has
A differential current 731 flows.

As a result, a current obtained by full-wave rectification of the differential currents 731 and 732 flows through the MOS transistor 728. MOS transistor 729 outputs a full-wave rectified current iout having a value equal to the current flowing through MOS transistor 728.

Next, the analog switch 52 shown in FIG.
This will be described with reference to FIG.

FIG. 4 is a circuit diagram of the analog switch 52 shown in FIG.

Here, MOS transistors 801 to 80
4 and the current sources 807 to 810 constitute an input buffer. The MOS transistors 813 to 820 constitute an analog switch, and are switch-controlled by a burst start signal 28 from the sequencer 11 input via the inverters 821 and 822. MOS transistors 805 and 806 and current sources 811 and 812 constitute an output buffer.

With the above configuration, one of the two Vins shown in FIG. 4 is selected according to the burst start signal, and output (Vout) from the output buffer.

Note that MOS transistors 813 to 820
A parasitic filter is formed by the on-resistance of the analog switch and the parasitic capacitance. By designing the parasitic filter so that its pole is sufficiently high with respect to the signal band, it is possible to suppress signal degradation. Can be.

Next, the frequency divider 53 will be described with reference to FIG.

FIG. 5 is a diagram for explaining the circuit configuration and operation timing of frequency divider 53 shown in FIG.

The frequency divider 53, as shown in FIG.
T-type flip-flops 951 and 952, a divide-by-2, divide-by-4, and divide-by-4 circuit section 965;
3, a frequency divider circuit section 966 composed of 3, 954 and a NOR gate 955, and a selector 956.

The T-type flip-flop 951 is a clock 9 obtained by dividing the clock Vin from the voltage controlled oscillator 23 by two.
60 is output. In addition, a T-type flip-flop 952
Is the output clock 960 of the T-type flip-flop 951
Is further divided by 2 and the 4 divided clock 962 is output Vout
(See FIG. 5B).

The divide-by-3 circuit section 966 includes the voltage controlled oscillator 2
The clock 961 obtained by dividing the clock Vin from 3 by 3 is output (see FIG. 5B).

The selector 956 has a frequency-divided clock 960,
One of 961 and 962 is selected, and the selected divided clock is output as a sample clock of the analog-to-digital converter 3.

Next, the digital-to-analog converter 22 will be described.

FIG. 6 is a circuit diagram of the digital-to-analog converter 22 shown in FIG.

The digital-to-analog converter 22 shown in FIG.
Uses the output voltage of the loop filter 21 as an input Vin and outputs a current 380 for controlling the voltage controlled oscillator 22. The output current 380 controls the oscillation frequency of the voltage controlled oscillator 22 so that the sample clock frequency in the burst signal processing of the analog-to-digital converter 3 has an offset. Sample the burst signal.

The digital-to-analog converter 22 outputs the output voltage (Vin) of the loop filter 21 as shown in FIG.
The current is converted into a current by the OP amplifier 351, the MOS transistor 352, and the resistor 353.

MOS transistors 354 to 359 form a current mirror circuit and have a gate size ratio of 1
It is designed to be 00: 100: 1: 2: 1: 2. Assuming that the current flowing through the MOS transistor 354 is i, the MOS transistors 355, 356, 357, 35
8, 359 are i, i / 10, respectively.
0, i / 50, i / 100 and i / 500.

The switch 368 is connected to the MOS transistor 3
The differential switches 60 to 367 are controlled. Thus, the output current 380 of the digital-to-analog converter 22 is controlled.

Next, the analog-to-digital converter 3 will be described with reference to FIG.

FIG. 7 is a circuit diagram of the analog-to-digital converter 3 shown in FIG.

As shown in FIG. 7, the analog-to-digital converter 3 includes switches 904 and 905 and voltage dividing resistors 906 to 905.
913, comparators 914 to 921, and the decoder 9
22. In FIG. 5, the voltage (VrefH1)
A reference voltage 900 and a voltage V (refH2) 901 are reference voltages used other than during the servo burst signal processing. Further, a voltage (VrefL1) 902 and a voltage V (re
fL2) 903 is a reference voltage for burst signal processing.

The analog-to-digital converter 3 having the above configuration is
Switches 904 and 90 according to the burst start signal 28
5 to switch the input of the reference voltage.

When the sequencer 11 is not outputting the burst start signal 28, the switches 904 and 905 select the reference voltages 900 and 902, respectively. When the sequencer 11 is outputting the burst start signal 28, the switches 904, 905
Are reference voltage 901 and reference voltage 90, respectively.
Select 3.

For example, reference voltages 900, 90
1, 902, 903 are respectively + 0.5V, +1.0
When set to V, -0.5 V, and 0.0 V, the dynamic range of the analog-to-digital converter 3 is -0.5 V to +0.5 V except for burst signal processing, and 0 V to +1 for burst signal processing. 0.0V. In this case, by setting the amplification factor of the amplifier 51 to twice, the dynamic range in the burst signal processing of the analog-to-digital converter 3 can be effectively used.

Also, for example, the reference voltage 90
0, 901, 902, and 903 are respectively +0.5 V, +
When the voltage is set to 0.5 V, -0.5 V, and 0.0 V, the dynamic range of the analog-to-digital converter 3 is -0.5 V to +0.5 V except for burst signal processing.
In the case of the burst signal processing, it becomes 0V to + 0.5V. In this case, by setting the amplification factor of the amplifier 51 to 1 time,
The dynamic range in the burst signal processing of the analog-to-digital converter 3 can be effectively used.

The analog-to-digital converter 3
In the following, a description will be given of a quantization error when quantizing a burst signal and an improvement in quantization accuracy by switching a dynamic range.

First, the quantization error of the burst signal will be described.

FIG. 8 is a diagram for explaining sampling timing when the burst signal is quantized by the analog-to-digital converter 3. Here, in order to simplify the description, a case where the burst signal is directly input from the analog filter 2 to the analog-to-digital converter 3 will be described.

The burst signal 155 is output from the voltage controlled oscillator 2
3 is sampled and quantized according to the output clock. Here, the number of samples of the burst signal 155 is k, and the quantization error at each sample point is e1, e2, e3,
e4, e5, e6,... ek. The average quantization error Eave at this time can be expressed by Eave = (e1 + e2 + e3 +... + Ek) / k (Equation 1).

Here, when the burst signal 155 is asynchronously sampled by the output clock of the voltage controlled oscillator 23, the value of each of the quantization errors e1 to ek is usually -0.5 [L].
SB (least significant bit)] to +0.5 [LSB]
Are distributed to some extent uniformly.

Therefore, by increasing the number k of samples of the burst signal 155 and sampling the burst signal 155 with a sample clock asynchronous with the burst signal 155, the distribution of the quantization error at each sample point is made uniform. As a result, the value of the average quantization error Eave can be made closer to 0 [LSB].

Here, if the resolution of the analog-to-digital converter 3 is x bits, the effective resolution of the analog-to-digital converter 3 by asynchronous sampling is y bits, and the dynamic range of the analog-to-digital converter 3 is V1, V1 / (2 ^y) = a (V1 * Eave) / (2 x) ( equation 2). Therefore, the effective resolution y of the analog-to-digital converter 3 using asynchronous samples can be represented by y = x-log2 (Eave) (Equation 3).

As can be seen from (Equation 4), the effective resolution y of the analog-to-digital converter 3 using asynchronous samples is
The value increases as the value of the average quantization error Eave approaches 0 [LSB], that is, as the number of samples increases.

Therefore, in the present embodiment, as described above, for the burst signal, the output clock from the voltage controlled oscillator 23 is directly input to the analog-to-digital converter 3 and the timing reproduction loop 70 is opened, The oscillation frequency of the voltage controlled oscillator 23 is equal to the sampling clock of the servo signal (the output clock of the frequency divider 53).
The frequency is controlled so as to be offset from the frequency of 1 / divide ratio.

By doing so, the burst signal 15
5 and the burst signal 15
The number of samples of 5 is increased to 1 / divide ratio of the sampling clock of the servo signal (the output clock of the frequency divider 53).

For example, the frequency of the output clock of the frequency divider 53 is fs1 [Hz], the frequency offset by the digital-to-analog converter 22 is d [%],
Is 1 / k, the frequency fs2 [Hz] of the output clock of the voltage controlled oscillator 23 is fs2 = fs1 * k * (1 + d / 100) (Equation 5). As is apparent from (Equation 5), the burst signal 1
The number of samples in one cycle of 55 is about k times the number of samples in one cycle of a servo signal (gray code or servo mark address) other than the burst signal.

According to the simulations of the present inventors,
When the burst signal was asynchronously sampled using a 6-bit analog-to-digital converter at a frequency approximately k times the frequency of the servo signal sampling clock, the effective resolution of the analog-to-digital converter could be set to 8 bits. As a result, it was confirmed that the effective resolution can be improved by two bits over the resolution of the analog-to-digital converter.

Next, the improvement of the quantization accuracy by switching the dynamic range will be described.

FIG. 9 is a diagram for explaining the sample points of the gray code 153 and the burst signal 155 and the manner of quantization.

As described above, in the present embodiment, the dynamic range of the analog-to-digital converter 3 is switched between the burst signal and other analog signals. Here, as shown in FIG. 9, the dynamic range of the analog-to-digital converter 3 when processing servo signals other than the burst signal is V1 [V], and the dynamic range of the analog-to-digital converter 3 when processing the burst signal 155. When the range V2 = V1 / 2 and [V], equation ^{2, V1 / (2 y) =} (V2 * Eave) / (2 x) = (V1 * Eave) / (2 (x + 1)) ( Expression 6), and Expression 3 becomes y = x + 1−log2 (Eave) (Expression 7).

As can be seen from (Equation 7), by changing the dynamic range of the analog-to-digital converter 3, the effective resolution of the analog-to-digital converter 3 can be increased by one bit.

Next, the servo address mark detector 10 will be described.

Before describing the circuit configuration of the servo address mark detector 10, the servo address marks detected by the servo address mark detector 10 will be described with reference to FIG.
0 will be described.

FIG. 10 is a diagram for explaining the pattern of the servo address mark of the servo signal stored in the servo sector of the magnetic disk.

As described above, the servo address mark 1
52 is used to generate the processing timing of the gray code 153. Hard disk controller 8
Specifies the timing of outputting the servo gate 29 by obtaining the position information of the servo sector from the servo address mark detection signal 16. The sequencer 11
Generates the burst start signal 28 and the burst signal processing gate 18 for specifying the processing timing of the burst signal by receiving the servo address mark detection signal 16.

For this reason, high reliability is required for the detection of the servo address mark 152, and the pattern of the servo address mark 152 needs to be a pattern with few detection errors even for bit errors.

Thus, in the present embodiment, the pattern 611 of the servo address mark 152 and the pattern 611
Is designed so that the minimum value dmin of the hamming distance between the pattern 602 shifted to the pattern 610 side of the timing reproduction unit 151 and the pattern 603 shifted to the pattern 612 side of the gray code 153 is increased.

By doing so, the bit error of dmin / 2 or less at which the servo address mark detector 10 can correctly detect the servo address mark 152 is increased.

Next, the circuit configuration of the servo address mark detector 10 will be described with reference to FIG.

FIG. 11 is a circuit diagram of the servo address mark detector 10 shown in FIG.

FIG. 11 shows a configuration example of the servo address mark detection circuit 10 which can detect a servo address mark for an error of up to one bit in an 8-bit servo address mark.

The servo address mark detector 10 is the same as that shown in FIG.
As shown in FIG. 1, the shift register 501 and the register 5
02, an adder 503, and EOR gates 504 to 511.
And a logic circuit 516.

The shift register 501 has a maximum likelihood decoder 5
Is stored.

The register 502 stores the pattern 611 of the servo address mark 152. Note that a memory such as a ROM may be used instead of the register 502.

Bits corresponding to each other in shift register 501 and register 502 are input to EOR gates 504 to 511, respectively.

The adder 503 includes EOR gates 504 to 5
11 outputs are added.

The logic circuit 516 includes an inverter 512
To 514 and an AND gate 515.

Servo address mark detector 1 having the above configuration
0 compares the pattern of the signal stored in the shift register 501 with the pattern 611 of the servo address mark 152 stored in the register 502 using the EOR gates 504 to 511, and compares the comparison result with the adder 503. By adding, the hamming distance between the pattern 611 of the servo address mark 152 and the pattern of the shift register 502 is calculated.

Then, based on the calculated Hamming distance, the logic circuit 516 determines the detection of a servo address mark, and if detected, generates a servo address mark detection signal 16.

In the above-described embodiment, as shown in FIG.
A description has been given of a case where the burst signal output from is input to the analog-to-digital converter 3 via the full-wave rectifier 50 and the amplifier 51.

However, the present invention is not limited to this. The present invention may be any analog-to-digital converter that can convert a burst signal into unsigned digital data.

FIG. 12 is a diagram for explaining a modification of the digital servo signal processing device shown in FIG. Here, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals.

The digital servo signal processor shown in FIG. 12 differs from that shown in FIG. 1 in that the full-wave rectifier 50, the amplifier 51 and the analog switch 52 are removed, and the output of the analog filter 2 is directly sent to the analog-to-digital converter 3. It is connected.

In the digital servo signal processing device shown in FIG. 12, the servo signal that has passed through the analog filter 2 is
The signal is converted into a digital signal by the analog-to-digital converter 3. At the time of burst signal processing, the dynamic range of the analog-to-digital converter 3 is switched from -A to + A to 0 to + B by the burst start signal 28.

FIG. 13 is a diagram for explaining the state of burst signal processing in analog-to-digital converter 3 shown in FIG.

As shown in FIG. 13, at the time of burst signal processing, the dynamic range of the analog-to-digital converter 3 is switched from V1 (-A to + A) to V2 (0 to + B). This eliminates the need to assign a code bit when quantizing the burst signal, thereby increasing the effective quantization accuracy of the burst signal 155 by one bit.

Note that the negative part of the burst signal becomes a digital signal of 0. Therefore, the negative part of the burst signal is equivalent to not being processed. Thick line 6 shown in FIG.
0 indicates a signal obtained by converting a burst signal into a digital signal.

In this embodiment, as shown in FIG. 1, the output clock of the voltage controlled oscillator 23 and the frequency divider 53
The switching of the sample clock input to the analog-to-digital converter 3 by switching the output clock with the switch 54 has been described.

However, the present invention is not limited to this embodiment. The burst signal is obtained by sampling with a clock higher than the frequency of a clock (servo clock) required to sample the frequency of the servo signal, and the servo signals other than the burst signal are obtained by sampling with the servo clock. Any signal that can be input to the maximum likelihood decoder 5 or the servo decoder 9 at the sample interval may be used.

FIG. 14 is a diagram for explaining a modification of the digital servo signal processing device shown in FIG. 1, and is a diagram of a portion corresponding to the timing reproduction loop 70 of FIG.

Here, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals. In this modification, the configuration other than the portion shown in FIG. 14 is the same as that shown in FIG.

The timing reproduction loop 70a shown in FIG.
Is an analog-to-digital converter 3-a digital filter 4 a
-A phase comparator 20-a loop filter 21-a digital-to-analog converter 22-a voltage-controlled oscillator 23-an analog-to-digital converter 3 in this order.

Accordingly, the analog-to-digital converter 3 samples an analog signal according to the output clock of the voltage controlled oscillator 23. In FIG. 14, reference numeral 212 denotes an output clock of the voltage controlled oscillator
This is a divide-by-2 frequency divider.

The digital filter 4a includes a delay circuit 201
To 204, multipliers 205 to 207, and adder 208
And tap coefficients 209 to 211.

Each of delay circuits 201 to 204 delays the digital signal by one clock of the output clock of voltage controlled oscillator 23.

The multipliers 205 to 207 are connected to the outputs of the analog-to-digital converter 3, the delay circuit 202 and the delay circuit 204, respectively. Therefore, the multiplier 206 receives as input a signal delayed by two clocks with respect to the input of the multiplier 205. The multiplier 507 receives as input a signal delayed by two clocks with respect to the input of the multiplier 206. Multiplier 2
05 to 207 represent tap coefficients 209,
The output is multiplied by 210 and 211.

The adder 208 adds the outputs of the multipliers 205 to 207.

The digital circuits (multipliers 205 to 207 and adder 208) other than the delay circuits 201 to 204
The operation is performed using the output clock of the ２ frequency divider 212. Therefore, multipliers 205 to 207 and adder 208
Is calculated every two clock intervals of the output clock of the voltage controlled oscillator 23.

Thus, the analog-to-digital converter 3 is sampled by the output clock of the voltage controlled oscillator 23. The signal sampled and quantized by the analog-to-digital converter 3 is processed by the digital filter 4a having the above-described configuration into a signal at two clock intervals of the output clock of the voltage controlled oscillator 23, and is output. On the other hand, adder 1
The signal input to 4 is a signal sampled by the output clock of the digital servo voltage controlled oscillator 23.

That is, according to the modification shown in FIG.
In the analog-to-digital converter 3, the servo signal is sampled at twice the clock of the servo clock, but is output by the digital filter 4 at the same sample interval as that processed by the normal servo clock.

Since the output of the analog-to-digital converter 3 is directly input to the adder 14, the adder 14 adds burst signals sampled with a clock twice the servo clock. .

Further, in the present embodiment, an example is described in which the burst signal is sampled with a clock that is asynchronous with respect to the burst signal by giving an offset to the sample clock frequency in the burst signal processing of the analog-to-digital converter 3.

However, the present invention is not limited to this. What is necessary is that the analog-to-digital converter samples the burst signal with a clock that is asynchronous with respect to the burst signal.

For example, even when the sample clock of the analog-to-digital converter is fixed (ie, in FIG. 1, the timing reproduction loop 70 is not opened when the analog-to-digital converter 3 samples the burst signal), When writing a format with a servo writer, by writing the burst signal with an offset in frequency, the burst signal can be sampled with a clock that is asynchronous to the burst signal.

FIG. 15 is a diagram showing a servo pattern of a servo sector of a magnetic disk.

[0246] The servo pattern 400 shown in FIG.
1, a gray code 412, and burst signals 413 to 4
16 is obtained.

The write frequency of the timing reproduction area 410, the servo address mark 411, and the gray code 412 is fs1, and the write frequency of the burst signals 413 to 416 is fs2. Usually, the same frequency is used for the writing frequencies fs1 and fs2.

Further, the timing reproduction loop 7 shown in FIG.
0 reproduces a clock synchronized with the frequency fs1, and uses this as a sample clock of the analog-to-digital converter 3.

Here, by setting fs2 to be a frequency having an offset with respect to fs1, the burst signal is sampled with a sample clock synchronized with the frequency fs1, thereby making the burst signal asynchronous with the burst signal. Can be sampled with a clock.

Next, a magnetic disk drive using the digital servo signal processing device of the present embodiment described above will be described.

FIG. 17 is a configuration diagram of a magnetic disk device using the digital servo signal processing device shown in FIG. Here, reference numeral 67 denotes a DC erase detection circuit, reference numeral 650 denotes a magnetic disk, reference numeral 651 denotes a head, reference numeral 652 denotes a read / write amplifier, reference numeral 653 denotes a voice coil motor, reference numeral 654 denotes a voice coil motor control circuit, and reference numeral 655 denotes a magnetic disk. A host computer connected to the device, and reference numeral 656 denotes a magnetic disk device and the host computer 6.
55.

Reference numeral 71 denotes an analog signal processing block, which corresponds to a configuration including the VGA 1, the analog filter 2, the full-wave rectifier 50, the amplifier 51, and the analog switch 52 in FIG. Reference numeral 72
Is a burst signal processing block. In FIG.
This corresponds to a configuration including the sequencer 11, the adder 14, the latch circuit 17, and the register 12.

Reference numeral 71 denotes a digital servo signal processing device, which corresponds to a configuration excluding the hard disk controller 8 and the microcomputer 15 in FIG.

The DC erase circuit 657 detects a DC erase (an area where nothing is recorded on the magnetic disk 650) based on the analog signal quantized by the analog-to-digital converter 3. As described above, in the DC erase detection, the analog-to-digital converter 3 asynchronously samples an analog signal in order to detect an area on the magnetic disk 650 where nothing is recorded. Also, the clock of the DC erase detection circuit 657 is processed by a clock that is asynchronous with the analog signal.

FIG. 18 is a circuit diagram of the DC erase detection circuit 657.

As shown in FIG. 18, the DC erase detection circuit 657 includes a threshold setting register 251, a shift register 252, comparators 254 to 257, and a logic circuit 253.

The register 251 stores a threshold value for detecting DC erase. Register 251
By changing the setting, DC erase of an arbitrary pattern can be detected.

The shift register 252 has the same bit width as the number of bits of the analog-to-digital converter 3 and stores the output of the analog-to-digital converter 3.

The comparators 254 to 257 determine whether the value stored in the shift register 252 is larger than the threshold value.
It is compared for each bit whether it is smaller.

The logic circuit 253 includes the comparator 25
DC erase is determined from the outputs of 4-257. Then, a DC erase detection signal 658 is output.

Next, the servo control processing of the magnetic disk device shown in FIG. 17 will be described.

FIG. 19 is a flow chart for explaining the servo control processing of the magnetic disk device shown in FIG.

In the servo control processing shown in FIG. 17, the host computer 655 executes a read command of the magnetic desk 650,
Alternatively, it is started by outputting a write command. Here, a case where there is a read command will be described.

First, when the read command output from the host computer 655 at step 2001 reaches the hard disk controller 8 via the interface 656, the hard disk controller 8 determines whether or not it is in the initial state (startup) (step S2001). 200
2).

Here, the initial state is the state of the hard disk 8
Indicates that the power is turned on, or that the hard disk controller 8 does not recognize the position of the servo sector when returning from the power save mode.

If it is determined that it is in the initial state (startup), the process proceeds to step 2003, and if it is determined that it is not in the initial state, the process proceeds to step 2005.

In step 2003, the hard disk controller 8 generates the servo gate 29. In response, the DC erase detection circuit 657 starts searching for DC erase. Upon receiving the servo gate 29, the digital servo signal processing device 73 reads an analog signal from the head 651 through the read / write amplifier 652. The read analog signal is supplied to the analog signal processing block 7
After being processed in step 1, the sample is asynchronously sampled by the analog-to-digital converter 3 and converted into a digital signal. The DC erase detection circuit 657 searches for the DC erase from the output of the analog-to-digital converter 3.

When DC erase detection circuit 657 detects DC erase, it outputs a DC erase detection signal 658 to hard disk controller 8 (step 200).
4).

The hard disk controller 8 receives the DC erase detection signal 658 from the DC erase detection circuit 657.
Is received, the position of the servo sector is calculated based on the signal, the generation timing of the servo gate 29 which is a signal for reading the servo signal written in the servo sector is obtained, and the servo gate 29 is generated (step 200).
5).

Upon receiving the servo gate 29 from the hard disk controller 8, the digital servo signal processing device 73 converts the servo signal 150 on the magnetic disk 650 to
The data is read via the head 651 and the read / write amplifier 652. Then, the servo address mark detection circuit 10
, The servo address mark 152 is detected (step 2006).

When the servo address mark detection circuit 10 detects the servo address mark 152 (step 200)
7), the digital servo signal processing device 73 outputs the gray code 15 which is data subsequent to the servo address mark 152.
Read 3 The binarized Gray code 152 is decoded by the servo decoder 9 via the analog-to-digital converter 3, the digital filter 4 and the maximum likelihood decoder 5, and the result is sent to the hard disk controller 8 via the input / output circuit 7. Send.

Next, the digital servo signal processing device 73
Reads a burst signal 155, which is data following the gray code 152. Then, the read burst signal 155 is transferred to the analog signal processing block 71, the analog-to-digital converter 3, and the timing reproduction loop 70.
Is sampled asynchronously and with a sample clock having a period shorter than the normal sample clock, and is converted into an unsigned digital signal. Then, an unsigned digital signal is added in the burst signal processing block 72 (step 2008).

Next, the hard disk controller 8 and the microcomputer 15 calculate a track position based on the gray code 153 and the burst signal 155 to generate a position error signal (step 2009). And
From the generated position error signal, it is determined whether or not the head 651 is on a track (step 2010).
If it is on-track, the process proceeds to step 2012 to perform a data reading process.

If the head 651 is not on-track, the voice coil motor control circuit 654 controls the voice coil motor 653 to move the head 651 (step 2011).

Then, the processing of steps 2005 to 2011 is repeated until the head 651 goes on-track.

Next, the hardware configuration of the magnetic disk drive shown in FIG. 17 will be described.

FIG. 20 is a hardware configuration diagram of the magnetic disk device shown in FIG. 17. FIG. 20 (a) is a front view of the magnetic disk device, and FIG. 20 (b) is a diagram of an electronic circuit portion inside the magnetic disk device. It is.

As shown in FIG. 20 (a), the magnetic disk drive uses a magnetic disk 650 on which data is written.
A spindle motor 682 for rotating the magnetic disk 650, a head 651 for reading data from the magnetic disk 650, and an arm 68 for supporting the head 651.
3, a voice coil motor 653 for moving the head 651, and a read / write amplifier 652 for amplifying a signal from the head 651.

The electronic circuit of the magnetic disk drive is
As shown in FIG. 20B, the host computer 655
684 for controlling the input / output of the connector 684, the hard disk controller 8 for controlling data transfer and format, the microcomputer 15, the digital servo signal processing device 73, and the spindle motor 682. Spindle control circuit 685 and voice coil motor 6
The voice coil motor control circuit 654 that controls the
Each has a configuration formed by an IC chip.

In FIG. 20B, an IC chip is assigned to each component, but all components may be included in one chip, or may be included in two or more chips.

Finally, an example of the configuration of the information processing device (host computer) 655 connected to the magnetic disk device shown in FIGS. 17 and 20 will be described.

FIG. 21 shows an information processing apparatus and FIG. 17 and FIG.
FIG. 3 is a diagram showing a state where the magnetic disk device shown in FIG.

The information processing device 655 includes a central processing unit 67
0, memory 671, and peripheral interface 67
2 and 673, and each component is connected by a bus 674. The information processing device 655 can be connected to external peripheral devices via the peripheral interfaces 672 and 673.

In the example shown in FIG. 21, a magnetic disk device using the digital servo signal processing device of this embodiment is connected to an information processing device 655 via a peripheral interface 672. In this case, the information processing device 655 reads and writes data on the magnetic disk via the peripheral interface 672.

Although the above embodiment has been described using a magnetic disk medium, the present invention can be widely applied to disks on which servo signals are written, such as magneto-optical disks.

[0286]

As described above, according to the present invention,
Without increasing the number of bits of the analog-to-digital converter,
The quantization accuracy of the burst signal for specifying the servo positioning information can be improved. Also, the result of adding the burst signal due to the fluctuation of the burst signal sample start timing,
That is, variation in the servo position error signal can be suppressed.

Therefore, the accuracy of the servo position error signal can be improved without increasing the number of bits of the analog-to-digital converter.

[0288] Further, from the above effects, the area of the burst signal in the servo format can be reduced, and the format efficiency of the disk medium can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a digital servo signal processing device for a magnetic disk according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining servo signals processed by the digital servo signal processing device shown in FIG. 1 and timings of signals output when processing the servo signals.

FIG. 3 is a circuit configuration diagram of the full-wave rectifier 50 shown in FIG.

FIG. 4 is a circuit configuration diagram of the analog switch 52 shown in FIG. 1;

FIG. 5 is a diagram for explaining a circuit configuration and an operation timing of the frequency divider 53 shown in FIG. 1;

6 is a circuit configuration diagram of the digital-to-analog converter 22 shown in FIG.

7 is a circuit configuration diagram of the analog-to-digital converter 3 shown in FIG.

FIG. 8 is a diagram for explaining sample timing when a burst signal is quantized by the analog-to-digital converter 3 shown in FIG. 7;

FIG. 9 is a diagram for describing sample points of a gray code and a burst signal and a state of quantization.

FIG. 10 is a diagram for explaining a servo address mark pattern of a servo signal stored in a servo sector of a magnetic disk.

11 is a servo address mark detector 10 shown in FIG.
FIG. 3 is a circuit configuration diagram of FIG.

FIG. 12 is a diagram for explaining a modification of the digital servo signal processing device shown in FIG. 1;

13 is a diagram for explaining a state of burst signal processing in the analog-to-digital converter 3 shown in FIG.

14 is a diagram for explaining a modification of the digital servo signal processing device shown in FIG. 1, and is a diagram of a portion corresponding to the timing reproduction loop 70 of FIG.

FIG. 15 is a diagram showing a servo pattern of a servo sector of a magnetic disk.

FIG. 16 is a diagram showing a format on a magnetic disk used in the apparatus of the embodiment shown in FIG. 1;

17 is a configuration diagram of a magnetic disk device using the digital servo signal processing device shown in FIG.

18 is a circuit configuration diagram of a DC erase detection circuit 657 shown in FIG.

19 is a flowchart for explaining a servo control process of the magnetic disk device shown in FIG.

20 is a hardware configuration diagram of the magnetic disk device shown in FIG. 17, and a signal processing block configuration diagram incorporating the digital servo signal processing system of the present invention.

FIG. 21 is a diagram showing a state in which the information processing device is connected to the magnetic disk device shown in FIGS. 17 and 20;

FIG. 22 is a schematic configuration diagram of a conventional digital servo signal processing device.

FIG. 23 is a diagram for explaining a servo signal processed by the conventional digital servo signal processing device shown in FIG. 22 and a timing of a signal output when processing the servo signal.

[Explanation of symbols]

Reference Signs List 1 VGA (Variable Gain Amp) 2 Analog filter 3 Analog-to-digital converter 4, 4a Digital filter 5 Maximum likelihood decoder 6 Data decoder 7 I / O circuit 8 Hard disk controller 9 Servo decoder 10 Servo address mark detection circuit 11 Sequencer 12, 24, 251, 502 Registers 14, 208, 503 Adder 15 Microcomputer 16 Servo address mark detection signal 17 Latch circuit 18 Burst signal processing gate 20 Phase comparator 21 Loop filter 22 Digital-to-analog converter 23 Voltage controlled oscillator 28 Burst start signal 29 Servo gate 50 Analog full-wave rectifier circuit 51 Amplifier 52 Analog switch 53, 212 Divider 54 Switch 70, 70a Timing recovery loop 71 Analog signal processing block 72 Gust signal processing block 73 Digital servo signal processing device 201-204 Delay circuit 205-207 Multiplier 252, 501 Shift register 254-257, 914-321 Comparator 253, 516 Logic circuit 351 OP amplifier 352, 354-367, 710-716 , 721-7
26,728,729,801-806,813-82
0 MOS transistor 353, 720 Resistance 368, 904, 905 Switch 504 to 511 EOR gate 650 Magnetic disk 651 Head 652 Read / write amplifier 653 Voice coil motor 654 Voice coil motor control circuit 655 Host computer 656 Interface 657 DC erase circuit 658 DC erase detection Signal 682 Spindle motor 683 Arm 685 Spindle control circuit 701 Voltage / current conversion block 702 Current mode full-wave rectification block 717, 718 Differential MOS transistor 719, 730, 807-812 Current source 733 Bias 821, 822 Inverter 906-913 Voltage dividing resistor 922 Decoder 922 951, 952 T-type flip-flop 953 Divide-by-2 and Divide-by-4 circuit section 95 3,954 D-type flip-flop 955 NOR gate 966 3 frequency dividing circuit section 956 selector

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tatsuya Komatsu 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. (72) Inventor Seiichi Mita 2880 Kozu, Kozu, Odawara-shi, Kanagawa Within Hitachi Storage Systems Division

Claims (17)

[Claims] 1. An analog-to-digital converter for sequentially sampling a servo signal or a data signal read from a disk medium and converting the signal into a digital signal, wherein the analog signal is included in the servo converted into a digital signal by the analog-to-digital converter. A digital servo signal processing device that determines servo positioning information based on a burst signal to be read, wherein the analog-to-digital conversion means converts the signal to an unsigned signal when the signal read from the disk medium is the burst signal. A digital servo signal processing device which converts a signal other than the burst signal into a digital signal and converts the signal into a signed digital signal. 2. The digital servo signal processing device according to claim 1, wherein: when the signal read from the disk medium is the burst signal, the signal is passed through the full-wave rectifier. Path switching means for inputting to the analog-to-digital conversion means and inputting the signal to the analog-to-digital conversion means without passing through the full-wave rectification means in the case of a signal other than the burst signal. A digital servo signal processing device characterized by the above-mentioned. 3. The digital servo signal processing device according to claim 2, wherein a servo address mark included in the servo signal is detected from the digital signal converted by the analog-to-digital conversion means, and a servo address mark detection signal is generated. It has a servo address mark detection means for outputting, the input path switching means, according to the servo address mark detection signal, to input the burst signal to the analog-digital conversion means via the full-wave rectifier, A digital servo signal processing device, wherein an input path to the analog-to-digital conversion means is switched. 4. The digital servo signal processing device according to claim 1, wherein said analog-to-digital conversion means comprises:
A first range having a negative value to a positive value, and a second range having one of the positive and negative values, using the second range for the burst signal, other than the burst signal A digital servo signal processing device using the first range as a signal. 5. The digital servo signal processing device according to claim 4, wherein a servo address mark included in the servo signal is detected from the digital signal converted by the analog-to-digital conversion means, and a servo address mark detection signal is generated. It has a servo address mark detecting means for outputting, wherein the analog-to-digital conversion means switches the input range so as to input the burst signal in the second range according to the servo address mark detecting signal. Digital servo signal processing device. 6. An analog-to-digital converter for sequentially sampling a servo signal or a data signal read from a disk medium and converting the signal into a digital signal, wherein the analog signal is included in the servo converted into a digital signal by the analog-to-digital converter. A digital servo signal processing device that determines servo positioning information based on a burst signal to be generated, wherein a sample period of the burst signal in the analog-to-digital converter is shorter than a sample period of a servo signal other than the burst signal. A digital servo signal processing device comprising a sample cycle switching means for switching a sample cycle of the analog-to-digital conversion means. 7. The digital servo signal processing device according to claim 6, wherein said sampling period switching means oscillates to output a clock signal, and divides a frequency of the clock signal output from said oscillating means. Means, a clock signal output from the oscillator is input to the analog-to-digital conversion means as a clock signal specifying the sample period of the burst signal, and the clock signal output from the frequency divider is other than the burst signal. A digital servo signal processing device, comprising: clock signal switching means for inputting the analog-to-digital conversion means as a clock signal for specifying the sample period of the servo signal. 8. The digital servo signal processing device according to claim 6, wherein said sample period switching means controls a servo period of said burst signal so that a sample period of said burst signal is asynchronous with said burst signal. A digital servo signal processing device, wherein the sample period is switched so that the sample period of the signal is synchronized with the servo signal. 9. The digital servo signal processing device according to claim 8, wherein said sampling period switching means oscillates to output a clock signal, and divides the frequency of the clock signal output from said oscillating means. Means, a clock signal output from the oscillator is input to the analog-to-digital conversion means as a clock signal specifying the sample period of the burst signal, and the clock signal output from the frequency divider is other than the burst signal. Clock signal switching means for inputting the analog-to-digital conversion means as a clock signal for specifying the sampling period of the servo signal; and offsetting the oscillation frequency of the oscillation means when the analog-to-digital converter samples the burst signal. A digital control device comprising: frequency control means; Bo signal processor. 10. The digital servo signal processing device according to claim 7, wherein a servo address mark included in the servo signal is detected from the digital signal converted by the analog-to-digital conversion means, and the servo address mark detection is performed. A servo address mark detection unit that outputs a signal; the clock signal switching unit outputs a clock signal to be input to the analog-to-digital conversion unit according to the servo address mark detection signal from the clock signal of the frequency divider. A digital servo signal processing device for switching to a clock signal of an oscillator. 11. An analog-to-digital converter for sequentially sampling a servo signal or a data signal read from a disk medium and converting the signal into a digital signal, wherein the analog-to-digital converter converts the digital signal into a digital signal. A digital servo signal processing device that determines servo positioning information based on a burst signal to be generated, wherein the digital signal converted by the analog-to-digital converter is converted into a signal whose output cycle is longer than the sample cycle of the analog-to-digital converter. A digital servo signal processing device comprising a period conversion means for converting. 12. The digital servo signal processing device according to claim 11, wherein the period conversion unit includes at least one delay circuit connected to an output side of the analog-to-digital conversion unit; A digital servo signal processing device, comprising: an adder for adding an output and an output of the delay circuit at a timing corresponding to a delay time of the delay circuit and outputting the result. 13. The digital servo signal processing device according to claim 11, wherein said analog-to-digital conversion means samples said burst signal asynchronously and synchronizes servo signals other than said burst signal. A digital servo signal processing device, comprising: a sample cycle switching means for switching a sample cycle of the analog-to-digital conversion means so as to perform sampling. 14. The digital servo signal processing device according to claim 13, wherein a servo address mark included in the servo signal is detected from a signal output from the period conversion means, and a servo address mark detection signal is generated. A digital servo signal processing device, comprising: a servo address mark detection unit that outputs a signal; and the sample period switching unit switches a sample period of the analog-to-digital conversion unit according to the servo address mark detection signal. 15. A digital servo signal processing apparatus according to claim 3, 5, 10 or 14, reading means for reading a signal from said disk medium, and digital signal sequentially sampled and converted by said analog-to-digital conversion means. Arithmetic means for respectively adding burst signals included in the servo; decoding means for decoding a gray code included in the servo signal based on the digital signal converted by the analog-to-digital conversion means; Calculating means for obtaining the servo positioning information based on the obtained addition result and the gray code obtained by the decoding means; and the reading means based on the servo positioning information obtained by the calculating means. Position control means for controlling a position on the disk medium. Apparatus. 16. A disk medium on which a burst signal is recorded at a frequency offset from the frequency of a servo signal other than the burst signal, reading means for reading a signal from the disk medium, servo signals and data read from the disk medium Analog-to-digital conversion means for converting a signal into a digital signal; arithmetic means for adding burst signals included in the servo, which are sequentially sampled and converted to digital signals by the analog-to-digital conversion means; and the analog-to-digital conversion means Decoding means for decoding a gray code included in the servo signal based on the digital signal converted in the above, based on the addition result obtained by the arithmetic means and the gray code obtained by the decoding means, Calculating means for obtaining positioning information of the servo; and the calculating means Position control means for controlling the position of the reading means on the disk medium based on the obtained positioning information of the servo, wherein the analog-to-digital conversion means is adapted to perform the sampling when the burst signal is sampled. A disk medium reproducing apparatus which performs synchronization in synchronization with a servo signal other than a burst signal. 17. A disk medium on which a burst signal is recorded at a frequency offset from the frequency of a servo signal other than the burst signal.