JP2001055560A - Polishing agent and method for polishing substrate by using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a polishing agent capable of efficiently conducting removal and flattening of excessively formed silicon oxide films and films for embedding a metal and the like at a high level and easily conducting process control in a recess CMP technique such as separation and formation of shallow trenches, metal-embedding wiring-formation and the like and a CMP technique of flattening interlaminar insulating films, and also provide a method for polishing a substrate by using the same. SOLUTION: This polishing agent contains abrasive grains and an anionic surface active agent with a concentration of the anionic surface active agent of 0.5-10 pts.wt. based on 100 pt.wt. slurry. It is preferred that the abrasive grains contain particles having grain boundaries. With the use of the polishing agent in an conventional polishing machine having a holder for holding a semiconductor substrate and a platen to which an abrasive pad is applied, polishing is conducted under a pressure of pressing the semiconductor substrate having a film to be polished being 100-1,000 gf/cm2 while continuously supplying the polishing agent to the abrasive pad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to polishing for use in semiconductor device manufacturing technology, and more particularly to a polishing process for a substrate surface, in particular, a process for forming a buried layer in trenches of shallow trench device isolation, capacitors, metal wirings, and the like. The present invention relates to an abrasive used in a step of planarizing an interlayer insulating film and the like, and a method for polishing a substrate using the same.

[0002]

2. Description of the Related Art In the current manufacturing process of ULSI semiconductor devices, processing techniques for high density and miniaturization have been researched and developed. One of them, CMP (Chemical Mechanical Polishing) technology, has become an essential technology. The CMP technology in the manufacturing process of a semiconductor device includes a recess CMP technology for removing an extra film formation portion of a film formation layer buried in a groove in element isolation formation, memory capacitor formation, plug and buried metal wiring formation, and the like. And a planarization CMP technique after forming an interlayer insulating film. LOCOS (local oxidation of silicon) has been used in the generation of the design rule of 0.5 μm or more in the device isolation forming technology in the integrated circuit. However, with the further miniaturization of the processing size, the shallow trench having a smaller device isolation width has been used. Trench isolation technology is being adopted. In the shallow trench isolation, CMP is an indispensable technique for removing an extra silicon oxide film buried on a substrate. Also in the metal wiring formation technology, in the generation of the design rule of 0.25 μm or more, W or the like is used for the Al wiring and the plug on the interlayer insulating film. Cu or Cu to fill
-Al alloys are being adopted. As the wiring technology of Cu or Cu / Al alloy, embedded wiring technology such as damascene or dual damascene is under study, and CMP is an essential technology for removing an extra metal film embedded on a substrate. In forming a capacitor of a memory element, a recessed CMP technique of a silicon oxynitride, a tantalum oxide film, and other ferroelectrics is indispensable in order to realize a trench structure or a complicated stacked structure.

Conventionally, in a semiconductor device manufacturing process, an insulating film such as silicon oxide, a capacitor ferroelectric film, a metal or metal alloy for wiring, etc. formed by a method such as plasma-CVD, low-pressure-CVD, sputtering, and electrolytic plating. In general, a method of polishing in a single step using a fumed silica or alumina-based abrasive as a chemical mechanical abrasive for forming a flattened and buried layer has been studied. However,
In such a polishing method, there is a technical problem that the flatness of the pattern is poor, and the characteristics vary due to thickness variation of the buried film and dishing.

In the conventional CMP technology for forming a flattening layer and a buried layer, the polishing rate of a convex portion greatly differs depending on the difference in pattern density or the size difference, and polishing of a concave portion also progresses. There is a technical problem that a high level of planarization cannot be realized in the whole. Therefore, in order to improve the flatness by reducing the difference between the polishing rate of the buried portion that becomes a concave portion after the burying layer is formed and the polishing speed of the convex portion that needs to remove the film layer after the burying layer is formed, to improve flatness. 2. Description of the Related Art A technique of adding an etch-back step of partially removing a film to be polished on a convex portion by etching has been widely adopted. However, since the number of processes increases, there is a problem in terms of manufacturing cost.

In addition, CMP for forming a buried layer
In the technology and the CMP technology for flattening an interlayer film, it is difficult to detect an ideal end point by a polishing apparatus. Therefore, a process management method of controlling a polishing amount by a polishing time is generally performed. However, there has been a problem that not only the change in the pattern step shape but also the state of the polishing cloth significantly changes the polishing rate, making process management difficult.

In the shallow trench isolation, a silicon nitride film is mainly formed as a mask and a stopper except for the silicon oxide film buried portion for element isolation. In order to realize stable element isolation characteristics, silicon nitride in the wafer is required. It is necessary to minimize the variation in the remaining film thickness. For this purpose, after the silicon nitride film is exposed, it is necessary that the polishing rate be reduced. The polishing rate ratio between the silicon oxide film and the silicon nitride film (the polishing rate of the silicon oxide film / the polishing rate of the silicon nitride film) is required. It is desirable that the polishing rate is large. However, the conventional polishing method using a single polishing step using a silica-based polishing agent has a problem that the polishing rate ratio is only about 2 to 3 and a sufficient process margin cannot be obtained. In the formation of a metal buried wiring or a capacitor, polishing must be completed when the film-forming base layer in which the buried groove is formed is exposed. An abrasive having a large polishing rate ratio between the substrate and the underlying film is used. However, on the other hand, when an abrasive having a large polishing rate ratio is used, there is a problem that dishing of the buried layer becomes large.

[0007] An abrasive containing cerium oxide or the like, which can obtain a higher polishing rate of a silicon oxide film than a silica-based abrasive, is also used. However, there are problems such as difficulty in process management because the polishing rate is too high, and large dependence of the polishing rate on the pattern of the film to be polished on the substrate. In addition, there is also a problem that the projections are less likely to be removed as the film pattern to be polished on the substrate becomes finer because the particles are generally used at a relatively low particle concentration, and only the polishing of the peripheral portion proceeds. A polishing agent containing cerium oxide can provide a polishing rate ratio of a silicon oxide film and a silicon nitride film approximately twice that of a silica-based polishing agent, but it is still not practically sufficient.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a shallow
Recess C for trench isolation formation, metal buried wiring formation, etc.
In the MP technology and the CMP technology for planarizing the interlayer insulating film,
A polishing agent capable of efficiently and efficiently removing and flattening an excess film forming layer of a buried film such as a silicon oxide film and a metal and easily performing process control, and a method of polishing a substrate using the same. To provide.

[0009]

The abrasive of the present invention is an abrasive containing abrasive grains and an anionic surfactant, wherein the concentration of the anionic surfactant is 0.1 to 100 parts by weight of the slurry. The abrasive is in the range of 5 parts by weight to 10 parts by weight. When the polishing is performed using this polishing agent, the flattening of the interlayer insulating film and the flattening of the buried film such as the formation of the shallow trench element isolation can be performed efficiently and at a high level.
In the above abrasive, when the abrasive grains include particles having crystal grain boundaries, higher effects can be obtained. In polishing using a normal abrasive, the polishing rate generally shows a characteristic proportional to the polishing pressure. When the abrasive of the present invention is used, the polishing rate has a polishing pressure dependence with an inflection point. The polishing pressure dependence at which the polishing rate has an inflection point means that the polishing rate of a substrate without a pattern becomes a point at which the polishing rate becomes an inflection point, compared to the polishing rate change almost proportional to the polishing pressure when no surfactant is added. When the polishing pressure is sufficiently small and is higher than the pressure at which the inflection point is obtained, a polishing rate sufficiently higher than the polishing rate at a polishing pressure equal to or lower than the inflection point is obtained. In addition, it shows a characteristic that the polishing pressure at which an inflection point appears changes depending on the concentration of the surfactant. As the anionic surfactant contained in the abrasive of the present invention, an organic polymer anionic surfactant is preferably used. As the anionic surfactant, those containing an ammonium acrylate salt as a copolymerization component are preferably used. A predetermined substrate such as a semiconductor chip on which at least a silicon oxide film is formed can be polished using the polishing slurry of the present invention.

[0010]

DETAILED DESCRIPTION OF THE INVENTION An abrasive containing abrasive grains and an anionic surfactant, wherein the concentration of the anionic surfactant is in the range of 0.5 to 10 parts by weight per 100 parts by weight of the slurry. By the polishing agent, the polishing rate has a polishing pressure dependency with an inflection point, so that the effective polishing pressure of the concave portion of the substrate on which the pattern is formed is P ₁ , and the effective polishing pressure of the convex portion is P ₂ , By adjusting the set polishing load P and the concentration of the additive such that the pressure P ′ at which the inflection point appears in the polishing rate of the substrate without the pattern becomes P ₂ > P ′>P> P ₁ , It is possible to realize a characteristic of selectively polishing a convex portion to which a polishing pressure higher than a pressure at an inflection point is applied according to a pattern shape. In addition, since the polishing rate after the flattening becomes a polishing rate of a set polishing pressure smaller than the pressure at which the inflection point appears, the polishing after the flattening hardly progresses, so that the process management by the polishing time is easy. become. The dependence of the polishing rate by this additive on the polishing pressure is described in the literature (IEDM96 (International Electronic Device Meeting)).
Proceedings (1996) p.349-352). As a result, high-efficiency, high-level planarization with little pattern density and small size dependence can be realized.

A higher effect is realized by the above-mentioned abrasive, wherein the abrasive contains abrasive grains having grains having grain boundaries.

In the present invention, the term "anionic surfactant" refers to a water-soluble organic solvent such as an acrylic acid polymer and its ammonium salt, a methacrylic acid polymer and its ammonium salt, and polyvinyl alcohol, which do not contain metal ions. Examples include polymers, water-soluble anionic surfactants such as ammonium lauryl sulfate and polyoxyethylene lauryl ether ammonium sulfate. In particular, at least one surfactant selected from water-soluble anionic surfactants such as a polymer dispersant containing an ammonium salt as a copolymer component is used. In addition, a water-soluble nonionic surfactant, a water-soluble anionic surfactant, a water-soluble cationic surfactant, or the like may be used in combination. These surfactant addition amounts are based on 100 parts by weight of the slurry.
A range of 0.5 to 10 parts by weight is preferred. Further, the molecular weight of the surfactant is preferably 100 to 50,000,
2000 to 20000 is more preferable. As a method of adding the additive, it is preferable that the additive is mixed with the abrasive dispersion just before polishing. When a structure that mixes well in the slurry supply pipe of the polishing device is provided, adjust the supply rates of the abrasive dispersion and the aqueous solution of the additive individually and mix them to a predetermined concentration in the pipe. Is also possible. When stored for a long time after mixing the additives, the particle size distribution of the abrasive may change, but since the polishing rate and polishing characteristics such as scratches are not significantly affected, the method of adding the surfactant is There is no restriction.

The abrasive grains contained in the abrasive of the present invention are inorganic oxide particles such as cerium oxide, silicon oxide and aluminum oxide, and cerium oxide particles are preferably used. Here, the concentration of the abrasive grains is not limited, but is preferably in the range of 0.5 to 15% by weight from the viewpoint of easy handling of the suspension. Further, the primary particle diameter of the abrasive grains is preferably from 5 to 600 nm, more preferably from 30 to 500 nm. Further, since it is used for polishing a semiconductor chip, the content of alkali metals and halogens is preferably suppressed to 1 ppm or less. In the present invention, the primary particle size is determined by a scanning electron microscope (for example, S-900 manufactured by Hitachi, Ltd.).
(Type). The abrasive of the present invention is of high purity, and contains Na, K, Si, Mg, Ca, Zr, Ti, N
i, Cr and Fe are each 1 ppm or less, and Al is 10 p
pm or less. The average particle size of the particles in the abrasive is preferably from 100 to 2000 nm,
More preferably, it is 0 to 1500 nm. If the average particle size of the particles is less than 100 nm, the polishing rate becomes too low, and if it exceeds 2000 nm, the film to be polished tends to be easily damaged. In the present invention, the particle size of the particles in the abrasive is measured by a laser diffraction type particle size distribution meter (for example, MA Co., Ltd.).
It is measured with a master sizer manufactured by LVERN.

As a method for forming an inorganic insulating film to which the polishing agent of the present invention and a method for polishing a substrate using the same are applied, there are a constant pressure CVD method, a plasma CVD method and the like. Constant pressure CV
In forming a silicon oxide insulating film by the D method, monosilane: SiH _{4 is} used as a Si source, and oxygen: O ₂ is used as an oxygen source. This is obtained by performing the SiH ₄ —O ₂ -based oxidation reaction at a low temperature of about 400 ° C. or less. When doping phosphorus: P for planarizing the surface by high temperature reflow,
It is preferable to use H ₄ -O ₂ -PH ₃ system reaction gas.
The plasma CVD method has an advantage that a chemical reaction requiring a high temperature can be performed at a low temperature under normal thermal equilibrium. The plasma generation method includes two types, a capacitive coupling type and an inductive coupling type. As a reaction gas, a SiH ₄ -N ₂ O-based gas using SiH ₄ as a Si source and N ₂ O as an oxygen source and TEOS- using tetraethoxysilane (TEOS) as a Si source are used.
O ₂ -based gas (TEOS-plasma CVD method) may be used. Substrate temperature is 250-400 ° C, reaction pressure is 67-4
A range of 00 Pa is preferred. As described above, the silicon oxide insulating film used in the present invention may be doped with elements such as phosphorus and boron. Similarly, the formation of a silicon nitride film by low-pressure CVD is performed by using dichlorosilane: SiH ₂ C as a Si source.
l ₂ , ammonia: NH ₃ is used as a nitrogen source. This S
The iH ₂ Cl ₂ -NH ₃ based oxidation reaction can be obtained by performed at a high temperature of 900 ° C.. The plasma CVD method uses SiH ₄ − using SiH ₄ as a Si source and NH ₃ as a nitrogen source.
An NH ₃ -based gas may be used. Substrate temperature is 300-400
C is preferred.

The predetermined substrate is a semiconductor substrate, that is, a semiconductor substrate in which circuit elements and wiring patterns are formed,
A substrate in which at least a silicon oxide film is formed over a semiconductor substrate such as a semiconductor substrate at a stage where circuit elements are formed can be used. The silicon oxide film layer formed on such a semiconductor substrate is polished by the above-mentioned polishing agent and a substrate polishing method using the same, whereby irregularities on the surface of the silicon oxide film layer are eliminated, and the entire surface of the semiconductor substrate is removed. Make it a smooth surface. This is completed when applied to the step of flattening the interlayer insulating film.In the case of the shallow trench isolation, the flattened silicon oxide film is further polished to the underlying silicon nitride layer. Then, only the silicon oxide film embedded in the element isolation portion is left. At this time, if the polishing rate ratio with respect to silicon nitride serving as a stopper is large, the polishing rate after exposure of the nitride film is reduced, and the polishing process margin is increased. In addition, in order to use it for shallow trench isolation, it is necessary that scratch generation during polishing is small. Here, as a polishing apparatus, a general polishing apparatus having a holder for holding a semiconductor substrate and a platen on which a polishing cloth (pad) is attached (a motor or the like capable of changing the number of rotations is attached) is used. it can. As the polishing cloth, general nonwoven fabric, foamed polyurethane, porous fluororesin and the like can be used, and there is no particular limitation. Also,
Preferably, the polishing cloth is subjected to groove processing for storing the abrasive. The polishing conditions are not limited, but the rotation speed of the platen is preferably low at 100 rpm or less so that the semiconductor does not jump out. The pressing pressure of the semiconductor substrate having the film to be polished against the polishing cloth is preferably 100 to 1000 gf / cm ² , and in order to satisfy the uniformity of the polishing rate within the wafer surface and the flatness of the pattern, 200 to 500 gf / cm ^2. /
cm ² is more preferable. During polishing, an abrasive is continuously supplied to the polishing cloth by a pump or the like. Although the supply amount is not limited, it is preferable that the surface of the polishing cloth is always covered with the abrasive.

After the polishing, the semiconductor substrate is preferably washed well in running water, and then dried using a spin drier or the like to remove water droplets adhering to the semiconductor substrate. In this manner, after forming a shallow trench isolation on a Si substrate, an insulating layer is formed, or after a silicon oxide insulating film layer is planarized, an aluminum wiring is formed thereon, and an oxide layer formed thereon is formed. The silicon film is planarized by the above method. An upper aluminum wiring is formed on the flattened silicon oxide film layer, and a silicon oxide film is formed between the wirings and on the wiring, and then polished by the polishing agent of the present invention and the substrate polishing method using the same. By doing so, unevenness on the surface of the insulating film is eliminated, and a smooth surface is formed over the entire surface of the semiconductor substrate. By repeating this process a predetermined number of times, a semiconductor having a desired number of layers is manufactured. Alternatively, after forming a shallow trench isolation on a Si substrate, a trench for buried wiring is formed on the interlayer insulating film layer and the surface thereof, and TiN is formed by sputtering.
A barrier metal layer such as Al and TaN and a seed layer for wiring metal are formed, and Cu or a Cu.Al alloy is formed by electrolytic plating or the like. By applying the abrasive of the present invention and the method of polishing a substrate using the same to this film formation layer, metal can be embedded only in the wiring groove. By repeating this process a predetermined number of times, a semiconductor having a desired number of layers is manufactured.

In addition, in the step of forming a capacitor of a memory element, in a trench type cell structure, when forming a buried structure such as polysilicon or silicon oxynitride,
Even in a stacked cell structure, an embedding process may be employed to form a complicated structure, and the polishing of the present invention is performed on ferroelectric materials such as STO and BST in addition to silicon oxide silicon and tantalum oxide films. An agent and a polishing method using the same are applied.

The polishing agent of the present invention and the method of polishing a substrate using the same include a silicon oxide film and a silicon nitride film formed on a semiconductor substrate, a metal film such as Cu, Cu.Al alloy, and a ferroelectric film. Rather, a silicon oxide film formed on a wiring board having predetermined wiring, glass, an inorganic insulating film such as silicon nitride, a metal film, an optical glass such as a photomask, a lens, a prism, and the like, an inorganic conductive film such as ITO, and glass Optical integrated circuit, optical switching element, optical waveguide,
Optical fiber end face, optical single crystal such as scintillator,
It is also used as a polishing agent and polishing method for solid laser single crystals, blue laser LED sapphire substrates, semiconductor single crystals such as SiC, GaP, and GaAs, magnetic disk glass substrates, magnetic heads, and the like.

[0019]

EXAMPLES (Example 1) (Preparation of cerium oxide particles) 2 kg of cerium carbonate hydrate
Was put in a platinum container, and calcined at 800 ° C. for 2 hours in the air to obtain about 1 kg of yellowish white powder. When this powder was subjected to phase identification by an X-ray diffraction method, it was confirmed that the powder was cerium oxide. The particle diameter of the calcined powder was 30 to 100 μm. When the surface of the fired powder particles was observed with a scanning electron microscope, grain boundaries of cerium oxide were observed. When the primary particle diameter of cerium oxide surrounded by the grain boundaries was measured, the median of the volume distribution was 190 nm and the maximum was 500 nm. 1 kg of cerium oxide powder was dry-ground using a jet mill. Observation of the pulverized particles with a scanning electron microscope revealed that, in addition to the small particles having the same size as the primary particle diameter, large pulverized residual particles of 1 to 3 μm and 0.5 to 1
Residual particles of μm were mixed.

(Preparation of Cerium Oxide Slurry) 1 kg of the cerium oxide particles prepared above, 23 g of an aqueous solution of ammonium polyacrylate (40% by weight), and deionized water 8977
g was mixed and subjected to ultrasonic dispersion for 10 minutes while stirring. The obtained slurry was filtered through a 1-micron filter, and further 5% by weight of slurry was obtained by adding deionized water. The slurry pH was 8.3. A mixture of 600 g of the above cerium oxide slurry (solid content: 5% by weight), 180 g of an aqueous solution of polyacrylic acid (100%) ammonium salt having a pH of 6.5 and a molecular weight of 5,000 as a surfactant (40% by weight), and 2220 g of deionized water was mixed. Thus, a cerium oxide abrasive (cerium oxide solid content: 1% by weight) was prepared by adding 2.4 parts by weight of a surfactant to 100 parts by weight of the slurry. The pH of the polishing slurry was 6.9, and the viscosity calculated from the values measured by an Ubbelohde viscometer and a specific gravity meter was 1.41 mPa · s. In addition, in order to measure the particles in the abrasive with a laser diffraction type particle size distribution analyzer, the particles were diluted to an appropriate concentration and measured. As a result, the median particle diameter was 300 nm.
Met.

(Blanket Wafer Polishing 1) Diameter 20
A blanket wafer having a 1000-nm silicon oxide film formed on a 0-mm Si substrate was manufactured. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. , And the processing pressure is 100 gf / c
is set to m ^2, the above-mentioned cerium oxide abrasive surface plate: dropwise (solid content 1 wt%) at a rate of 200 cc / min, the platen and the wafer was rotated for 1 minute at 50 rpm, silicon oxide The film was polished. Similarly, set the processing pressure to 200
Polishing the other wafer is set to 100 gf / cm ² every range of ~800gf / cm ^2. The polished wafer was washed and dried, and the film thickness was measured with an interference film thickness meter to calculate the change in film thickness before and after polishing. As a result, the pressure was 100 gf /
The polishing rate of cm ² is 24 nm / min, and the pressure is 200 gf.
/ Cm ² polishing rate is 41 nm / min, pressure 300 g
The polishing rate of f / cm ² is 65 nm / min, and the pressure is 400
The polishing rate of gf / cm ² is 85 nm / min, and the pressure is 50.
Polishing rate of 0 gf / cm ² is 105 nm / min, the polishing rate of the pressure 600 gf / cm ² is 123 nm / min,
The polishing rate at a pressure of 700 gf / cm ² is 146 nm / mi.
n, the polishing rate at a pressure of 800 gf / cm ² is 302 nm / m
and the inflection point of the polishing rate was obtained at a processing pressure of 700 gf / cm ² .

(Blanket wafer polishing 2) Diameter 20
A blanket wafer having a 1000 nm silicon oxide film formed on a 0 mm Si substrate and a blanket wafer having a 100 nm silicon nitride film formed thereon were produced. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. , And the processing pressure is 3
Set to 00gf / cm ^2, platen to the cerium oxide abrasive (solid content: 1 wt%) of 200 cc / min
The platen and the wafer were rotated at 50 rpm for 1 minute while dripping at a speed of 1 to polish the silicon oxide film. Similarly, the processing pressure was set to 300 gf / cm ² , and the silicon nitride film was polished. The polished wafer was washed and dried, and the film thickness was measured with an interference film thickness meter to calculate the change in film thickness before and after polishing. As a result, the polishing rate of the silicon oxide film was 65 nm / min, the polishing rate of the silicon nitride film was 6 nm / min, and the polishing rate ratio (silicon oxide film polishing rate / silicon nitride film polishing rate) was 11
Met.

(Polished pattern wafer) Diameter 200 mm
After forming a 100 nm silicon nitride film on the Si substrate, a photoresist was applied, and dots of the 100 × 100 μm ² silicon nitride film were left as a mask material at a pitch of 158 μm, and a 400 nm trench was formed in the Si substrate by etching. Subsequently, after forming a thin thermal oxide film, a silicon oxide film was formed to a thickness of 550 nm by a low-pressure CVD method, and a pattern wafer having a silicon oxide film embedded in a trench of 500 nm including a silicon nitride film was manufactured. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. Further, the processing pressure was set to 300 gf / cm ² . The above cerium oxide abrasive (solid content:
(1% by weight) was dropped at a speed of 200 cc / min, and the platen and the wafer were rotated at 50 rpm for 3 minutes to polish the silicon oxide film. Polishing was performed under the same conditions with a polishing time of 4 minutes and 5 minutes. After the wafer was washed and dried, the thickness of the silicon oxide film on the silicon nitride film and the trench portion was measured by an interference film thickness meter, and the step at the boundary was measured by a stylus type step meter. The measurement result of the wafer after polishing for 3 minutes is
The thickness of the silicon oxide film on the silicon nitride film was 28 nm, the thickness of the silicon oxide film in the trench portion was 520 nm, and the remaining steps were at least <10 nm or less, indicating that the planarization was completed. . The measurement result of the wafer after polishing for 4 minutes shows that the silicon oxide film on the silicon nitride film has disappeared, the thickness of the silicon nitride film is 96 nm, and the thickness of the silicon oxide film in the trench portion is 485 nm. The measurement results of the subsequent wafer show that the thickness of the silicon nitride film is 90 nm, and the thickness of the silicon oxide film in the trench portion is 469 nm. We were able to.

Example 2 (Preparation of Cerium Oxide Particles) Cerium carbonate hydrate 2 kg
Was put in a platinum container, and calcined at 800 ° C. for 2 hours in the air to obtain about 1 kg of yellowish white powder. When this powder was subjected to phase identification by an X-ray diffraction method, it was confirmed that the powder was cerium oxide. The particle diameter of the calcined powder was 30 to 100 μm. When the surface of the fired powder particles was observed with a scanning electron microscope, grain boundaries of cerium oxide were observed. When the primary particle diameter of cerium oxide surrounded by the grain boundaries was measured, the median of the volume distribution was 190 nm and the maximum was 500 nm. 1 kg of cerium oxide powder was wet-pulverized using a wet bead mill. Observation of the pulverized particles with a scanning electron microscope revealed that the pulverized particles were pulverized into small particles having the same size as the primary particle diameter.

(Preparation of Cerium Oxide Slurry) 1 kg of the cerium oxide particles prepared above, 23 g of an aqueous solution of ammonium polyacrylate (40% by weight), and deionized water 8977
g was mixed and subjected to ultrasonic dispersion for 10 minutes while stirring. The obtained slurry was filtered through a 1-micron filter, and further 5% by weight of slurry was obtained by adding deionized water. The slurry pH was 8.3. 600 g of the above cerium oxide slurry (solid content: 5% by weight), 75 g of a polyacrylic acid (100%) ammonium salt aqueous solution (40% by weight) having a pH of 6.5 and a molecular weight of 5,000 as a surfactant, and 2,325 g of deionized water were mixed. Thus, a cerium oxide abrasive (cerium oxide solid content: 1% by weight) was prepared by adding 1.0 part by weight of a surfactant to 100 parts by weight of the slurry. The pH of the polishing slurry was 7.3, and the viscosity calculated from the values measured by an Ubbelohde viscometer and a specific gravity meter was 1.19 mPa · s. In addition, in order to measure the particles in the abrasive with a laser diffraction type particle size distribution analyzer, the particles were diluted to an appropriate concentration and measured. As a result, the median particle diameter was 200 nm.
Met.

(Blanket Wafer Polishing 1) Diameter 20
A blanket wafer having a 1000-nm silicon oxide film formed on a 0-mm Si substrate was manufactured. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. , And the processing pressure is 100 gf / c
is set to m ^2, the above-mentioned cerium oxide abrasive surface plate: dropwise (solid content 1 wt%) at a rate of 200 cc / min, the platen and the wafer was rotated for 1 minute at 50 rpm, silicon oxide The film was polished. Similarly, set the processing pressure to 200
Polishing the other wafer is set to 100 gf / cm ² every range of ~800gf / cm ^2. The polished wafer was washed and dried, and the film thickness was measured with an interference film thickness meter to calculate the change in film thickness before and after polishing. As a result, the pressure was 100 gf /
The polishing rate in cm ² is 20 nm / min, and the pressure is 200 gf.
/ Cm ² polishing rate is 38 nm / min, pressure 300 g
The polishing rate of f / cm ² is 50 nm / min and the pressure is 400
The polishing rate of gf / cm ² is 78 nm / min, and the pressure is 50.
Polishing rate of 0 gf / cm ² is 120 nm / min, the polishing rate of the pressure 600 gf / cm ² is 135 nm / min,
The polishing rate at a pressure of 700 gf / cm ² is 161 nm / mi.
n, the polishing rate at a pressure of 800 gf / cm ² is 285 nm /
min, and an inflection point of the polishing rate was obtained at a processing pressure of 700 gf / cm ² .

(Blanket Wafer Polishing 2) Diameter 20
A blanket wafer having a 1000 nm silicon oxide film formed on a 0 mm Si substrate and a blanket wafer having a 100 nm silicon nitride film formed thereon were produced. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. , And the processing pressure is 3
Set to 00gf / cm ^2, platen to the cerium oxide abrasive (solid content: 1 wt%) of 200 cc / min
The platen and the wafer were rotated at 50 rpm for 1 minute while dripping at a speed of 1 to polish the silicon oxide film. Similarly, the processing pressure was set to 300 gf / cm ² , and the silicon nitride film was polished. The polished wafer was washed and dried, and the film thickness was measured with an interference film thickness meter to calculate the change in film thickness before and after polishing. As a result, the polishing rate of the silicon oxide film was 51 nm / min, the polishing rate of the silicon nitride film was 6 nm / min, and the polishing rate ratio (silicon oxide film polishing rate / silicon nitride film polishing rate) was 9.

(Polishing of Pattern Wafer) Diameter 200 mm
After forming a 100 nm silicon nitride film on the Si substrate, a photoresist was applied, and dots of the 100 × 100 μm ² silicon nitride film were left as a mask material at a pitch of 158 μm, and a 400 nm trench was formed in the Si substrate by etching. Subsequently, after forming a thin thermal oxide film, a silicon oxide film is formed to a thickness of 550 nm by a low-pressure CVD method, and a pattern wafer is formed by embedding the silicon oxide film in a trench of 500 nm including the silicon nitride film thickness. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. Further, the processing pressure was set to 300 gf / cm ² . The above cerium oxide abrasive (solid content:
(1% by weight) was dropped at a speed of 200 cc / min, and the platen and the wafer were rotated at 50 rpm for 3 minutes to polish the silicon oxide film. Similarly, polishing was performed at polishing times of 4 minutes and 5 minutes. After the wafer was washed and dried, the thickness of the silicon oxide film on the silicon nitride film and the trench portion was measured by an interference film thickness meter, and the step at the boundary was measured by a stylus type step meter. The measurement result of the wafer after polishing for 3 minutes shows that the thickness of the silicon oxide film on the silicon nitride film is 112 nm, the thickness of the silicon oxide film in the trench portion is 535 nm, and the remaining step is 80 nm.
nm. The measurement result of the wafer after polishing for 4 minutes shows that the thickness of the silicon oxide film on the silicon nitride film is 24 nm, the thickness of the silicon oxide film in the trench portion is 497 nm, and the step is 30 nm or less, and the flatness is reduced. It turned out to be finished. The measurement result of the wafer after polishing for 5 minutes shows that the oxide film on the silicon nitride film has disappeared, the thickness of the silicon nitride film is 98 nm, and the thickness of the silicon oxide film in the trench portion is 470.
and polishing hardly progresses after 4 minutes polishing,
The target silicon nitride film could be polished.

Comparative Example 1 (Blanket Wafer Polishing) A blanket wafer having a silicon oxide film having a thickness of 1000 nm formed on a Si substrate having a diameter of 200 mm and a blanket wafer having a silicon nitride film having a thickness of 100 nm formed thereon were manufactured. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. , And the processing pressure is 300 gf / cm
^The surface plate and the wafer were rotated at 50 rpm for 1 minute while dropping (solid content: 12.5% by weight) at a rate of 200 cc / min using a commercially available silica slurry on the platen, and then oxidized. The silicon film was polished. Similarly, the processing pressure was set to 300 gf / cm ² , and the silicon nitride film was polished.
The polished wafer was washed and dried, and the film thickness was measured with an interference film thickness meter to calculate the change in film thickness before and after polishing. As a result, the polishing rate of the silicon oxide film was 175 nm / min, the polishing rate of the silicon nitride film was 70 nm / min, and the polishing rate ratio (silicon oxide film polishing rate / silicon nitride film polishing rate) was 2.
It was 5.

(Polishing of Pattern Wafer) Diameter 200 mm
After forming a 100 nm silicon nitride film on the Si substrate, a photoresist was applied, and dots of the 100 × 100 μm ² silicon nitride film were left as a mask material at a pitch of 158 μm, and a 400 nm trench was formed in the Si substrate by etching. Subsequently, after forming a thin thermal oxide film, a silicon oxide film is formed to a thickness of 550 nm by a low-pressure CVD method, and a pattern wafer is formed by embedding the silicon oxide film in a trench of 500 nm including the silicon nitride film thickness. The pattern wafer is set on a holder to which a suction pad for attaching a substrate to be held is attached, and the holder is placed with the insulating film face down on a platen having a diameter of 600 mm to which a polishing pad made of porous urethane resin is attached. Further, the processing pressure was set to 300 gf / cm ² . Commercially available silica slurry (solid content: 1
(2.5% by weight) at a rate of 200 cc / min while rotating the platen and the wafer at 50 rpm for 2 minutes.
The silicon oxide film was polished. Similarly, polishing was performed at polishing times of 3 minutes and 4 minutes. After the wafer was washed and dried, the thickness of the silicon oxide film on the silicon nitride film and the trench portion was measured by an interference film thickness meter, and the step at the boundary was measured by a stylus type step meter. The measurement result of the wafer after polishing for 2 minutes shows that the thickness of the silicon oxide film on the silicon nitride film is 12 nm, the thickness of the silicon oxide film in the trench portion is 324 nm, and the remaining step is 19 nm.
It was about 0 nm. The measurement result of the wafer after polishing for 3 minutes shows that the silicon oxide film on the silicon nitride film has disappeared, the thickness of the silicon nitride film is 32 nm, the thickness of the silicon oxide film in the trench portion is 220 nm, and the remaining step is It was about 210 nm. The measurement result of the wafer after polishing for 4 minutes showed that the silicon nitride film disappeared and the Si substrate was exposed. Polishing could be performed to the target position of the silicon nitride film in a polishing time of 3 minutes. However, since the residual step was large at> 150 nm and the polishing rate after the silicon nitride film was exposed did not decrease so much, one polishing was performed. Then, it is difficult to set the polishing time.

[0031]

According to the polishing method of the present invention, recess CMP for forming a shallow trench isolation, forming a metal buried wiring, etc.
Technology and planarization of interlayer insulating film In the CMP technology, the removal and flattening of an extra film-forming layer of a buried film such as a silicon oxide film and a metal can be efficiently performed at a high level and the process management can be easily performed. .

Claims (3)

[Claims] 1. An abrasive containing abrasive grains and an anionic surfactant, wherein the concentration of the anionic surfactant is in the range of 0.5 to 10 parts by weight based on 100 parts by weight of the slurry. Abrasive. 2. An abrasive, wherein the abrasive grains of the abrasive include particles having crystal grain boundaries. 3. A method for polishing a substrate, comprising: polishing a semiconductor chip on which at least a silicon oxide film is formed with the polishing slurry according to claim 1.