JP2001053142A - Method for manufacturing integrated circuit having shallow trench insulation region - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a planarized shallow trench insulation region, without the use of chemical and mechanical polishing by removing a part of an insulation layer formed on a material layer to expose a part of a trench insulation layer, and then removing the insulation layer on the material layer using a life-off process. SOLUTION: A pad oxide layer 105 is formed between a material layer 110 and a substrate 100, and after a trench is formed by etching, an insulation layer 130 is formed on the material layer 110 and in the trench. The material and deposition process of the insulation layer 130 are selected to form a thin region 135. When the material layer 110 of SiN is etched, using hot phosphoric acid after a region 125 of the material layer 110 is exposed by removing the thin region 135, an insulation region 140 above the pad oxide has a step height in the range of 200-1,000 Å and the insulation region 140 has an overall thickness X5 in the range of 3,500-4,000 Å. According to the method, a planarized shallow trench insulation region can be formed, without using chemical and mechanical polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to integrated circuits, and more particularly, to a method for forming a shallow trench isolation structure in an integrated circuit.

[0002]

2. Description of the Related Art Shallow trench isolation
(lation: STI) is a chemical mechanical polishing
Combined with shing (CMP), it is an important isolation scheme for sub-0.2 micron devices. This technique has the advantage of shrinkability and planar shape. A typical STI process involves forming an oxide layer for a pad on a substrate followed by a nitride layer. The nitride layer, the pad oxide layer, and the substrate are etched after a patterned photoresist layer is formed over the nitride layer. The patterned photoresist includes a window corresponding to the insulating region. After that, an oxide layer is blanket deposited and the photoresist is removed.
Fill 40.

[0003] Blanket deposition forms oxide in the trenches and on the non-trenched surfaces. Therefore, a planar top surface must be formed using some type of planarization process. Chemical mechanical polishing (CMP) of as-deposited material is an approach. However, this technique suffers from local polishing rate fluctuations and dishing phenomena and problems due to residual oxides. These variations are due to local variations in pattern density and etching of different materials at different rates during CMP.

[0004] Pattern density is also referred to as variation in the shape of an integrated circuit. The local CMP rate strongly depends on the pattern density near the trench 115. One problem resulting from this pattern variation is dishing in areas where the pattern density is low.

One way to solve these problems is to use CM
The purpose is to provide a reverse tone oxide etch to improve the uniformity of P. In this case, a patterned photoresist is formed over the oxide layer, and this pattern corresponds to the inverse tone of the pattern forming the trench. The oxide layer is etched to reduce the amount of oxide formed on the non-trenched regions. The cost of this process increases because of the extra lithographic steps required. Furthermore, this approach cannot be scaled down due to compensation and registration issues.

Another approach is to add a "dummy fill" pattern to the mask used to define the trench in the photoresist. This dummy fill pattern minimizes variations in pattern density throughout the substrate 100. However, designing dummy fill patterns for various integrated circuits adds significantly to the complexity and cost of this mask.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method by which planarized features can be produced without the disadvantages of CMP.

[0008]

SUMMARY OF THE INVENTION The present invention is a method of fabricating an integrated circuit including a shallow trench isolation (STI) region. The method of the present invention includes providing a material layer having a trench and a substrate. An insulating layer is formed over the material layer and in the trench. A part of the insulating layer is removed to expose the trench insulating layer. Thereafter, the insulating layer formed on the material layer is removed using a lift-off process to complete a shallow trench region. As a result, planarized shallow trench isolation regions can be formed without using chemical mechanical polishing (CMP). Therefore, the method of the present invention can avoid the problems associated with CMP.

[0009]

DETAILED DESCRIPTION OF THE INVENTION As shown in FIG. 1A, in the method of the present invention, in step 1, a substrate including a material layer and a trench is prepared. In step 2, an insulating layer is formed over the material layer and in the trench. Step 3 removes a portion of the insulating layer to expose the trench insulating layer. Thereafter, the insulating layer formed on the material layer in Step 4 is removed using a lift-off process to complete a shallow trench insulating region. As a result, the planarized shallow trench insulation is
It can be formed without using P). Therefore, the method of the present invention
Avoid problems related to P.

FIG. 1B is a flowchart illustrating another process for fabricating a shallow trench isolation (STI) region in accordance with the method of the present invention. The process of FIG. 1B will now be described with reference to FIGS.

In step 10, a material layer 110 is formed on substrate 100. This substrate 100 is silicon,
It is made of GaAs, SiGe or a known semiconductor material. A pad oxide layer 105 is formed between the material layer 110 and the substrate 100. The pad oxide layer 105 is formed by thermal growth,
For example, it is made of SiO2. The thickness X1 of the pad oxide layer 105 ranges from 100 ° to 200 °, for example, 150 °.

[0012] The material layer 110 is made of a material selected to be etched faster than the subsequently formed insulating layer 130 when exposed to a common etchant. For example, material layer 110 is resistant to etching by a first etchant, while insulating layer 130 is less resistant to the first etchant than material layer 110. The material layer 110 etches faster than the insulating layer 130 when exposed to the first etchant. Furthermore, the material layer 110 is also selected to have a function as a hard mask used in forming the trench 115. This etching process is, for example, a wet chemical etching process. Thickness X of material layer 110
2 is, for example, about 1700 ° between 1500 ° and 2000 °.

In one embodiment of the present invention, material layer 110
Is made of SiN, and the insulating layer 130 is made of high-density plasma (high
density plasma (HDP) is made of oxide, and the etchant contains hot phosphoric acid. SiN and HDP oxide are formed using a known technique. Alternatively, the material layer 110 may be made of polysilicon and the etchant may be NH ₄ OH.

In step 20, a patterned patterned mask layer 120 is formed over the material layer 110. For example, patterned mask layer 120 is a patterned photoresist formed using conventional lithographic techniques. In step 30, material layer 110 and substrate 100 are etched using conventional etching techniques to form trenches 115. Pad oxide layer 10
5 is also etched if present. In step 40, the patterned patterned mask layer 120 is removed, and the substrate 100 is cleaned using a known process. Thereafter, in step 50, an insulating layer 130 is formed over the material layer 110 and in the trench 115. The material of the insulating layer 130 and the deposition process are selected so that a thin region 135 is formed. Furthermore, the deposition process is selected such that trench 115 is filled with the deposited material.

The process shown is a high density plasma (HDP) oxide deposition in a gap-filling mode. U.S. Patent No. 5,872,058 discloses an oxide deposition process using a gap filling process. The thickness X3 of the insulating layer 130 is about 4500 ° between 4000 ° and 5000 °.

In step 60, the insulating layer 130 is etched to expose a portion of the material layer 110. Step 60 may be a single etch or multiple etches. For example, insulating layer 130 is blanket etched using an anisotropic etch that selectively etches non-planar regions. After that, the insulating layer 130
Is etched using a diluted (100: 1) HF etchant. Thin area 1 by this two-step process
35 is removed to expose the region 125 of the material layer 110. Alternatively, region 125 may be exposed using only a blanket isotropic etch or HF etch. A thickness of 200 to 300 mm of insulating layer 130 is removed during step 60.

In step 70, an etching agent having a high selectivity to the material layer 110 is used for etching. The material layer 110 is made of SiN and is etched using hot phosphoric acid. FIG. 8 shows the insulating region 140 formed by the above process. The step height of the insulating region 140 above the pad oxide is between 200 ° and 1000 ° and the insulating region 1
The total thickness X5 of 40 is between 3500 ° and 4000 °. Pad oxide layer 105 protects active region 103 in substrate 100 during the etching step performed in step 70.

In step 80, the integrated circuit is completed using known processes. For example, the device is substrate 1
The subsequent conductive and dielectric layers formed in the substrate are formed to form a complete integrated circuit. Devices and the interconnections of these devices depend on the integrated circuit to be manufactured.

FIG. 9 is a flowchart of another embodiment of the present invention. This embodiment is the same as the embodiment of FIG. 1B, except that steps 55, 57 and 59 are added and step 60 is changed. The process of FIG.
This will now be described with reference to -11.

In step 55, a mask layer 150 is formed over the insulating layer 130. A mask layer 150 is formed to protect a portion of the insulating layer 130 formed in the trench 115 from subsequent etching. Mask layer 15
0 is, for example, a patterned photoresist. In step 57, the insulating layer 130 is etched to expose the material layer 110, and in step 59, the mask layer 1 is exposed.
50 is removed from the substrate 100. In step 60, the insulating layer 130 is etched to expose the region,
Remove remaining material from 70. Thus, the material layer 110
Large area 160 is exposed and then etched in step 70. The integrated circuit is completed as described above and is shown in FIG.

In another embodiment of the present invention, a dummy fill pattern can be used in the process shown in FIGS. 1A, 1B and 9. In this case, the dummy fill pattern may have trenches 115 in regions where insulating regions 140 are not needed.
Forming As a result, the insulating region 140 is formed over the wafer and the insulating region 14 is formed over the wafer.
The pattern density of 0 becomes more constant.

[Brief description of the drawings]

FIG. 1A is a flowchart for forming a shallow trench insulating region according to a first embodiment of the present invention. B is a flowchart for forming a shallow trench insulating region according to the second embodiment of the present invention.

FIG. 2 is a diagram illustrating a first step of a process of manufacturing an integrated circuit by the process illustrated in FIG. 1B.

FIG. 3 is a view showing a second step of the integrated circuit manufacturing process by the process shown in FIG. 1B.

FIG. 4 is a diagram showing a third step of the integrated circuit manufacturing process by the process shown in FIG. 1B.

FIG. 5 is a view showing a fourth step of the integrated circuit manufacturing process by the process shown in FIG. 1B.

FIG. 6 is a view showing a fifth step of the integrated circuit manufacturing process by the process shown in FIG. 1B.

FIG. 7 is a view showing a sixth step of the integrated circuit manufacturing process by the process shown in FIG. 1B.

FIG. 8 is a view showing a seventh step of the integrated circuit manufacturing process by the process shown in FIG. 1B.

FIG. 9 is a flowchart for forming a shallow trench insulating region according to a third embodiment of the present invention.

FIG. 10 is a view showing a fifth step of the integrated circuit manufacturing process by the process shown in FIG. 9;

FIG. 11 is a view showing a sixth step of the integrated circuit manufacturing process by the process shown in FIG. 9;

FIG. 12 is a view illustrating a seventh step of the integrated circuit manufacturing process by the process illustrated in FIG. 9;

[Explanation of symbols]

1. A substrate having a material layer and a trench is prepared. 2 An insulating layer is formed on the material layer and in the trench. 3 Exposing a part of the material layer below the insulating layer. 4 Remove the insulating layer using a lift-off process to form a shallow trench isolation region. 10 Form a material layer on the substrate. 20. Form a patterned mask over the material layer. 30 Pattern material layer and substrate to form trench. 40. Remove the photoresist mask layer and clean the material layer and trench. An insulating layer is formed on the material layer and in the trench. 55. A mask layer is formed on the insulating layer. The insulating layer is etched to expose a part of the 57 material layer. 59 The mask layer is removed. 60. Etch the insulating layer to expose the material layer. 70. Remove material layer to lift off remaining portion of insulating layer. 80 Complete the manufacture of the integrated circuit. REFERENCE SIGNS LIST 100 substrate 103 active region 105 pad oxide layer 110 material layer 115 trench 120 patterned mask layer 125 region 130 insulating layer 135 thin region 140 insulating region 150 mask layer 160 region 170 region

 ──────────────────────────────────────────────────続 き Continuation of the front page (71) Applicant 596077259 600 Mountain Avenue, Murray Hill, New Jersey 07974-0636 U.S.A. S. A. (72) Inventor Majob Ali Ali Abdelgadir Fitzwilliam Way 507, Orlando, 32828 Florida, United States of America 507 (72) Inventor Gerald W. Gibson Jr. United States, 32835 Florida, Orlando, Willow Shade Court 4418 (72) Inventor Stephen Gregory Gunter United States, 32809 Florida, Orlando, Stafford Drive 1716 (72) Inventor Alvaro Mauri United States, 32819 Florida, Ohio Land, Land Groove Court 8034

Claims (18)

[Claims] (A) a material layer (11) on a substrate (100);
0), the substrate (100) and the material layer (110) have a trench (115), and (b) an insulating layer (100) on the material layer (110) and in the trench (115). (C) removing at least a portion of the insulating layer (130) by etching the material layer (110) to form a shallow trench insulating region. A method of manufacturing an integrated circuit having a shallow trench insulating region. 2. The method of claim 1 wherein said step (c) includes etching said material layer (110) using a first etchant, said first etchant being faster than said insulating layer (130). The method of claim 1, wherein (110) is etched. 3. The method of claim 2, further comprising the step of: (d) etching the insulating layer (130) to expose a portion of the material layer (110). 4. The method according to claim 3, wherein said step (d) is performed before step (c). 5. The method of claim 3, further comprising the step of: (e) forming a patterned layer (120) on said insulating layer (130). 6. The method of claim 5, wherein step (e) is performed before step (d). 7. The step (d) includes the step of:
4. The method according to claim 3, wherein the insulating layer is etched without using 0). 8. The method of claim 1 wherein said step (c) leaves a portion of said insulating layer (130) formed in said trench (115) after etching. 9. An integrated circuit manufactured by the method of claim 1. 10. A step of: (a) forming a hard mask on the substrate (100); (b) forming a trench (115) on the hard mask and in the substrate (100); Forming an insulating layer (130) in the trench (115) and on at least a portion of the hard mask; and (d) a portion of the insulating layer (130) formed on a portion of the hard mask. Lifting off a semiconductor device, and a method of manufacturing an integrated circuit. 11. The method of claim 10, wherein said step (d) includes etching a hard mask. 12. The method according to claim 11, wherein said hard mask is etched by wet etching. 13. The method of claim 10, further comprising: forming a shallow trench isolation region. 14. An integrated circuit manufactured by the method of claim 10. 15. The method of claim 10, wherein said hard mask is made of SiN and said insulating layer (130) is made of an oxide. 16. A substrate (100) without using chemical mechanical polishing.
Forming a shallow trench insulating region in the semiconductor device. 17. An integrated circuit manufactured by the method according to claim 16. 18. A substrate (100) and said substrate (100).
A hard mask formed over the hard mask and having a trench (115), the hard mask having a region near the trench (115);
A partially formed integrated circuit having an insulating layer (130) formed in said trench (115).
A partially formed integrated circuit, wherein a region (125) of the hard mask adjacent to said hard disk is not covered by said insulating layer (130).