JP2001051965A - Testing method for information processor and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache coherency test in the state of enabling each of CPUs to access the same block and not destroying data from the other CPU in the case of a random instruction test with a multi-CPU as an object in an information processor. SOLUTION: Plural CPUs (CPU-0, CPU-1...) are connected by a bus and the cache coherency test is executed with a device equipped with a cache memory 9 in each of CPUs as an object. In the case of such a test, the value of a vase register indicating the operand address of an access instruction generated from a random instruction stream is set to a value shifted for a fixed value for each of CPUs and the value of an index register indicating the index part of the operand address and a displacement value inside the operand address are previously specified. Thus, overlapped access from each of CPUs can be avoided when the same access space is allocated to all the CPUs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to verify a cache coherency function by a random instruction test for a multi-CPU system in which a plurality of CPUs are connected by a bus and each CPU has a cache memory. The present invention relates to a test method and a recording medium for an information processing device.

[0002]

2. Description of the Related Art A conventional example will be described below.

§1: Description of cache coherency In recent years, as one means of increasing the speed of a computer, a high-speed memory called a cache memory of several kilobytes to several megabytes is called a cache memory separately from a main memory (main memory). To speed up the process.
In this case, data read from the main memory into the cache can always be processed at high speed while operating on the cache memory.

In this control, when one CPU is used, the consistency between the cache memory inside the own CPU and the main memory (Cach
e Coherency: It is only necessary to consider cache coherency), but if multiple CPUs are installed, the CP
It is necessary to consider the cache memories of the U and U, and the hardware control becomes complicated. This control is briefly described below with reference to the drawings.

[0005] § 2: Explanation of system configuration and processing outline
FIG. 15 is a system configuration diagram of a conventional example. This system is an example of a multi-CPU system, and includes a plurality of CPUs.
(CPU-0, CPU-1 ...) and main memory 1
(One memory shared by all CPUs) and the system controller 2 are connected by a bus. And each CP
Each U has a cache memory (hereinafter, also simply referred to as “cache”).

In this case, a primary cache (hereinafter referred to as "L1 $") is provided inside each CPU, and a secondary cache (hereinafter referred to as "L2 $") is provided outside the chip of each CPU. L1 $ is a small-capacity cache,
L2 # is a cache with a larger capacity than L1 #.

A system controller 2 is connected to the bus, and another bus connected to the system controller 2 is connected to a ROM 6 via an input / output control unit (hereinafter referred to as an “I / O control unit”) 5. Etc. are connected. The system controller 2 performs various controls including management of a cache memory in the system, and a cache control unit 3 having a cache information table 4 is provided in the system controller 2.

[0008] The cache control unit 3 includes a CPU
Has a function of storing the information of L1 $ and L2 $ held in the cache information table 4 and performing cache control of these L1 $ and L2 $. For example, when the CPU fetches data from the main storage memory 1, the CPU first looks at the internal L1 #. If there is no data corresponding to L1 $, the CPU goes to another CPU to retrieve the corresponding data. At this time, the CPU goes to the system controller 2 to obtain cache information, and based on the information, the other CPU Read the data.

Therefore, the system controller 2 determines each C
The information of the L1 $ and L2 $ of the PU is stored in the cache information table 4 and managed while being constantly updated.
The cache control is performed on U based on this information.

In the above system, the processing outline when each CPU executes a load instruction (Load) and a store instruction (Store) is as follows. For example, the load instruction is a process of taking the data of the main memory 1 into a register in the CPU. In this case, if it is the first load instruction, the data is stored in the main memory 1 → L2Ｌ → L1 ＄ → C
The data is transferred in the order of the registers inside the PU.

The store instruction is a process for writing data stored in a register in the CPU into the main memory 1. The process when this instruction is executed is as follows. First, it is determined whether or not data corresponding to the data to be stored stored in the register in the CPU exists in L1 $. If the data exists, the data corresponding to L1 $ is stored in the new data (the storage target). And the process is terminated. At this time, since the data in the main memory 1 is not rewritten, the data remains old.

However, if there is no data corresponding to the data to be stored in L1 #, it is determined whether or not data corresponding to the data to be stored is in L2 #. The corresponding data is rewritten with the new data (the data to be stored), and the process ends. At this time, since the data in the main memory 1 is not rewritten, the data remains old.

Further, if there is no data corresponding to the data to be stored in either L1 # or L2 #, the corresponding data is read from the main memory 1 and written into L2 #, and the corresponding data in L2 # is stored. Is rewritten with the new data (the data to be stored), and the process ends. At this time,
Since the data in the main memory 1 is not rewritten, the data remains old.

The data to be written to the main storage memory 1 is the data that has been evicted from L2 #. The above processes are constantly monitored by the system controller 2, and the information of the cache memory is stored in the cache information table 4 by the cache control unit 3. Also,
Data in L1 $ is always in L2 $. Therefore,
When each CPU executes an access command, processing is performed based on information in the cache information table 4 from the system controller 2.

Incidentally, regarding the control of the cache,
The theory of “MOESI” is described in many documents and is well known (well-known theory), and thus detailed description is omitted. One of the references related to "MOESI"
For example, the following references are known, for example:

Reference: "ultraSPARC ^™ -IUser's Manu"
al ", Revision 1.0, Sept 18, 1995," SPARC Technology
Business '' A Sun Microsystems, Inc. Business 2550 G
arcia Avenue, Mountain View, CA 94043 USA, Part No;
STP1030-UG. (See pages 91-97). §3: Description of processing in the system In the above system, for example, when the CPU-0 loads the contents of the address 100 in the main memory 1, the C-0
Data of one block (for example, 64 bytes) from address 100 of the main storage memory 1 is read into the PU-0 cache (L1 #). Next, 100 of the main memory 1
When new data is stored at the address (Store), CPU-
The cache 0 (L1 # or L2 #) is replaced with new data, but the main memory 1 holds old data.

In this state, when the CPU-1 loads the contents of the address 100 in the main memory 1, the data at that time is not read from the main memory 1 but is read from the cache (L1 # or L2 #) of the CPU-0. Is read. This is because the latest data at address 100 is held in the cache (L1 # or L2 #) of the CPU-0. A method for verifying cache consistency in a system having such a mechanism will be described below.

§4: Description of a method for verifying the coherency of caches--see FIG. 16 FIG. 16 shows a conventional random instruction test example. Generally, when a plurality of certain tasks are operated simultaneously, areas for rewriting data such as a stack area and a data access area are provided for the number of tasks, and each task is realized by using a space allocated to the task. Let me. This method is applicable to a case where one task is shared and operated by a plurality of CPUs. In general, a multi-CPU random instruction test often uses this method.

In the prior art, a random instruction test operating under one CPU (including a memory access instruction) is simply operated simultaneously under a plurality of CPUs. It is. In other words, if a random instruction is executed from a plurality of CPUs at the same time, an access instruction included in the random instruction sequence is also randomly transmitted from the plurality of CPUs, and as a result, a test between the cache and the main memory can be performed. .

For example, in the example shown in FIG. 16, the random test sequence is different and the memory access area is different from the first test example (see FIG. 16A). A different second test example (FIG. 16)
(See FIG. B). In this case, the test example 1
In the test, the CPU-0 and the CPU-1 perform tests by using different memory areas and executing different instruction sequences. In Test Example 2, CPU-0 and CPU-1 are
The test is performed by using the same memory area and executing different instruction sequences.

The problem here is that since the access area from each CPU exists in another space, the memory access operation of one CPU does not affect the cache of another CPU. That is, at present, the cache coherency test cannot be performed across a plurality of CPUs. To implement this test, it is necessary to access the same cache line, but such a technique is not provided at present.

[0022]

The above-mentioned prior art has the following problems.

As described above, to enable access to the same cache line (for example, 64 bytes), each CPU needs to access the same block address (64 bytes from the 64 byte boundary). . Here, it may be considered that the space (memory area) accessed by each CPU should be the same.
Since the PU operates asynchronously, if each CPU uses the same address, different data may be read when reading the contents written to the memory depending on the timing. This is because there is a possibility that another CPU may write another content to the address immediately before reading the content of the address.

The present invention solves such a conventional problem, and in a random instruction test for multiple CPUs, each CPU can access the same block and another CPU
It is an object of the present invention to realize a cache coherency test using a method that does not destroy data from the cache.

[0025]

FIG. 1 is an explanatory view of the principle of the present invention. 1 is a main memory, 2 is a system controller, 3 is a cache control unit, 4 is a cache control information table, and 6 is a program. ROM 9 indicates a cache memory. The present invention is configured as follows to achieve the above object.

(1): Multiple CPUs (CPU-0, CPU
-1,...) Connected by a bus, and each CPU is provided with a cache memory 9 for an information processing device having a multi-CPU configuration. In the test method of the information processing apparatus for generating a random instruction sequence and performing a cache coherency test by adding a statement value and generating an operand address of an access instruction, the method of the access instruction generated by the random instruction sequence The value of the base register indicating the operand address is
The same access space is set for all CPUs by setting the value of the index register indicating the index part of the operand address and the displacement value in the operand address in advance by setting the value shifted by a constant value every time. Duplicate access from each CPU at the time of assignment is avoided.

(2): A plurality of CPUs are connected by a bus, and each C
A test method for an information processing apparatus for performing a cache coherency test by generating a random instruction sequence in the CPU for an information processing apparatus having a multi-CPU configuration including a cache memory in a PU, the method having an identical logical space, A plurality of different contexts that can be switched by are prepared, each of the contexts has correspondence information between a logical address and a physical address of a real memory, and in the process of executing the random instruction sequence, the context is switched by a specific instruction. At this time, even if the same logical address is accessed, the cache replacement is performed by pointing to a different physical address of the real memory, so that the number of cache replacements is generated more.

(3): A plurality of CPUs are connected by a bus, and each C
In a test method for an information processing device that generates a random instruction sequence in the CPU and performs a cache coherency test, the information processing device is intended for an information processing device having a multi-CPU configuration including a cache memory 9 in a PU. A specific instruction for selecting a test target cache address is provided in the random instruction sequence, and by executing this specific instruction, the same test target cache address is selected for each CPU and assigned to each CPU. A value obtained by adding the shift byte is obtained, and this value is used for each CPU.
From the viewpoint of the same cache address and access is not duplicated.

(4): A plurality of CPUs are connected by a bus, and each C
In a test method for an information processing apparatus that performs a cache coherency test by generating a random instruction sequence in the CPU for an information processing device having a multi-CPU configuration including a cache memory 9 in a PU, A process of copying to another space, a process of creating an address translation table having the same logical address and a different physical address for both random instruction spaces, and defining different context values in the table, A process of setting a value in a context and starting a test from a certain logical address, and upon a certain interrupt, selecting a logical address of an instruction from the address conversion table, and adding an address in a random instruction to the instruction counter for this value. By setting, and by switching the context value triggered by a certain interrupt The instruction counter of the logical address remains unchanged, and only the physical address can be changed. By the above-described processing, the random instruction sequence is sequentially executed from the beginning, and only the execution space is changed. Enabled cache coherency test.

(5): A plurality of CPUs are connected by a bus, and each C
A multi-CPU information processing device having a cache memory in a PU, and in the CPU, adds an index register value or a displacement value to a base register value to generate an operand address of an access instruction. By doing so, an information processing device that generates a random instruction sequence and performs a cache coherency test stores a value of a base register indicating an operand address of an access instruction generated by the random instruction sequence in each CPU.
A procedure for setting a value shifted by a constant value every time, a procedure for preliminarily defining a displacement value in the operand address and a value of an index register indicating an index portion of the operand address. A computer-readable recording medium on which a program is recorded.

(Operation) The operation of the present invention based on the above configuration will be described with reference to FIG.

(A): In the above (1), when testing the information processing apparatus, the value of the base register indicating the operand address of the access instruction generated by the random instruction sequence is shifted by a constant value for each CPU. The value of the index register indicating the index portion of the operand address and the displacement value in the operand address are defined in advance.

In this way, when the same instruction is executed from all CPUs, the access address of the access instruction can point to an address range that is always determined for each CPU. That is, duplicate access from each CPU when the same access space is allocated to all CPUs can be avoided.

Therefore, in a random instruction test for multiple CPUs, a cache coherency test can be realized in which each CPU can access the same block and data is not destroyed by another CPU.

(B): In the above (2), when testing the information processing apparatus, a plurality of different contexts which have the same logical space and can be switched by an instruction are prepared. And
Each context has correspondence information between the logical address and the physical address of the real memory, and in the process of executing a random instruction sequence, when the context is switched by a specific instruction and the same logical address is accessed, even if the same logical address is accessed. Cache replacement (for example, flushing of cache data from L1 # to L2 #) is performed by pointing to a different physical address. This makes it possible to generate a larger number of cache replacements.

(C): In the above (3), when the information processing apparatus is tested, a specific instruction (for example, Select) for selecting a test target cache address in a random instruction sequence executed by each CPU. Line ()) is provided, and by executing this specific instruction, each CPU selects the same cache address to be tested, obtains a value obtained by adding a shift byte allocated to each CPU to this address, and obtains this value. As a result, when viewed from each CPU, the same cache address and the access are not duplicated.

That is, it is possible to derive from the plurality of CPUs memory addresses whose accesses do not overlap within the same memory block to be tested. In this way, it is possible to implement a method of incorporating the intended cache coherency logic into the random instruction sequence, and it is possible to reduce the realization time of all combinations at the time of testing.

(D): In the above (4), when the test of the information processing apparatus is performed, a process of copying the generated random instruction sequence into another space, and a process in which a logical address is assigned to both random instruction spaces. A process of creating an address translation table having the same physical address but different physical addresses and defining different context values in the table; a process of setting a value in the context as an initial value and starting a test from a certain logical address; A process of selecting a logical address of an instruction from the address conversion table upon the occurrence of an interrupt and setting a random instruction address in the instruction counter to this value, and switching a value of a context upon the trigger of an interrupt. A process for changing only the physical address without changing the instruction counter of the address is performed.

By the above processing, the random instruction sequence is sequentially executed from the beginning, and only the execution space is changed, thereby enabling a cache coherency test of the instruction cache.

(E): In the above (5), by reading and executing the program on the recording medium, the value of the base register indicating the operand address of the access instruction generated by the random instruction sequence is set to a fixed value for each CPU. The offset value is set in advance, and the value of an index register indicating the index portion of the operand address and the displacement value in the operand address are defined in advance.

In this way, when the same instruction is executed from all CPUs, the access address of the access instruction can point to an address range that is always determined for each CPU. That is, duplicate access from each CPU when the same access space is allocated to all CPUs can be avoided.

Therefore, in the random instruction test for the multiple CPUs, the cache coherency test can be realized so that each CPU can access the same block and the data is not destroyed by another CPU.

[0043]

Embodiments of the present invention will be described below in detail with reference to the drawings.

§1: Description of the System—See FIG. 2 FIG. 2 is a system configuration diagram. This system is an example of a multi-CPU system (information processing device having a multi-CPU configuration), and a plurality (n) of CPUs (CPU-
0, CPU-1... CPU-n) and main memory 1
(One memory shared by all CPUs), a system controller 2 and the like. And each CPU:
Each cache memory (hereinafter simply "cache")
Also noted).

In this case, L1 $ (primary cache) is provided inside each CPU (inside the CPU chip),
L2 # (secondary cache) is provided outside (a chip different from the CPU chip), and these are connected by a bus. In this example, the primary cache and the secondary cache are provided. However, in general, more caches (tertiary cache, quaternary cache, etc., generally up to the nth cache) may be provided. it can.

L1 $ is a small-capacity cache,
For example, a cache memory of 32 KB (kilobytes) (Way-0, Way-1, Way-2, W
ay-3) (four cache areas). Also, the L2 ＄ is 1 MB or 2 MB.
This is a large-capacity (larger than L1 $) cache having a capacity of MB or 4 MB. In this case, in the drawing, Way-0, Way-1, Way-2, W
The left end of ay-3 is address = 0, and the right end is address =
32K. The hatched portion in FIG. 2 is a cache line having a width of 64 bytes.

The bus is connected to a system controller 2, and another bus connected to the system controller 2 is connected to a ROM 6 via an input / output control unit (hereinafter referred to as “I / O control unit”) 5. Etc. are connected. The system controller 2 performs various controls including cache management in the system. The system controller 2 includes a cache control unit 3 having a cache information table 4.

The cache control unit 3 stores information (cache information) of L1 $ and L2 $ of each CPU in the cache information table 4, and performs cache management (or cache control) of these L1 $ and L2 $. Has functions. For example, when the CPU takes in (loads) the data in the main storage memory 1, first, it looks at the internal L1 #.

If there is no data corresponding to L1 {, L2}, the CPU goes to another CPU to retrieve the corresponding data. At this time, the CPU goes to the system controller 2 to obtain the cache information, and Based on other C
Read cache data from PU.

Therefore, the system controller 2 sets each C
The information of the PU L2 # is stored in the cache information table 4 and is managed while constantly updating the information.
The cache control is performed on the PU based on this information. The ROM 6 stores a cache test program described below.

When the cache coherency test described below is performed, the program stored in the ROM 6 is transferred to the CPU (for example, CPU-
0) is loaded into the main memory 1, and the CPU fetches and executes the program in the main memory 1,
Perform tests in this system.

In the above system, the processing outline when each CPU executes a load instruction (Load) and a store instruction (Store) is as follows. For example, the load instruction is a process of taking the data of the main storage memory 1 into a register in the CPU.
If the instruction is a load instruction (with 2 ＄ all empty), the data is transferred in the order of main memory 1 → L2 ＄ → L1 ＄ → register in the CPU.

In this case, for example, 10
If the data at address 0 is to be loaded, 64 bytes of data are read from address 100 of the main memory 1,
This data is stored in L2 #, and then L2 #
The data is transferred to 1 # and stored in Way-1 of L1 #.

When data is sequentially loaded by repeating the operation as described above, L1 # is sequentially set to Way-3 →
64 bytes of data are stored in each of Way-2 → Way-1 → Way-0, and the data read from the main storage memory 1 is sequentially stored in the cache line shown in FIG.

The store instruction is a process for writing data stored in a register in the CPU into the main memory 1. The process when this instruction is executed is as follows. First, it is determined whether or not data corresponding to the data to be stored stored in the register in the CPU exists in L1 $. If the data exists, the data corresponding to L1 $ is stored in the new data (the storage target). And the process is terminated. At this time, since the data in the main memory 1 is not rewritten, the data remains old.

However, if there is no data corresponding to the data to be stored in L1 $, it is determined whether or not data corresponding to the data to be stored is in L2 $. The corresponding data is rewritten with the new data (the data to be stored), and the process ends. At this time, since the data in the main memory 1 is not rewritten, the data remains old.

Further, if there is no data corresponding to the data to be stored in either L1 # or L2 #, the corresponding data is read from the main memory 1 and written into L2 #, and the corresponding data in L2 # is stored. Is rewritten with the new data (the data to be stored), and the process ends. At this time,
Since the data in the main memory 1 is not rewritten, the data remains old. Hereinafter, a specific example of the cache coherency test will be described in detail.

§2: Description of Example 1—See FIGS. 3 and 4 FIG. 3 is an explanatory diagram (part 1) of Example 1; FIG. A is a definition of an operand address generation base register; FIG. Figure C shows the definition of the index register for address generation, and Figure C shows the definition of the displacement value for operand address generation. FIG. 4 is an explanatory diagram (part 2) of Example 1.

Example 1 is a test method using a technique for preventing duplicate access from each CPU when the same access space is allocated to all CPUs. Note that each CPU is provided with various registers and the like.
The index register provided in the PU is referred to as% G1, and the base register is referred to as% G2 (% G1 and% G2 are both register numbers).

The generation of the operand address of the access instruction to the main storage memory 1 is performed by: a base register (% G
2) address + index register (% G1) address (% G2 +% G1), or: base register (% G2) address + displacement value (% G1)
2 + displacement value). Therefore,% G
By defining the value of 1, the value of% G2, and the displacement value, it is possible to make the space (area of the main memory 1) accessed by each CPU the same and to avoid overlapping access of the area. Therefore, the definition of each register is as follows.

(1): Definition of a base register for generating an operand address The value of the base register (% G2) indicating the operand address of an access instruction generated by a random instruction sequence is stored in each C
Each PU is defined fixedly, and each CPU has its register (% G
Set a value shifted by 16 bytes to the value of 2). The value of 16 bytes defined here is a value when a maximum of 4 CPUs are operated when the cache access unit is 64 bytes. That is, this value changes depending on the number of CPUs to be tested and the cache access unit.

In this example, the values of the base registers (% G2) of the CPU-0 to CPU-3 are set as shown in FIG. 3A (x is a symbol meaning hexadecimal hexadecimal). ). For example, the base register (% G
The address of 2) is set to n = “0x00100000”, and a value shifted by 16 bytes from this value is set in the base register of another CPU.

That is, the address of the base register (% G2) in the CPU-1 = n + 16 = “0x001000”
10 ”and set the base register (% G
Address of 2) = n + 32 = "0x00100020"
And the address of the base register (% G2) in the CPU-3 = n + 48 = “0x00100030”.

(2): Definition of an index register for generating an operand address The value of an index register (% G1) indicating an index portion of an operand address of an access instruction generated by a random instruction sequence is fixedly defined, and its contents are cached. Is set at the access boundary (64-byte boundary).
In this example, as shown in FIG. 3B, “0bm... Mmm0000” is stored in the index register (% G1).
00 ”is set. In this case, for example, 0x3c0 (m
Is in bits).

(3): Definition of displacement value (direct value) for generating operand address The bits 4 and 5 of the displacement value in the operand address of the access instruction generated by the random instruction sequence are fixed to 0. In this example, the displacement value is set to “0bnnnnnnnn00mmmm”. In this case, for example, the displacement value = 0x2c8
(The units of m and n are bits). The value “0b”
In the “nnnnnnnn00mmmm”, m at the right end in the figure is bit 0, and m on the left side is bit 1. Therefore, bit 4 is the fifth bit 0 from the right end.

The bits 4 and 5 correspond to the conditions described in the definition of the operand address generation base register in (1) above (the defined value of 16 bytes is a maximum of 4 CPUs when the cache access unit is 64 bytes). Is operated. That is, this value changes depending on the number of CPUs to be tested and the cache access unit.)

The value of m in this case is defined by the type of the generated instruction. For example, when a 1-byte storage instruction is generated, a value of “mmmm” (m is an arbitrary value), when a 2-byte storage instruction is generated, a value of “mmm0”
When a 4-byte storage instruction is generated, the value of “mm00” is set. When an 8-byte storage instruction is generated, “mm0” is set.
0 ”.

That is, it is necessary to define a value that does not exceed 16 boundaries when data is accessed from that address. This is because if the access is made beyond the 16 boundaries, the access reaches the area accessed by the next CPU. The operand address of the access instruction generated under the above conditions can always point to an address determined for each CPU on a 64-byte boundary. For example, when the following instruction is generated and the values of the above example are applied, the result is as shown in FIG. 3C.

When the address of the base register (% G2) + the address of the index register (% G1) is applied, the following is obtained. For example, in the example of 8-byte access, the store instruction is STX (X: for example, 8 bytes), and the I register number 5 provided in the CPU is% I
5. Assuming that the access address (operand address) of the access instruction is OP, STX,% I5, [% G2 +%
G1] is as follows. Note that the above [% G2 +% G
1] indicates an address of the main memory 1.

That is, the CPU-0 determines that% G2 = 0x0
0100000 +% G1 = 0x3c0, OP = 0x00
1003c0, CPU-1 is% G2 = 0x00100
010 +% G1 = 0x3c0, OP = 0x001003
d0, CPU-2 is% G2 = 0x00100020 +
% G1 = 0x3c0, OP = 0x001003e0, C
PU-3 is% G2 = 0x00100030 +% G1 =
0x3c0 and OP = 0x001003f0.

When the address of the base register (% G2) + the address of the displacement value is applied,
It looks like this: For example, in the example of 8-byte access,
Assuming that the store instruction is STX (X: for example, 8 bytes), the I register number 5 is% I5, and the operand address is OP, STX,% I5, [% G2 + 0x2c8] are as follows. Note that% I5 is a register for storing an operand address.

That is, the CPU-0 determines that% G2 = 0x0
0100000 + Imm13 = 0x2c8, OP = 0x
001002c8, CPU-1 calculates% G2 = 0x001
00010 + Imm13 = 0x2c8, OP = 0x00
1002d8, CPU-2 is% G2 = 0x00100
020 + Imm13 = 0x2c8, OP = 0x0010
02e8, CPU-3 uses% G2 = 0x0010003
0 + Imm13 = 0x2c8, OP = 0x001002
f8. [% G2 + 0x2c8] indicates the address of the main memory 1.

As described above, when the same instruction is executed from all CPUs, the access address of the access instruction represented by the OP indicates a range (16 bytes in this case) which is always determined for each CPU. be able to. Therefore,
An access command issued randomly by each CPU (for example,
When the same access space (memory area) is allocated to all CPUs, a duplicate access from each CPU can be prevented. This state is shown in FIG.

In FIG. 4, each of CPU-0 to CPU-3 is assigned to an area (address range) separated by 16 bytes, so that duplication in accessing can be prevented. That is, when the same access space (memory area) is allocated to all CPUs, it is possible to reliably prevent duplicate accesses from each CPU.

In this case, the block unit of data when accessing the main storage memory 1 is, for example, 64 bytes, but in general, (block size) / (number of CPUs) =
The address range assigned to each CPU (16 in FIG. 4)
Bytes).

§3: Description of Example 2—See FIG. 5 FIG. 5 is an explanatory diagram of Example 2, showing the relationship between access register numbers and memory addresses. Example 2 is an example in which a cache coherency operation environment is generated in a random instruction sequence by realizing a cache coherency operation environment only by switching windows.

For example, RISC such as "Ultra-sparc"
(Reduced Instruction Set Computer) type computers (reduced instruction set computers) include general-purpose registers (% G0 to% G7), in-registers (% I0 to% I7) for each window, and local registers (% L0 to% L0).
L7) and an out register (% O0 to% O7),
As shown in FIG. 5, the window registers have the in (% I) and out (% O) registers of adjacent windows overlapping (% I and% O have the same contents).

In this case, the local registers (% L0 to% L
L7) has different contents when the windows (CW0 to CW4) are switched, but the contents of the out-register (% O) and the in-register (% I) of the adjacent windows are the same. When these registers point to a certain window, only the registers of the window at that time and the general-purpose registers (% G) can be used.

For this reason, it is almost always the case that a general-purpose register (% G) which can be referred to from any window is used for access. In this case, at most only seven addresses can be specified. In the present invention, the local registers (% L0 to% L7) of each window focus on the access registers.
Assuming that there are five windows, 40 addresses can be specified (extraordinarily many register values can be obtained simply by switching windows).

By setting different addresses in the logical space in advance in these forty registers, more operating environments for cache coherency can be created only by switching the current window with an instruction. In this case, the current windows CW0 to CW4 (CW: Current Wind
ow) is a window that can be switched by a window switching command on the program. Then, by switching the register of% L by CW, it is used as a base register. That is, by switching% L between CW0 and CW4, the% L is used as the base register.

The% G is used as the index register. In this case, the values of -64, 0, and +64 are stored in the% G as index pointers, and if these are used, the operating environment of cache coherency can be easily realized only by switching the CW. Becomes possible.

As described above, different addresses in the logical space are set in advance in the local registers (% L) provided for each window, and the local registers are switched by the windows to generate the random instruction sequence. By using the general-purpose register (% G) as an index register indicating an index portion of the operand address by using the base register indicating the operand address of the access instruction to be executed, the cache coherency operation can be performed only by switching the window. Environment can be realized.

In this case, the generation of the operand address of the access instruction to the main storage memory 1 is performed as follows:
It is determined by the address of the base register (% L) + the address of the index register (% G) (% L +% G).

§4: Description of Example 3—See FIG. 6 FIG. 6 is an explanatory diagram of Example 3, and shows the definition (CW0, 1, 2, 3, 4) of the L1 replacement register. FIG. 6 is an enlarged explanatory view of the local register% L shown in FIG. Example 3 is an example in which the number of times of cache replacement (replacement of cache data) is increased to generate more operating environments of cache coherency in a random instruction sequence.

Even if the number of address registers to be accessed is defined to be large, if the address to be actually accessed has a too large range such as access register + (−) 0 × 10000, the corresponding line (cache line) of the cache is accessed. The probability of performing a cache replacement (cache data eviction) is reduced as a result.

The cache replacement in this case is performed by replacing the cache data, that is, from L1 # to L2 #.
Eviction of data. For example, when new data is written to L1 #, if there is no free space in the area of L1 #, the old data in L1 # is evicted and written to L2 #. Write data.

Therefore, the conditions for determining the address are as follows:
The index register (% L) and the displacement value (immediate value) are fixed at three places of minus 64, 0 and plus 64 (−64, 0, +64) so that other values are not generated. I do. As a result, the access area is limited to within plus or minus 64 bytes of the address indicated by the local register (% L).

In this case,% L0 to% L7 (register% L in FIG. 5 is enlarged and shown in FIG. 6) used as base registers are respectively Way-0 to Wa of L1 #.
According to 32KB which is each width of y-3, 32K
B is provided separately. For example, the interval between% L0 and% L1 is 32 KB, the interval between% L1 and% L2 is 32 KB, and the interval between% L2 and% L3 is 32 KB.

The general-purpose register% G used as an index register for each% L is set at intervals of -64 bytes, 0 bytes, and +64 bytes from the boundary of 32 KB. Therefore, an index value is put in the general-purpose register% G used as an index register. In this case, the index value = -64 is added to% G1.
, And the index value = +0 in% G2, and% G3
Is set to +64.

The displacement value (immediate value) also uses a value of -64 bytes, 0 bytes, and +64 bytes. In this way, the value of the index register (% G) is added to the value of the base register (% L).
Or displacement value (immediate value)
Is added to generate an operand address of the access instruction, thereby generating an access instruction.

Therefore, if an access instruction is executed four times with a randomly generated instruction sequence in each CPU, the same cache line is stochastically indicated once. The cache line in this case is represented by the Way-in L1 # shown in FIG.
This is a hatched line extending from 0 to Way-3.

§5: Description of Example 4—See FIG. 7 FIG. 7 is an explanatory diagram of Example 4, showing the relationship between the test space and the MMU table. Example 4 is an example of generating more cache coherency operating environments in a random instruction sequence by generating a larger number of cache replacements.

As a method of increasing the number of cache replacements, there is a context switch. Note that in Example 4, the context refers to a group of one continuous logical space (a term of a UNIX machine). MMU is an address translation table.

As shown in FIG. 7, different contexts Ctx have the same logical space (logical addresses = 0 to n).
In this case, N (Ctx = a, Ctx = b, Ctx = c) are prepared (N = 3 in this example). In this case, each context has a logical space of logical addresses 0 to n, and each has a correspondence table between logical addresses and physical addresses. Then, different data is set in the correspondence table between each logical address and each physical address.

For example, in the logical space of Ctx = a, Ctx = b, and Ctx = c shown in FIG. 7, a logical address and a physical address are associated with each other. , As shown by the illustrated arrows,
Even though the logical address is the same, it points to a different physical address (real memory address).

Therefore, a random instruction sequence is executed in the environment (the first context is Ctx = a), and the context is switched at a certain point (for example, from Ctx = a).
By switching to Ctx = b), the logical address is the same before and after the context is changed, but since the context is different, cache replacement is performed even if the same logical address is accessed.

As described above, by combining the environments in which the caches are replaced, it becomes possible to realize a much larger number of cache coherency states by orders of magnitude than the conventional number of occurrences of the cache coherency. Therefore, the cache coherency can be verified in a short period of time, and the quality of hardware can be guaranteed.

§6: Description of Example 5—See FIG. 8 FIG. 8 is an explanatory diagram of Example 5, and FIG.
FIG. B shows a cache address table. Example 5 is an example in which the same cache line to be tested is derived from a plurality of CPUs by incorporating intended cache coherency logic into a random instruction sequence.

In the test methods of Examples 1 to 4, the access instructions are issued at random from all the CPUs, so that the cache in each CPU and the main memory 1
It is possible to realize a combination of all states between,
With this method, it is not clear how much the combination can be realized. Therefore, as a method for shortening the realization time of the combination of all the states, the following example 5 is used.
There is a technique.

The selection of the test target cache address is performed by selecting the select line instruction “Select Line () ".
In this test, a cache address to be tested is selected, and a value obtained by adding a shift byte allocated to each CPU is obtained. In this case, since all CPUs need to point to the same physical address, the following method is used.

A test cache address table is created for each CPU. The logical addresses in this table may differ between CPUs, but the physical addresses must always match.

: Selector called from each CPU
In instruction (function) "Select Line () "is the caller
The lower few bits of the link address (A)
Target address from the cache address table (B).
Find dress (logical address). In this case, each CPU
Is a select line instruction (function) from the same address (A)
"Select Line () ”is selected by each CPU.
All addresses point to the same physical address.

: One block (64 bytes) from the selected logical address is divided by each CPU.
Add the value obtained by multiplying the number by 16. The test address selected in this way has a value within the same memory block (64 bytes) as viewed from each CPU and with no duplicate access.

In this case, the select line instruction (function) is Line () = ｛C = ^* (B + (A & 0x
f8); D = C + (CPU number × 16); Return
(D) It is represented by｝. In this case, A is the link address,
B is a logical address, C is a physical address, D is an address shifted by 16 bytes, 16 bytes are shifted, 0xf8 is a lower bit, ^* is contents in parentheses, Return (D)
Means to return with the contents of D.

That is, Select Line () = ｛C =
^* (B + (A &0xf8); D = C + (CPU number × 1
6); Return (D)} is the logical address of B +
The value of (address A + lower-order bit “0xf8”) is used as the value of C, the value obtained by adding the value of (CPU number × 16) to the value of C is used as D, and the process returns with the value of D. Content.

FIG. 8A shows that each CPU executes the same command (test command or test command). FIG. 8B shows that even if the logical address B of each CPU is different, the physical addresses (cache physical addresses) converted from the logical address are all the same.

For example, the logical address “50” of CPU-0
“00000” is converted to a physical address “200000”, and the logical address “7000000” of the CPU-1 is converted to a physical address “200000”. Also, CP
The logical address “5002000” of U-0 is converted to the physical address “202000”, and the logical address “7002000” of the CPU-1 is converted to the physical address “20200”.
0 ”.

As described above, a specific instruction (select line instruction) for selecting a test target cache address is provided in the random instruction sequence executed by each CPU, and by executing this specific instruction, each CPU becomes identical. Test target cache address, and this address
A value obtained by adding the shift byte allocated to U is obtained, and this value allows the same cache address and the same access to be prevented from being seen from each CPU. In other words, the addresses selected by the select function can be prevented from overlapping in the same memory block when viewed from each CPU.

§7: Explanation of Example 6—See FIG. 9 FIG. 9 is an explanatory diagram of Example 6, (a) is an example of a routine table, (x) is a master CPU process (CPU-0), (y) )
Indicates slave CPU processing (CPU-1, 2, 3).
In this case, the CPU-0 is a master and the other CPUs are slaves, but any master CPU may be used. Example 6 is an example in which verification of intended cache coherency logic can be realized by a random instruction test by incorporating intended cache coherency logic into a random instruction sequence.

A routine for testing cache coherency (cache consistency) as shown in FIG. 9 is prepared in advance. For example, a routine table as shown in FIG. In the routine shown in FIG.
Using the F statement, processing units (x) and (y) dedicated to each CPU are provided. This is because this routine is started from all CPUs and different operations are performed for each CPU.

The dedicated processing units (x) and (y) for each CPU
This routine, which incorporates the logic of cache coherency (known as "MOESI" described in the conventional example), is developed at random in the process of generating a random instruction sequence, thereby achieving an intentional cache coherency test. Will be possible. Hereinafter, the detailed logic in the routine will be described.

First, a cache line to be tested (see the hatched portion in FIG. 2) is selected (Select). Line command)
After synchronizing the CPUs, the CPU branches to the instruction sequence of each CPU (processing is executed separately for each CPU). Here, by definition, CPU-0 is a master and other CPUs are slaves. The master sets a state in the cache.
For example, a store instruction (Store) is used. The slave changes the state of the cache set by the master. For example, a change is given by a load instruction (Load) (data is changed).

In this example, when the master has the latest cache information, a change in the cache state when the information is read from the slave is realized. In this way, by changing the store instruction and the load instruction, various state changes of the cache can be clearly realized, and the cache coherency (coherency of the cache) at that time can be verified.

As described above, the verification of the intended cache coherency logic can be realized by the random instruction test by inserting the routine shown in (a) at random when the random instruction sequence is generated. For example, the cache coherency has the following contents. That is, the data is stored in the main memory 1 and the L1 #, L1 of each CPU.
2), the latest data does not necessarily have to be in the main memory 1;
Or L2}.

That is, the latest data may be in the main memory 1 or any of L1 # and L2 # of each CPU, and may be anywhere, but must be always somewhere. All of these logics are "MOESI"
It is processed according to the logic established as.

§8: Explanation of Example 7—See FIGS. 10 and 11 FIG. 10 is an explanatory diagram (part 1) of Example 7, where FIG. 10A is an instruction definition body of an intermediate language, and FIG. is there. FIG.
1 is an explanatory diagram (part 2) of Example 7, and (x) is master C
PU processing (CPU-0) and (y) show slave CPU processing (CPU-1, 2, 3).

Example 7 is an example in which the intended combination of cache data in the cache coherency test is realized at random by incorporating the intended cache coherency logic into the random instruction sequence.
In the method of Example 7, one intended cache operation can be realized by one routine. However, since the original test is a random instruction test, the intended cache operation is given randomness, and the combination of cache operations is changed. It is desirable to be able to do it in one routine. A technique for realizing this will be described below.

First, an instruction definition body of an intermediate language (macro instruction) as shown in FIG. 10A to be defined in the routine is prepared. This intermediate language (macro instruction) is analyzed by a generator that generates a random instruction sequence, and is converted into an executable instruction.

In this case, one of the parameters of the intermediate language
First, the following functions are provided. That is, "C
HAIN "," CHAIN LIMIT ”,“ END ”
In each of the instructions “CHAIN”, “CHAIN” means that there is an instruction sequence thereafter, and “CHAIN” LIMIT "
Means that there is an instruction sequence after that, and the instruction sequence specified by this parameter (provided that it is continuous)
On the other hand, this means that the order of instructions to be developed is randomly changed when the data is developed in the memory. “END” means the end of the instruction sequence.

The above function will be described with an example. FIG.
FIG. 11B and the example shown in FIG.
This is one example of the safety test. In this case, CPU-0, 1,
2 and 3 are store instructions (STORE) from the initialization state respectively
After executing the load instruction (LOAD),
Some commands that change the state of the flus
h, U flush, Load, Store, Casxa)
"CHAIN B in FIG. 10 with "LIMIT" added.
Create the table shown in.

When this table is selected from the generator, the table is replaced with an executable instruction (machine language) in order from the top. In this process, the instruction sequence of (b) shown in FIG. 11 is replaced. At this time, since the order of the instruction to be replaced changes, a different instruction sequence is generated every time this table is selected. Of the cache state can be realized.

Therefore, by changing the type of the instruction for changing the cache state and the state immediately before issuing the instruction, which is the object of the test, many cache state transition tests can be realized with a small number of tables.

§9: Explanation of Example 8—See FIG. 12 FIG. 12 is an explanatory diagram of Example 8, wherein FIG. 12A is an explanatory diagram of a random instruction, FIG. Example 8 is a technique that enables a cache coherency test of an instruction to be realized. Instead of the cache coherency of data (normal data other than an instruction) as in Examples 1 to 7, it is necessary to have a plurality of instruction execution spaces to enable a cache coherency test of an instruction. A method that satisfies this condition and enables the functions of Examples 1 to 7 is realized by the following procedure.

: The generated random instruction sequence is completely copied to another space.

MM: Both random instruction spaces (original instruction space and copied instruction space) have the same logical address and different physical addresses (random instruction space).
Create a U table (address conversion table). Then, different context values are defined in each MMU table. The context in this case is a control register for switching the space, and the context value is the value of the control register.

Context value = 10 as an initial value
For example, the test is started from logical address = 0x000000.

[0127] When a certain interrupt occurs, the logical address of the instruction is arbitrarily selected from the MMU table. The address in the random instruction sequence (if the space of the random instruction sequence is assumed to be 1 MB, the address obtained by ORing the value of the 1 MB boundary) is set in the instruction counter to this value.

For example, when an interrupt occurs at address 0x505010, a new instruction address (0x70000000)
0) plus a random instruction sequence address (0x50010) = 0x705010. By returning at this address, the execution order of the random instruction sequence is not disturbed, and the logical address can be changed.

Also, upon a certain interrupt, the context is switched to a different context value (10 → 2
0) is obtained. Thus, only the physical address can be changed without changing the instruction counter of the logical address. In this case, an instruction in a random instruction space of 0x300000 operates.

By the above-mentioned processing, the random instruction sequence is sequentially executed from the beginning, and only the space to be executed changes. That is, since the physical space to be executed and the execution logical address are sequentially switched, a cache coherency test of the instruction can be performed.

Assuming that L2 # is 2 MB, replacing an actual address with an address 2 MB away causes cache replacement. Also, L1 ＄ is 64K
Assuming that the B is 4 Way, the cache is replaced by accessing a logical address 16 KB apart 5 times.

§10: Description of Test Example—See FIGS. 13 and 14 FIG. 13 is an explanatory diagram of the test example, and FIG. 14 is a flowchart of random instruction sequence generation processing. Hereinafter, specific test examples will be described with reference to FIGS.

(1): Description of Test Example The cache coherency test is performed, for example, as follows.

: Start the same task from all CPUs.

The started task is divided into a master CPU (CPU-0 in this example) and slave CPUs (CPU-1, 2, 3,..., N in this example). Is generated.

Perform random instruction generation processing (to be described later).

: After instruction generation, all CPUs synchronize
After that, each CPU sets an initial value in the register and passes the process to the head of the generated random instruction area. In this case, the registers (for example, G1: index only, G2: base register only) allocated exclusively for the access of the access instruction among the registers for setting the initial values include the logical address indicating the data area and the address. Set an index value to point to the displacement of The access is changed by a subroutine called from the random instruction sequence. The change may be made in response to some interruption.

Return to the original task by the last return processing of the random instruction sequence.

Finally, the data obtained as a result of the test is compared. The logic of this data comparison is, for example, as shown in the following a and b.

A: Trace the contents of all registers and memory under a certain condition (for example, an interrupt) in the execution of a random instruction sequence. In this case, this random instruction sequence is executed twice while changing the running environment, and when the second execution is performed, the random instruction sequence is compared with the information traced the first time.

B: This task process is executed by the actual machine and the soft simulator, and the contents of both registers and the memory are compared under certain conditions.

(2): Random Instruction Generation Processing Hereinafter, random instruction generation processing will be described with reference to FIG. In addition, S1 to S8 indicate each processing step. When the process of generating a random instruction is started, first, random data is written in the instruction generation area (S1). Next, using the random data in the instruction generation area, an arbitrary one is extracted from the routine table or the instruction conversion table, converted into an instruction, and then the instruction or the instruction sequence is written in the instruction generation area.

By sequentially performing this processing, a random instruction is created in the entire instruction generation area. Specifically, it is as follows. After writing the random data in the instruction generation area as described above, the pointer P is set at the head of the instruction generation area (S2). Then, branch to one of the contents of the pointer P (S3).

When branching to one side, the following processing is performed. First, arbitrary instruction data is randomly selected from the instruction conversion table, and an instruction is generated by multiplying AND data and OR data in the instruction data and random data read from the pointer P. The generated instruction has a pointer P
At the address. When generating an access instruction, the AND / OR data is defined so that a predetermined access register is selected (S4).

Thereafter, the value of the pointer P is updated (S
5), a final determination is made (S6), and the processing from S3 is repeated until the final processing is performed. If the process branches to the other as a result of the process in S3, the process is performed as follows. First, an arbitrary routine is randomly selected from the routine table, the command sequence in the routine is sequentially converted into an instruction, and the instruction is stored after the address of the pointer P (S
7). After that, the value of the pointer P is updated by the number of instructions of the generated instruction (S8), and the process shifts to S6. The above processing is performed, and when it is determined in the final determination that the processing has been completed up to the final processing, the random instruction generation processing ends.

§11: Description of Test Program and Recording Medium The information processing apparatus (information processing system) shown in FIG. 2 has a communication control unit, a display device, a keyboard, and a flexible disk in addition to the configuration shown in FIG. A drive (floppy disk drive) (hereinafter referred to as “FDD”), a CD-ROM drive, a hard disk drive (hereinafter referred to as “HDD”), and the like are provided.

Then, the system shown in FIG.
The program stored (recorded or stored) in the OM 6 is read out under the control of the CPU and stored in the main storage memory 1, and the CPU executes the program to execute the cache coherency test (the information processing device). Test).

However, the present invention is not limited to such an example. For example, a test program is stored in the hard disk of the HDD as follows, and this program is stored in the CP.
The cache coherency test can be performed by U executing.

A program (program data created by another device) stored in a flexible disk (floppy disk) created by another device is copied to an FD.
D and stored in the recording medium (hard disk) of the HDD.

: Magneto-optical disk or CD-ROM
Data stored in a storage medium such as a CD-ROM
The data is read by the drive and stored in the recording medium (hard disk) of the HDD.

: Receives data such as a program transmitted from another device via a communication line such as a LAN via a communication control unit, and stores the data on a recording medium (hard disk) of an HDD.

[0152]

As described above, the present invention has the following effects.

(1): With an increase in the number of access registers causing cache coherency and an increase in the probability of occurrence of cache replacement, it is possible to verify the cache coherency function utilizing the characteristic of random instruction generation. In other words, by generating a random instruction before and after an access instruction affecting the cache, the transmission timing of the access instruction can be shifted, and the state of the cache can be verified in various environments. Therefore, hardware quality can be improved.

(2): A cache coherency test using random instructions for multiple CPUs,
Can access the same block, and a cache coherency test can be realized by preventing data from being destroyed by another CPU.

(3): In a test method for an information processing apparatus in which a random instruction sequence is generated in the CPU and a cache coherency test is performed in an information processing device having a multi-CPU configuration, the random instruction sequence is generated with a random instruction sequence. The value of the base register indicating the operand address of the access instruction is
The value is shifted by a constant value for each PU, and the value of an index register indicating the index portion of the operand address and the displacement value in the operand address are defined in advance.

In this way, when the same instruction is executed from all CPUs, the access address of the access instruction becomes an address range which is always determined for each CPU (for example,
16 bytes). That is, all CPUs
It is possible to avoid duplicate access from each CPU when the same access space is allocated to the CPU.

Therefore, in a random instruction test for multiple CPUs, a cache coherency test can be realized so that each CPU can access the same block and data is not destroyed by another CPU.

(4): When testing the information processing apparatus,
A plurality of different contexts having the same logical space and switchable by an instruction are prepared. Then, each context has correspondence information between the logical address and the physical address of the real memory, and in the process of executing the random instruction sequence, when the context is switched by a specific instruction, the same logical address is accessed. Cache replacement is performed by pointing to a different physical address of the memory. This makes it possible to generate a larger number of cache replacements.

(5): When testing the information processing apparatus,
A specific instruction for selecting a test target cache address is provided in a random instruction sequence executed by each CPU, and by executing this specific instruction, each CPU selects the same test target cache address, and Each CP
A value obtained by adding the shift bytes allocated to U is obtained, and this value is used to prevent the access from being duplicated at the same cache address as seen from each CPU.

That is, it is possible to derive a memory address from the plurality of CPUs that does not duplicate access in the same memory block to be tested. In this way, it is possible to implement a method of incorporating the intended cache coherency logic into the random instruction sequence, and it is possible to reduce the realization time of all combinations at the time of testing.

(6): When testing the information processing apparatus,
A process of copying the generated random instruction sequence to another space;
For both random instruction spaces, create an address translation table having the same logical address and different physical address, define a different context value in the table, and set a value in the context as an initial value. A process for starting a test from a logical address, a trigger for selecting a logical address of an instruction from the address conversion table, and a process for setting an address in a random instruction to an instruction counter to this value. As an opportunity,
By switching the value of the context, a process of changing only the physical address without changing the instruction counter of the logical address is performed.

By the above-described processing, the random instruction sequence is sequentially executed from the beginning, and only the execution space is changed, thereby enabling the cache coherency test of the instruction cache.

(7): By reading and executing the program on the recording medium, the value of the base register indicating the operand address of the access instruction generated by the random instruction sequence is shifted by a constant value for each CPU. Set,
A value of an index register indicating an index portion of the operand address and a displacement value in the operand address are defined in advance.

In this way, when the same instruction is executed from all CPUs, the access address of the access instruction can point to an address range that is always determined for each CPU. That is, duplicate access from each CPU when the same access space is allocated to all CPUs can be avoided.

Therefore, in a random instruction test for multiple CPUs, a cache coherency test can be realized while each CPU can access the same block and data is not destroyed by another CPU.

With respect to the above description, the following items are further disclosed.

(A): A plurality of CPUs are connected by a bus
A multi-CPU information processing device having a cache memory in a PU, and in the CPU, adds an index register value or a displacement value to a base register value to generate an operand address of an access instruction. By doing so, in a test method for an information processing apparatus that generates a random instruction sequence and performs a cache coherency test, a general-purpose register, an in-register, a local register, and an out-register for each window, When pointing, when only the register of the window at that time and the general-purpose register can be used, a different address of the logical space is set in advance in a local register provided for each window, and the local register is set. Is switched by a window, and the Use as the base register that points to the operand address of an access instruction generated by the instruction sequence, by using the general-purpose register as an index register to point to the index of the operand address, only the switching of the window by the instruction,
Realize more cache coherency operating environment.

In this way, an operating environment of cache coherency can be easily realized by simply using a large number of existing registers and simply switching windows. Further, since there are many registers that can be used as base registers, many operating environments can be easily realized.

(B): A plurality of CPUs are connected by a bus
A multi-CPU information processing device having a cache memory in a PU, and in the CPU, adds an index register value or a displacement value to a base register value to generate an operand address of an access instruction. By doing so, in a test method of an information processing device that generates a random instruction sequence and performs a cache coherency test, a value of an index register and a displacement value, which are conditions for determining an address of an access instruction, are stored in a cache memory. With respect to the value n defined by the width, the number of times of cache replacement is generated more by fixing at three places of -n, 0, and + n so that other values are not generated.

As described above, the value of the index register and the displacement value, which are the conditions for determining the address of the access instruction, are calculated by subtracting the value n (for example, n = 64) defined by the width of the cache memory from- n, 0, + n
If the values are fixed at the three positions described above and other values are not generated, the number of times of cache replacement can be generated more.

(C): A plurality of CPUs are connected by a bus
A routine for testing cache coherency in an information processing apparatus test method for generating a random instruction sequence in the CPU and performing a cache coherency test for an information processing apparatus having a multi-CPU configuration having a cache memory in a PU Is prepared, and each CP is
A dedicated processing unit is provided for each U, and this dedicated processing unit incorporates the logic of the cache coherency test into this routine.
By random development in the process of generating a random instruction sequence, verification of the intended cache coherency logic can be realized by a random instruction test. If you do this,
Verification of the intended cache coherency logic can be realized by random instruction testing.

(D): A plurality of CPUs are connected by a bus
In a test method for an information processing apparatus that performs a cache coherency test by generating a random instruction sequence in the CPU for a multi-CPU information processing apparatus having a cache memory in a PU, Prepare and analyze this macro instruction by the generation means that generates a random instruction sequence, and in the process of converting it from the beginning to the executable form instruction, by changing the order of the instructions to be developed at random, Realize the transition. In this way, more cache state transitions can be realized and a cache coherency test can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram in the embodiment of the present invention.

FIG. 3 is an explanatory diagram (part 1) of Example 1 in the embodiment of the present invention.

FIG. 4 is an explanatory diagram (part 2) of Example 1 in the embodiment of the present invention.

FIG. 5 is an explanatory diagram of Example 2 in the embodiment of the present invention.

FIG. 6 is an explanatory diagram of Example 3 in the embodiment of the present invention.

FIG. 7 is an explanatory diagram of Example 4 in the embodiment of the present invention.

FIG. 8 is an explanatory diagram of Example 5 in the embodiment of the present invention.

FIG. 9 is an explanatory diagram of Example 6 in the embodiment of the present invention.

FIG. 10 is an explanatory diagram (No. 1) of Example 7 in the embodiment of the present invention.

FIG. 11 is an explanatory view (No. 2) of Example 7 in the embodiment of the present invention.

FIG. 12 is an explanatory diagram of Example 8 in the embodiment of the present invention.

FIG. 13 is an explanatory diagram of a test example according to the embodiment of the present invention.

FIG. 14 is a flowchart of a random instruction sequence generation process according to the embodiment of the present invention.

FIG. 15 is a system configuration diagram of a conventional example.

FIG. 16 is an example of a conventional random instruction test.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main memory (main memory) 2 System controller 3 Cache control unit 4 Cache information table 5 I / O control unit (input / output control unit) 6 ROM 9 Cache memory L1 Primary cache (Primary cache memory) L2 ＄ Secondary Cache (secondary cache memory)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/08 320 G06F 12/08 320 12/12 12/12 A 12/16 330 12/16 330B 13 / 00 301 13/00 301T F-term (reference) 5B005 JJ01 KK12 LL11 MM05 MM12 PP12 RR02 UU32 VV22 5B018 GA03 HA32 MA03 QA13 RA11 5B045 BB12 DD12 JJ02 5B048 AA17 AA19 FF03 5B083 AA08 BB08 CE01EE02

Claims (5)

[Claims] 1. A multi-CPU information processing apparatus in which a plurality of CPUs are connected by a bus and each CPU is provided with a cache memory. In the CPU, a base register value, an index register value, or In a test method of an information processing apparatus for generating a random instruction sequence and performing a cache coherency test by adding a displacement value and generating an operand address of an access instruction, the access instruction generated by the random instruction sequence The value of the base register indicating the operand address is set to a value shifted by a constant value for each CPU, and the value of the index register indicating the index portion of the operand address and the displacement value in the operand address are defined in advance. The same access to all CPUs. Each CPU at the time of allocation of space
A method for testing an information processing apparatus, characterized by avoiding duplicate access from a user. 2. A multi-CPU information processing apparatus having a plurality of CPUs connected by a bus and a cache memory for each CPU. A random instruction sequence is generated in the CPUs to perform a cache coherency test. In the test method for an information processing device, a plurality of different contexts having the same logical space and switchable by an instruction are prepared, and each of the contexts has correspondence information between a logical address and a physical address of a real memory, and the random instruction In the process of executing a column, when the context is switched by a specific instruction, even if the same logical address is accessed, the cache is replaced by pointing to a different physical address in the real memory, and the number of cache replacements is generated more. A method for testing an information processing apparatus, the method comprising: 3. A cache coherency test is performed by connecting a plurality of CPUs via a bus and generating a random instruction sequence in the CPU for a multi-CPU information processing apparatus having a cache memory for each CPU. In the test method for an information processing device, a specific instruction for selecting a test target cache address is provided in the random instruction sequence executed by each CPU, and the execution of the specific instruction causes each CPU to execute the same test target cache. An address is selected, and a value obtained by adding a shift byte allocated to each CPU to this address is obtained.
A test method for an information processing apparatus, characterized in that the same cache address and the same access are not duplicated when viewed from each CPU by using this value. 4. A cache coherency test in which a plurality of CPUs are connected by a bus and a random instruction sequence is generated in said CPU for a multi-CPU information processing apparatus having a cache memory for each CPU. In the test method of the information processing apparatus, a process of copying the generated random instruction sequence to another space, and creating an address translation table having the same logical address and different physical address for both random instruction spaces, A process of defining a different context value as an initial value, a process of setting a value to a context as an initial value, and starting a test from a certain logical address, and a certain interrupt triggering the logical address of an instruction from the address conversion table. Select and set the address in the random instruction to the instruction counter to this value. The machine, by switching the value of the context, the unchanged instruction counter of the logical address, and a process to be able to change only the physical address, by the process, sequentially perform a random instruction sequence from the beginning,
A test method for an information processing apparatus, wherein a cache coherency test of an instruction cache is enabled by changing only an execution space. 5. A multi-CPU information processing device in which a plurality of CPUs are connected by a bus and each CPU is provided with a cache memory. In the CPU, a base register value, an index register value, or By adding a displacement value and generating an operand address of an access instruction, an information processing apparatus that generates a random instruction sequence and performs a cache coherency test is provided with an operand address of an access instruction generated by the random instruction sequence. Setting the value of the base register pointing to a value shifted by a constant value for each CPU; and predefining the value of the index register pointing to the index part of the operand address and the displacement value in the operand address. And the program to execute Computer readable recording medium.