JP2001043111A - Interruption control circuit and microcontroller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interruption control circuit equipped with a means for improving reliability by preventing runaway of a microcomputer system by outputting a control signal of write/read to a memory and controlling generation of the interruption request signal to a CPU on the basis of contents of a control register. SOLUTION: A control register 7 sets a write/read condition of the memory and the condition of interruption to a CPU 21. A control circuit 8 receives coincidence signals ch0 and ch1 from comparators 5 and 6 and a signal 28 for controlling the write/read of a RAM 24 from the CPU 21 and outputs a signal 70 for controlling the write/read and a flag signal 73 showing the generation of interruption corresponding to a value of the control register 7. A flag register 9 holds the flag signal 73 showing the interruption generation outputted from the control circuit 8. On the basis of the flag signal 73 showing the interruption generation, an interruption signal generating circuit 10 generates an interruption request signal 71.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a one-chip microcontroller, and more particularly to a circuit which is built in a semiconductor integrated circuit such as a one-chip microcomputer and generates an interrupt.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing an example of the configuration of a conventional one-chip microcomputer, that is, a one-chip microcontroller. The CPU 21 performs a processing operation according to a program. I / O port, ie I / O port 2
2 exchanges data with the outside of the one-chip microcomputer. The ROM 23 is a read-only memory for storing programs. The RAM 24 is a writable / readable memory for temporarily recording calculation results and data.
The watchdog timer 25 resets the one-chip microcomputer or generates an interrupt to the CPU 21 according to the overflow of the counter value. The address bus 26 transfers addresses from the CPU 21 to the RAM 24 and the ROM 23. The data bus 27 is connected to the CPU 2
1, the data is transferred to and from the RAM 24 and the ROM 23.
Write / read control signal output from CPU 21
The iwre 28 controls writing / reading of data in the RAM 24, the ROM 23, and the like.

A one-chip microcomputer of this kind is mainly used as a system controller of an embedded control device.
Such an embedded control device is called a microcomputer system.

As an example of a microcomputer system, an automobile engine control system will be considered. In the engine control system of the automobile, the CPU 21 receives a signal from an accelerator or the like via the I / O port 22, executes calculation and data processing according to a program stored in the ROM 23, and controls the I / O port 22. The processing result is sent to the engine via the engine, and the gasoline injection amount of the injector is controlled.

In a conventional one-chip microcomputer, a watchdog timer 25 is provided as a measure against a runaway in order to increase the reliability of a microcomputer system such as an engine control system of an automobile. Watchdog timer 25
Is a timer that can set a counter value, and resets the one-chip microcomputer or generates an interrupt to the CPU 21 when the counter overflows.

A method for monitoring a system using a watchdog timer is as follows. The counter of the watchdog timer 25 is set to 0 to operate the timer. During normal operation, before the timer overflows,
The CPU 21 sets the counter of the watchdog timer 25 to 0
And repeat the operation from the beginning. If the CPU 21 cannot clear the counter to 0 due to a runaway or the like, an overflow of the watchdog timer 25 occurs, and a one-chip microcomputer reset or an interrupt to the CPU 21 occurs.

Next, from the viewpoint of the program configuration, prevention of runaway of the microcomputer system using the watchdog timer 25 will be considered. The program installed in the one-chip microcomputer will be divided into two, an operating system OS and an application program App. O
S manages basic operations such as scheduling of the microcomputer system. The application program actually executes control of the engine control system and the like.

In this case, the program for setting the watchdog timer 25 is the OS, and the set time is the execution time of the application program to be executed next.
If the application program is working properly,
Since the CPU 21 can transfer control from the application program to the OS within the installation time, the watchdog timer can be cleared during execution of the OS. If the application program runs away, the CPU 21 cannot transfer control to the OS within the set time of the watchdog timer 25, so that the watchdog timer 25 cannot be cleared to 0, the timer overflows, and the one-chip microcomputer Is reset or an interrupt to the CPU 21 occurs.
Generally, the reliability of the microcomputer system is secured by such a mechanism.

[0009]

However, in the case of such a system, the conventional countermeasure does not prevent runaway beforehand, but is merely a symptomatic treatment after runaway.

Moreover, once a runaway occurs, a timer overflow occurs and the runaway continues until a reset or an interrupt occurs.
At the maximum, the time corresponding to the set value of the counter is required. A rewritable area such as the RAM 24 has a high probability of being rewritten during a runaway.

Therefore, even if the control is transferred to the runaway processing routine due to the interruption, the data has already been destroyed and the system cannot be returned to the state immediately before the runaway.

In particular, when the data area of the OS is destroyed, the OS itself may malfunction, and there is no way to recover from the runaway state except for resetting the system.

For example, in an engine control system of an automobile, resetting may directly lead to an accident. In many cases, resetting cannot be easily performed while the system is operating. Therefore, the reliability of conventional system monitoring using a watchdog timer is not high. Was enough.

A method for preventing the runaway in advance will be considered. One cause of microcomputer system runaway is that data stored in a writable area such as RAM or stack data such as a CALL instruction is destroyed for some reason.
The OS or the application program accesses the destroyed data.

The current 32-bit class high-performance microprocessor has a function of protecting the memory by giving the CPU a memory management function by switching the CPU operation mode in order to minimize the destruction of data in the RAM and the like. That is, the operation of the CPU is divided into an OS and an application program, and correspondingly, a data area related to the foundation of the microcomputer system such as the OS and a data area accessed by the application program are divided, and the application program Make the area inaccessible. As a result, data writing to an inappropriate area due to a malfunction is prohibited, and runaway due to data destruction is prevented in advance.

In such a case, even if the application program goes out of control, it is possible to return from the runaway without resetting the system if control of the OS can be reliably transferred by an interrupt such as a watchdog timer. It is.

In a microprocessor such as the MIPS R2000 / R3000, an interrupt can be generated when an application program accesses the data area of the OS.

However, there are the following problems in a method of improving the reliability of the microcomputer system by using the memory management function of the operation mode switching method. To implement the memory management function, large logic must be 8 bits or 16 bits.
It must be placed on the CPU of the class.
U must be changed from its architecture, and this operation mode switching method cannot be applied to existing one-chip microcomputers.

When a one-chip microcomputer without a memory management function is used in a microcomputer system for which reliability is to be improved, it is necessary to change the microprocessor to a 32-bit class or higher-performance microprocessor. This requires a significant change in the program and redesign of the microcomputer system, resulting in an increase in system cost and a prolonged development period.

An object of the present invention is one of the causes of microcomputer system runaway in a microcomputer system using a one-chip microcomputer without a memory management function, without increasing the cost of the microcomputer system or lengthening the development period. An object of the present invention is to provide an interrupt control circuit having means for preventing unnecessary memory writing and preventing runaway of a microcomputer system and improving reliability, and a microcontroller incorporating the interrupt control circuit.

[0021]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an address register for designating an address causing an interrupt and a match between the address causing the interrupt and the address designated by the CPU. A match detecting means for detecting, a control register for setting a memory write / read condition and an interrupt condition to the CPU, and a memory write / read control signal based on the contents of the control register when a match is detected. And an output control circuit for controlling generation of an interrupt request signal to the CPU.

The interrupt control circuit may include a mask register for masking a part of the address specified by the address register.

Each interrupt control circuit can include a plurality of sets of address registers and coincidence detecting means or a plurality of sets of address registers, mask registers and coincidence detecting means.

In this case, the control means may have a function of permitting the occurrence of an interrupt in accordance with the order of coincidence of a plurality of designated interrupt occurrence addresses.

According to another aspect of the present invention, there is provided an I / O port for exchanging data with an external circuit, a CPU, a ROM for storing a program, and temporarily storing calculation results and data. A microcontroller having a writable / readable RAM and a watchdog timer for resetting the microcontroller or generating an interrupt to the CPU in response to an overflow of the counter value; A match detecting means for detecting a match between an address causing an interrupt and an address designated by the CPU; a control register for setting a RAM write / read condition and a CPU interrupt condition; , Control register contents Based outputs the write / read control signal to the RAM, and proposes a microcontroller and a control means for controlling the generation of an interrupt request signal to the CPU.

The microcontroller may include a mask register for masking a part of the address specified by the address register.

Each microcontroller can include a plurality of sets of address registers and coincidence detecting means or a plurality of sets of address registers, mask registers and coincidence detecting means.

In this case, the control means may have a function of permitting the occurrence of an interrupt in accordance with the order of coincidence of a plurality of designated interrupt occurrence addresses.

According to the present invention, in an interrupt control circuit for generating an interrupt upon an address match, an address register for specifying an address as a cause of an interrupt and detecting a match between the address as a cause of the interrupt and an address specified by a CPU. A match detection means, a control register for setting a memory write / read condition and an interrupt condition to the CPU, and a write / read to / from the memory based on the contents of the control register when the match is detected. Control means for outputting a control signal and controlling generation of an interrupt request signal to the CPU, so that when an address matches and an interrupt occurs, writing / writing of the matching address is performed.
By controlling read permission, erroneous data writing to the memory, which is one cause of runaway, can be prevented, and an interrupt process can be generated immediately after an erroneous write attempt, thereby preventing runaway.

In addition, since control means for permitting an interrupt to be generated in accordance with the order of coincidence between a plurality of registers and an address is provided, data can be transferred more variously and interrupts can be controlled in accordance with the order of access to the storage device. A memory management function that performs

The interrupt control circuit of the present invention always monitors an address irrespective of the operation mode of the CPU, and protects data in a storage device and interrupts by matching an address with the contents of a register installed according to the present invention. Control.

This memory management function can be realized without changing the CPU architecture. Therefore, the existing CP
Since it is not necessary to change the core portion of the U, changes in the OS and the like can be minimized, and the reliability of the microcomputer system can be enhanced while suppressing an increase in cost and development period.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION

[0034]

FIG. 2 is a block diagram showing a configuration of a first embodiment of a one-chip microcomputer incorporating an interrupt control circuit according to the present invention. As is apparent from comparison with the configuration of the conventional one-chip microcomputer of FIG. 1, the first embodiment adds an interrupt control circuit 69 and an OR circuit 72 to the conventional one-chip microcomputer of FIG. Write / read control signal iw
In response to re28, the interrupt control circuit 69 sends a write / read control signal wre70 and an interrupt request signal irq71.
And a one-chip microcomputer configured to output

The CPU 21 executes a processing operation according to a program. I / O port or input / output port 22
Exchanges data with the outside of the one-chip microcomputer.
The ROM 23 is a read-only memory for storing programs. The RAM 24 is a writable / readable memory for temporarily recording calculation results and data. The watchdog timer 25 resets the one-chip microcomputer according to the overflow of the counter value, or
An interrupt to the PU 21 is generated. Address bus 2
6 transfers an address from the CPU 21 to the RAM 24 and the ROM 23. The data bus 27 is connected to the CPU 21, R
The data is transferred to and from the AM 24 and the ROM 23. CPU
21 is a write / read control signal iwre2
Reference numeral 8 controls writing / reading of data in the RAM 24, the ROM 23, and the like.

FIG. 3 is a block diagram showing a circuit configuration of an embodiment of the interrupt control circuit according to the present invention. The address registers 1 and 2 store an address at which an interrupt is to be generated. The mask registers 3 and 4 specify a mask of the matching address bits. The comparators 5 and 6 compare the value of the address bus with the values of the address registers 1 and 2 and output coincidence signals ch0 and ch1 when they match. The control register 7 stores the write / read conditions of the memory and C
An interrupt condition for the PU 21 is set.

The control circuit 8 receives the coincidence signals ch0 and ch1 from the comparators 5 and 6, and the signal iwre 28 for controlling the writing / reading of the RAM 24 from the CPU 21, and writes / reads according to the value of the control register 7. Control signal wre70 and a flag signal 7 indicating the occurrence of an interrupt
3 is output.

The flag register 9 holds a flag signal 73 output from the control circuit 8 and indicating the occurrence of an interrupt.
The interrupt signal generation circuit 10 generates an interrupt request signal irq71 based on a flag signal 73 from the flag register 9 indicating occurrence of an interrupt.

The address register 1, the mask register 3, and the comparator 5 are independent from the address register 2, the mask register 4, and the comparator 6, and in this example, the two set addresses are set. Interrupt can be generated.

In this specification, the address register 1, the mask register 3, and the comparator 5 are referred to as channel 0, the address register 2, the mask register 4, the comparator 6
Is referred to as channel 1. The number of channels is not limited to two, and may be further increased.

FIG. 4A is a diagram showing an example of the configuration of the control register 7. As shown in FIG. The control register 7 for setting the conditions for writing / reading and interrupts is
The PU 21 is a writable / readable register.

The bit of the control register 7 shown in FIG.
0 indicates that the address set in the channel 0 address register 1 and the address accessed by the CPU 21 on the address bus 26 match, and when the match signal ch0 of the channel 0 is output, the permission of writing data to the matched address is set. This bit (WE0) sets prohibition. When this bit is 1, writing is prohibited.

The bit of the control register 7 shown in FIG.
1 indicates that when the address set in the channel 1 address register 2 matches the address accessed by the CPU 21 on the address bus 26, and when the match signal ch1 of channel 1 is output, the permission of data writing to the matched address is obtained. This bit (WE1) sets prohibition. When this bit is 1, writing is prohibited.

Bit 2 in FIG. 4A is a bit (IE0) for setting permission / inhibition of interrupt generation by the coincidence signal ch0 of channel 0. When this bit is 1, channel 0
Enable interrupt generation by.

Bit 3 in FIG. 4A is a bit (IE1) for setting permission / inhibition of the occurrence of an interrupt by the coincidence signal ch1 of channel 1. When this bit is 1, channel 1
Enable interrupt generation by.

FIG. 4B is a diagram showing an example of the configuration of the flag register 9. Bit 0 in FIG.
The address set in the address register 1 matches the address accessed by the CPU 21 on the address bus 26,
This bit (f0) is set to 1 when the coincidence signal ch0 of the channel 0 is output and IE0 of bit 2 of the control register 7 is 1, that is, when the interrupt generation by the channel 0 is permitted.

In bit 1 of FIG. 4B, the address set in the channel 1 address register 2 matches the address accessed by the CPU 21 on the address bus 26, and a match signal ch1 of channel 1 is output. This bit (f1) is set to 1 when IE1 of bit 3 of bit 7 is 1, that is, when interrupt generation by channel 1 is permitted.

The CPU 21 can read the contents of the flag register 9 and clear the flag. Flag register 9
Once set, the flag is not cleared unless the CPU 21 clears it.

When the bit 0 (f0) of the flag register 9 is set to 1 or the bit 1 (f1) is set to 1, the interrupt generation circuit 10 generates an interrupt request signal irq71.

FIG. 4C is a diagram showing an example of the configuration of the mask registers 3 and 4. The mask registers 3 and 3 shown in FIG.
If 4 is set, it is not an exact address match,
Only predetermined areas can be matched. That is, if 4 (hex) is input to the mask register, the address bit
3 to 0 are excluded from comparison.

For example, channel 0 address register 1
Is set to 5555 (hex) and the set value of mask register 3 is set to 4
In this case, the match signal ch0 is output for addresses between addresses 5550 to 555F (hex). Similarly, when the set value of the channel 1 address register 2 is 7777 (hex) and the set value of the mask register 4 is 5, addresses 7700 to 77
A match signal ch1 is output for addresses up to FF (hex).

FIG. 5 shows the verilog of the control circuit 8 of the first embodiment.
FIG. 18 is a diagram illustrating an example of an HDL (IEEE Std1364) description. The control circuit 8 controls the coincidence signals ch0 and ch1 from the comparators 5 and 6 with C
A signal iwre28 for controlling writing / reading of the RAM 24 from the PU 21 is received, and a signal wre7 for controlling writing / reading according to the value of the control register 7 is received.
0 and a flag signal 73 indicating occurrence of an interrupt are output.
The flag register 9 holds a flag signal 73 output from the control circuit 8 and indicating the occurrence of an interrupt. In addition, CPU
The write / read signal iwre 28 from 21 is iwre = 1 at the time of writing and iwre = 0 at the time of reading.

First, write / read control will be described. Normally, the write / read control signal wre7
0 matches the write / read signal iwre28, wre
= Iwre.

On the other hand, when WE0 = 1 and ch0 = 1, that is, a bit (WE0) for setting permission / inhibition of data writing to the coincident address of the control register 7 is set.
Is set to write-protection, and when the value set in the channel 0 address register 1 matches the address accessed by the CPU 21, the write / read control signal wre70 is forcibly set to wre = 0.

When WE1 = 1 and ch1 = 1, that is, the bit (WE1) for setting permission / inhibition of data writing to the coincident address of the control register 7 is set to write inhibition, and the channel 1 address is set. When the value set in the register 2 matches the address accessed by the CPU 21, the write / read control signal wre
70 is forcibly set to wre = 0.

Next, control of the flag register 9 will be described. if0 and if1 are input signal names of the flag register 9. If IE0 = 1 and ch0 = 1, that is, if IE0 of the control register 7 is set to generate an interrupt and the value set in the address register 1 of channel 0 matches the address accessed by the CPU 21, if0 = 1. This value is input to the flag register 9 and f0 = 1.

If IE1 = 1 and ch1 = 1, that is, WE1 of the control register 7 is set to write-protection, and the value set in the channel 1 address register 2 matches the address accessed by the CPU 21. In this case, if1 = 1. This value is input to the flag register 9, and f1 = 1.

FIG. 6 shows the verilog of the interrupt generation circuit 10.
FIG. 18 is a diagram illustrating an example of an HDL (IEEE Std1364) description. of
0 and of1 are output signal names of the flag register 9 and f0 = of
0, f1 = of1. f0 or f1 = 1, ie, of0 or of1
When = 1, it is a logic for generating an interrupt.

FIG. 7 is a diagram showing an example of a program of the microcomputer system. FIG. 7A shows a memory map,
FIG. 7B shows the control procedure. In this case, O
S and App1 and App2, the stack and data area of the OS are E800 to EFFF (hex), and the stack and data area of App1 and App2 are E000 to E7.
Let it be FF (hex).

[0060] App1 and App2 are executed under the management of the OS. That is, App1 and App2 are
It is executed in the flow of OS → App1 → OS, OS → App2 → OS, and execution does not directly go from App1 to App2 or from App2 to App1.

In the OS, E800 is stored in the address register 1.
(hex) and bit 14 of the address in the mask register 2.
The control register 7 is set so as to mask up to -bit0. In this way, channel 0 will be
For values up to EFFF (hex), the match signal c for channel 0
Outputs h0. IE0 for enabling an interrupt is set for a match of ch0, and a flag WE0 for inhibiting writing to an address of channel 0 is set to 1. After the setting, the CPU 21 executes App1 or App1 from execution of the OS.
Execute p2.

Since the stack and data area of App1 or App2 are E000 to E7FF (hex),
During the execution of 1, App2, usually only the range of E000 to E7FF (hex) is accessed. Therefore, the value of the channel 0 address register 1 does not match the value of the address bus, and ch0 is not set.
Is not set to 1, no interrupt is generated, and the CPU 21 executes App1 and App2, and immediately moves the processing to the OS.

However, for example, App1 and App2 execute the calculation and store E000 to E7FF (h
When the range of (ex) is accessed and the result value has more digits than expected by the program and a write access is made to the E800, it matches the set value of the channel 0 address register 1, so ch0 is set, Since f0 is set to 1, the interrupt control circuit 69 of the present invention generates an interrupt to the CPU 21. After an interrupt occurs,
U21 executes error processing of the OS, reliably detects that App1 or App2 has accessed the stack or data area of the OS based on the interrupt information, and can execute processing of an abnormal access to the access prohibited area.
At this time, since the write prohibition flag WE0 is set, even when the CPU 21 makes a write access (iwre = 1) to the address E800 (hex), the write enable signal wre of the RAM is generated by the logic shown in FIG. , Wre = 0, E800 to EFFF (he by App1 or App2)
x) No data is written to the area, and the values of the stack and data area of the OS do not change.
OS can be executed normally.

Since the CPU 21 can operate the OS normally and execute abnormal processing by interruption, runaway of the microcomputer system can be prevented. Further, there is no need to perform a reset, and the reliability of the microcomputer system can be improved.

In the present invention, channel 1 and the like are also
Since operation can be performed in the same manner as channel 0, operation conditions such as channel 0 and channel 1 can be set independently.

[0066]

Second Embodiment FIG. 8A is a diagram showing an example of the configuration of a control register 7 of a second embodiment of a one-chip microcomputer incorporating an interrupt control circuit according to the present invention. The first and second embodiments are different from the control register 7, the control circuit 8,
Since only the internal circuits of the flag register 9 and the interrupt generation circuit 10 are different, the block diagram showing the entire configuration of the one-chip microcomputer of the second embodiment is shown in FIG. Also, the configuration of the interrupt control circuit is as shown in FIG.

Bit 0, bit 1, bit 4, bit 5 in FIG.
Has the same configuration as the first embodiment, and operates in the same manner.

Bit 2 in FIG. 8A indicates that the address issued by the CPU 21 matches the address of channel 0, and
This bit (WE2) sets permission / prohibition of writing data to the channel 1 address when the address matches the channel 1 address when the next instruction is executed. When this bit is 1, data writing is prohibited.

Bit 3 in FIG. 8A indicates that the address issued by the CPU 21 matches the address of channel 1 and
This bit (WE3) sets permission / prohibition of writing data to the address of channel 0 when the address matches the address of channel 0 when the next instruction is executed. When this bit is 1, data writing is prohibited.

Bit 6 in FIG. 8A matches the address of channel 0, and when the next instruction is executed, channel 1
This bit (IE2) sets permission / inhibition of interrupt generation when the address matches the address. When this bit is 1, interrupt generation is permitted.

Bit 7 in FIG. 8 (a) matches the address of channel 1 and, when the next instruction is executed, channel 0
This bit (IE3) sets permission / inhibition of interrupt generation when the address matches the address. When this bit is 1, interrupt generation is permitted.

Also in the second embodiment, the control register 7 for setting an interrupt condition is a register to which the CPU 21 can write / read.

FIG. 8B is a diagram showing an example of the configuration of the flag register 9 in the embodiment. Bit 0, b in FIG.
it1 is the same as in the first embodiment of the present invention.

Bit 2 in FIG. 8B indicates that the address issued by the CPU 21 matches the address of channel 0 and the address of channel 1 next, and that the control signal IE2 is 1. And bit (f2) to be set.

Bit 3 in FIG. 8B indicates that the address issued by the CPU 21 matches the address of channel 1 and the address of channel 0 next, and that the control signal IE3 is 1. Is the bit (f3) to be set.

Also in the second embodiment, the CPU 21 can read the contents of the flag register 9 and clear the flag. Once set, the flag register 9 is not cleared unless the CPU 21 clears it.

The bits f0, f1, and f of the flag register
If any of f2 and f3 is set, an interrupt occurs.

The control circuit 8 outputs a write / read control signal rwe70 in accordance with the setting of the control register 7, and controls the flag register 9.

The interrupt control circuit 10 sends an interrupt request signal ir to the CPU 21 based on the value of the flag register 9.
Generates q71.

FIG. 9 shows the verilog of the control circuit 8 of the second embodiment.
FIG. 18 is a diagram illustrating an example of an HDL (IEEE Std1364) description. CP
The write / read signal iwre from U21 is set to iwre = 1 at the time of writing and iwre = 0 at the time of reading.

First, write / read control will be described. Normal or if WE0 = 1 and ch0 = 1, W
The case of E1 = 1 and ch1 = 1 is the same as in the first embodiment.

When WE2 = 1, ST0 is set when the set value of the channel 0 address register 1 first matches the address value of the CPU 21, that is, when ch0 = 1. Next, when the set value of the channel 1 address register 2 matches the address value of the CPU 21 and ch1 = 1, that is, when ST0 = 1 and ch1 = 1, s
f2 = 1. When sf2 = 1 and WE2 = 1, force wr
e = 0.

In the case of WE3 = 1, ST1 is set when the set value of the channel 1 address register 2 and the address value of the CPU 21 first match, that is, when ch1 = 1. Next, when the set value of the channel 0 address register 1 matches the address value of the CPU 21 and ch0 = 1, that is, when ST1 = 1 and ch0 = 1, s
f3 = 1. When sf3 = 1 and WE3 = 1, force wr
e = 0.

Next, the flag control will be described. if
0, if1, if2, and if3 are input signal names of the register 9.
When IE0 = 1 and IE1 = 1, the operation is the same as in the first embodiment.

When IE2 = 1, ST0 is set when the set value of the channel 0 address register 1 and the address value of the CPU 21 match at first, that is, when ch0 = 1. Next, when the set value of the channel 1 address register 2 matches the address value of the CPU 21 and ch1 = 1, that is, when ST0 = 1 and ch1 = 1, s
f2 = 1. When IE2 = 1 and sf2 = 1, if2 = 1 and f2 of the flag register 9 is set.

In the case of IE3 = 1, ST1 is set when the set value of the channel 1 address register 2 and the address value of the CPU 21 first match, that is, when ch1 = 1. Next, when the set value of the channel 0 address register 1 matches the address value of the CPU 21 and ch0 = 1, that is, when ST1 = 1 and ch0 = 1, s
f3 = 1. When IE3 = 1 and sf3 = 1, if3 = 1, and f3 of the flag register 9 is set.

FIG. 10 shows an interrupt generation circuit 1 according to the second embodiment.
11 is a diagram illustrating an example of a verilog-HDL (IEEE Std1364) description of 0. FIG. of0, of1, of2, of3 are output signal names of the flag register 9, where f0 = of0, f1 = of1, f2 = of2, and f3 = of3. f0 or f1 or f2 or f3 = 1, that is, of0 or o
When f1 or of2 or of3 = 1, this is a logic for generating an interrupt.

FIG. 11 is a diagram showing an example of a program of the microcomputer system. FIG. 11A shows a memory map, and FIG. 11B shows a control procedure. task1 and
task2 is an internal task of App1. in this case,
The program repeats the operation in the order of OS → task1 → task2 → OS. task1 accesses E000 to E3FF (hex), and task2 accesses E400 to E7FF (hex). E000
~ E3FF (hex) and E400 ~ E7FF (hex) are continuous. Here, while App1 is running, task1 is E400 to E7FF (hex)
If the following is accessed, the next task2 is not executed normally,
Task1 is E400 ~
Suppose you want to prohibit access to E7FF (hex).

A method of preventing runaway from occurring in the program of FIG. 11 according to the second embodiment will be described. Channel 0
The start address 1000 (hex) of the address where the program of task 1 is stored is set in the address register 1, and 7 is set in the channel 0 mask register 3. With this setting, channel 0 is assigned to the task 1 program area (1000
-1FFF (hex)), the match signal ch0 is output.

Also, the channel 1 address register 2
The start address E400 (h
ex) is set, and 6 is set in the channel 1 mask register 4. As a result, the channel 1 sets the coincidence signal ch1 for the access prohibited area (E400 to E7FF (hex)) of task1.

Set WE2 and IE2 in the control register 7. As a result, after the address of the channel 1 matches, when the set value of the channel 1 matches the address of the CPU 21, an interrupt is generated, and writing to the set value of the channel 1 is prohibited.

First, the normal operation will be described. When the program is executed and the process moves from OS to task1, ch
The set value of 0 matches, ch0 is output, and ST0 is set. After that, task1 is the stack and data area of task1.
Access E000 to E3FF (hex). In this case, since there is no match with ch1, no interrupt is generated with only ST0 standing.

Next, when the control is shifted from task 1 to task 2,
ST0 is cleared because the set values of ch0 do not match. After that, task2 is E4, which is the stack and data area of task2.
Access 00 to E7FF (hex). Since ch1 matches and ST1 stands, ST0 is cleared and sf2 does not stand, so IE2
Is not set, and no interrupt occurs. After the processing of task2, the process returns to the OS and repeats task1.

However, when task 1 is executed (when ST0 = 1), t
When accessing the stack and data area of ask1 such as E000 to E3FF (hex), the amount of data to be handled becomes larger than expected, for example, task1 continues to the original data area of E000 to E3FF (hex), and the stack and data of task2 The area E400 to E7FF (h
When ex) is accessed, it matches the value of ch1 and ST0 = 1, so sf2 is set, sf2 = 1 and IE2 = 1, and an interrupt occurs. At this time, since the write prohibition flag WE3 is set, even if iwre becomes 1 with respect to the memory areas E400 to E7FF (hex) when sf2 is set, wre is 0, so that the memory area E400 ~ E7FF (hex)
Is not rewritten.

In the interrupt processing routine, task1
It is possible to detect that an attempt has been made to write to the memory area for which access is prohibited in step 1, so that it is known that an error has occurred in the processing of task 1 and error processing can be executed. Also, ta
Since the stack and data area E400 to E7FF (hex) of sk2 are not broken, it is possible to resume execution from task2 after error processing.

According to the present invention, runaway is prevented beforehand, and after the error processing, the task next to the task that caused the error (in this case, tas
Since the execution can be resumed from k2), the microcomputer system can be restored immediately after the occurrence of the abnormality, and the reliability of the microcomputer system can be secured.

[0097]

According to the present invention, there are provided a register capable of designating a plurality of addresses of an interrupt occurrence factor, and a control means for controlling permission of writing / reading of the matched address when the addresses match and an interrupt occurs. So
Erroneous data writing to the memory, which is one cause of runaway, can be prevented, and an interrupt process can be generated immediately after an erroneous write attempt to prevent runaway.

Further, the address is always monitored irrespective of the operation mode of the CPU, and the data protection of the storage device and the generation of an interrupt are controlled by matching the address with the contents of the register provided according to the present invention. The memory management function can be realized without changing the architecture.

Therefore, it is not necessary to change the core part of the existing CPU by adding a small amount of logic, and it can be easily embedded as a part of the one-chip microcomputer. In addition, it is possible to increase the reliability of the microcomputer system while suppressing an increase in the development period.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a configuration of a conventional one-chip microcomputer, that is, a one-chip microcontroller.

FIG. 2 is a block diagram showing the configuration of a first embodiment of a one-chip microcomputer incorporating an interrupt control circuit according to the present invention.

FIG. 3 is a block diagram illustrating a circuit configuration of an embodiment of an interrupt control circuit according to the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of a control register 7, a flag register 9, and mask registers 3 and 4 in the interrupt control circuit according to the first embodiment.

FIG. 5 shows a verilog-HDL (IEEE S) of the control circuit 8 of the first embodiment.
[td1364] It is a figure showing an example of description.

FIG. 6 shows verilog-H of the interrupt generation circuit 10 according to the first embodiment.
FIG. 4 is a diagram illustrating an example of a DL (IEEE Std1364) description.

FIG. 7 is a diagram showing a memory map of a program to which the first embodiment is applied and a control procedure thereof.

FIG. 8 is a diagram illustrating an example of a configuration of a control register 7 and a flag register 9 in the interrupt control circuit according to the second embodiment.

FIG. 9 shows a verilog-HDL (IEEE Std) of the control circuit 8 according to the second embodiment.
Fig. d1364) is a diagram illustrating an example of the description.

FIG. 10 shows a verilog of the interrupt generation circuit 10 according to the second embodiment.
FIG. 18 is a diagram illustrating an example of an HDL (IEEE Std1364) description.

FIG. 11 is a diagram showing a memory map of a program to which the second embodiment is applied and a control procedure thereof.

[Explanation of symbols]

 1 Channel 0 Address Register 2 Channel 1 Address Register 3 Channel 0 Mask Register 4 Channel 1 Mask Register 5 Channel 0 Comparator 6 Channel 1 Comparator 7 Control Register 8 Control Circuit 9 Flag Register 10 Interrupt Generation Circuit 21 CPU 22 I / O Port 23 ROM 24 RAM 25 Watchdog timer 26 Address bus 27 Data bus 28 Write / read control signal 69 Interrupt control circuit 70 Write / read control signal 71 Interrupt request signal 72 OR circuit 73 Interrupt flag signal

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Takehiko Yamashita 3-1-1 Kochi-cho, Hitachi-shi, Ibaraki F-term in Hitachi Plant, Hitachi, Ltd. (Reference) 5B017 AA02 BA01 BB03 CA01 CA13 5B042 GA13 GB08 JJ06 JJ13 JJ41 KK01 KK04 5B062 AA08 AA10 DD10 JJ03

Claims (8)

[Claims] An address register that specifies an address that causes an interrupt; a match detection unit that detects a match between the address that causes the interrupt and an address specified by a CPU; A control register for setting an interrupt condition to the CPU; and when the match is detected, outputting a write / read control signal to / from the memory based on the contents of the control register, and an interrupt request signal to the CPU. Control means for controlling the occurrence of the interrupt. 2. The interrupt control circuit according to claim 1, further comprising a mask register for masking a part of an address specified by said address register. 3. The interrupt control circuit according to claim 1, wherein a plurality of pairs of the address register and the coincidence detecting unit or a plurality of pairs of the address register, the mask register and the coincidence detecting unit are provided. An interrupt control circuit characterized in that: 4. The interrupt control circuit according to claim 3, wherein said control means is a control means for permitting the occurrence of an interrupt in accordance with the order of coincidence of a plurality of designated interrupt occurrence addresses. circuit. 5. An I / O for exchanging data with an external circuit.
O port, CPU, and ROM for storing programs
And a writable / readable RAM for temporarily recording the calculation results and data, and resetting the microcontroller in response to an overflow of the counter value, or
In a microcontroller having a watchdog timer that generates an interrupt to a PU, an address register that specifies an address that causes an interrupt, and a match that detects a match between the address that causes the interrupt and the address specified by the CPU Detecting means, write / read conditions of the RAM, and the CPU
A control register for setting an interrupt condition to the CPU; and, when the match is detected, outputting a write / read control signal to / from the RAM based on the contents of the control register, and outputting an interrupt request signal to the CPU. Control means for controlling generation. 6. The microcontroller according to claim 5, further comprising a mask register for masking a part of an address specified by the address register. 7. The microcontroller according to claim 5, wherein a plurality of sets of the address register and the match detecting means or a plurality of sets of the address register, the mask register and the match detecting means are provided. Characterized microcontroller. 8. The microcontroller according to claim 7, wherein the control means is a control means for permitting the occurrence of an interrupt in accordance with the order of coincidence of a plurality of designated interrupt occurrence addresses.