JP2001041998A - Performance testing device and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test the performance of a light emitting element array head. SOLUTION: A controller 106 controls a gate selector 108, steadily supplies total none light emission data for an image data processing part 104, and in the state of low current consumption without light emission current, communicates with a power supply part 103 to detect the amount of current supplied for an SLED head. Then the detected current value is compared with a predetermined threshold value, and 'a tendency to degrade in the SLED chip detected' is displayed on a display panel 107 in the case that the detected current value exceeds the predetermined threshold value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for testing the performance of a light emitting element array head, and more particularly to an image forming apparatus capable of performing a performance test of a light emitting element array head.

[0002]

2. Description of the Related Art Conventionally, SLEDs (self-scanning LED arrays) have been disclosed in Japanese Patent Application Laid-Open Nos. 1-238962, 2-206867 and 2-212170.
JP-A-3-20457, JP-A-3-19497, JP-A-4-5872, JP-A-4-23367, JP-A-4-296579, and JP-A-5-8497
No. 1 and a proposal of a light emitting element array for an optical printer integrating a Japan Hard Copy '91 (A-17) drive circuit,
The Institute of Electronics, Information and Communication Engineers ('90 .3.5) has been introduced in the proposal of a self-scanning light emitting device (SLED) using a PNPN thyristor structure and the like, and the SLED is receiving attention as a recording light emitting device.

The configuration of such an SLED is as shown in FIG. 6. In FIG. 6, VGA is a power supply voltage of the SLED, and is connected to a diode cascaded to φS via a resistor R. Have been. SLED
As shown in FIG. 6, a thyristor for transfer is arranged in an array and a thyristor for light emission is arranged in an array. The gate signal of each thyristor is connected to the first thyristor. Is connected to the signal input section of φS. The gate of the second thyristor is connected to the cathode of the diode connected to the terminal of φS, the third thyristor is connected to the cathode of the next diode,
… It is configured as follows.

Next, an operation of the SLED when all the elements are turned on will be described with reference to a timing chart of FIG.
The transfer starts by changing φS from 0V to 5V. When φS becomes 5V, Va = 5V, Vb = 3.7V
(The forward voltage drop of the diode is assumed to be 1.3 V), V
c = 2.4 V, Vd = 1.1 V, and 0 V after Ve
And the gate signals of the transfer thyristors ST1 and ST2 change from 0V to 5V and 3.7V, respectively.

In this state, when φ1 changes from 5V to 0V, the potential of the transfer thyristor in ST1 is such that the anode potential is 5V, the cathode potential is 0V, and the gate potential is 3.7.
V, the thyristor is turned on, and the transfer thyristor ST1 is turned on. In this state, φS is set to 0V
Thyristor ST1 is ON,
a ≒ 5 V (when the thyristor is turned on, the potential between the anode and the gate becomes substantially equal). Therefore, φS
Is 0 V, the ON condition of the first thyristor is maintained, and the first shift operation is completed.

In this state, when the φ1 signal for the light-emitting thyristor changes from 5 V to 0 V, the condition becomes the same as the condition when the transfer thyristor is turned on, and the light-emitting thyristor SL1 is turned on.
Then, the first LED is turned on. By returning φ1 to 5 V in the first LED, the potential difference between the anode and the cathode of the light emitting thyristor disappears, and the minimum holding current of the thyristor cannot flow, so that the light emitting thyristor SL1 is turned off.

Next, thyristor ST1 to thyristor S
The transfer of the thyristor ON condition at T2 will be described.
Even if the light-emitting thyristor ST1 is turned off, the transfer thyristor ST1 remains on because φ1 remains at 0 V, and therefore, the gate voltage Va of the transfer thyristor ST1 is kept.
≒ 5V and Vb = 3.7V.

In this state, when φ2 is changed from 5V to 0V, the transfer thyristor ST2 causes the anode potential to become 5V.
V, the cathode potential becomes 0 V, the gate potential becomes 3.7 V, and the transfer thyristor ST2 is turned on. Then, after the transfer thyristor ST2 is turned on, φ1 changes from 0 V to 5
When the voltage changes to V, the transfer thyristor ST1 is turned off in the same manner as the light-emitting thyristor SL1 is turned off.
The ON state of the transfer thyristor shifts from the thyristor ST1 to the thyristor ST2. When φ1 is changed from 5V to 0V, the light emitting thyristor SL2 is turned on to emit light.

Note that only the light-emitting thyristor that is ON is emitted by the transfer thyristor when the transfer thyristor is not ON, except that the gate voltage is 0 V except for the thyristor adjacent to the ON thyristor. Therefore, the ON condition of the thyristor is not satisfied, and the thyristor for light emission is turned ON also for the adjacent thyristor, so that φ1
Is 3.4 V (a forward voltage drop of the light-emitting thyristor), and the adjacent thyristor cannot be turned on because there is no potential difference between the gate and the cathode.

In the above, an example has been described in which the light emitting thyristor is turned on and light is emitted by setting φI to 0 V. In an actual printing operation, it is naturally determined whether or not the light is actually emitted at that timing. It is necessary to control according to the data.

As such image data, there is the image data φD shown in FIG. 7, and the φI terminal of the SLED externally takes the logical sum of φI and the image signal, and the image data becomes 0.
Only in the case of V, the φLED terminal of the SLED actually emits light at 0 V, and when the image data is 5 V, the φI terminal of the SLED remains at 5 V so as not to emit light.

FIG. 8 shows an example of mounting an SLED array. An SLED semiconductor chip 811 is mounted on the base substrate 812, and a printed wiring board made of a glass epoxy material, a ceramic material, or the like is used as the base substrate 812. A connector 813, a power supply circuit 810, and a lighting control circuit (driver IC (integrated c.
ircuit) 814 is provided. Via a connector 813, a control signal and power are received from outside. The power supply circuit 810 is connected to a power supply circuit 819 via a power supply cable 818, and supplies power to the array head. The lighting control circuit 814 receives a control signal from the outside and generates a lighting control signal for the SLED semiconductor chip.

The output signal φ1 from the driver IC 814,
φ2, φS, φI, and the negative-side power supply input (ground in this example) are connected to the SLED semiconductor chip by bonding wires 815, respectively.

On the base substrate 812, a positive electrode side power supply pattern (+ 5V in this example) 816 is drawn. The positive side power supply pattern 816 drawn on the base substrate is an SLED
Adhesively fixed with the back electrode of the semiconductor chip and silver paste,
Electrical conductivity is taken.

Such an SLED array head has a CC
It is used as an optical writing device in an image forming apparatus including an image reader unit including a D (charge coupled device) sensor and the like, and a printer unit that forms an image by an electrophotographic method based on image data from the image reader unit. That is, the photosensitive drum is primarily charged by a charger, an electrostatic latent image is formed on the photosensitive drum by an SLED array head based on image data, and the electrostatic latent image is developed by a developing device to form a toner image. The image is transferred to a recording medium by a transfer device.

[0016]

(Wiring failure in SLED chip) In such an SLED array, it is necessary to send a large number of control electric signals to control the light emitting operation of each chip. In the area, many dense and fine pattern wirings and structures are laid by lithography technology.

In such a case, of course, the (reverse) withstand voltage performance of each PN junction and the inner insulating film due to lithography wiring failure due to dust and impurity contamination and sudden high voltage electrostatic breakdown (electrostatic breakdown) after lithography formation. Deterioration occurs.

(Conventional Method for Avoiding SLED Wiring Failure) SL
If the ED wiring is a plane pattern, there is a method to remove wiring defects by careful visual judgment with a microscope,
Deterioration of the withstand voltage performance in the interlayer portion of the chip is difficult to find by this determination. Therefore, conventionally, the light emission operation is actually performed, and the light emission luminance and the light emission pattern are detected by a photodiode, a CCD, or the like in response to a designated input signal.
Wiring failure inspection has been performed by image analysis.

Next, this wiring defect inspection will be described with reference to FIG. First, a specific 1 is supplied to the lighting control circuit 814.
Set the control signal so that the bit turns on. The light from the lit one bit is guided to a translucent mirror 904 via a lens 902, and is split into a photodiode 903 and a CCD 901 by the translucent mirror 904. In this state, the current of the photodiode 903 is measured. This is performed for all bits and all SLED array chips 811. Next, a control signal is set so that all bits are turned on. In this state, the CCD 901 measures the light amount of each bit.
This is performed for all chips. As a result, it is possible to find all the chips that cannot obtain normal light emission and have at least wiring defects.

However, in the above-mentioned conventional example, detection was not possible unless there was a clear performance degradation in the light emitting operation. For example, even if there was considerable electrostatic damage in each post-assembly process and the precursor of the performance degradation appeared in the reverse leakage current characteristic of the PN junction, it could not be detected.

Even if it is determined that such a light emitting point does not cause any problem in the light emission amount confirmation test at the time of shipment, the deterioration of the PN junction rapidly proceeds, and the desired life performance may not be satisfied. .

In order to find such a defect, in the conventional method, aging by continuous operation for a long time is necessary in some cases, which is expensive in many points such as power consumption and space, and the throughput is high. It was low.

A first object of the present invention is to solve the above-mentioned problems and to provide a performance test apparatus capable of testing the performance of a light emitting element array head.

A second object of the present invention is to provide an image forming apparatus which can solve the above problems and can test the performance of a light emitting element array head.

[0025]

According to a first aspect of the present invention, there is provided a light emitting element array, and driving means for supplying a predetermined driving signal to a plurality of external terminals of the light emitting element array to sequentially drive constituent light emitting elements. A current measuring means for measuring the current consumption of the light emitting element array head by supplying all non-light emitting data to the plurality of external terminals in place of the drive signal, and Determining means for determining whether or not the performance of the light emitting element array head has deteriorated based on a result of comparing the current consumption value measured by the measuring means with the current consumption value in a normal state. .

According to the first aspect of the present invention, when the determination means determines that the performance of the light-emitting element array head has deteriorated, the display control means may display the fact.

In the first aspect, the light-emitting element constituting the light-emitting element array may be a light-emitting thyristor.

According to a third aspect of the present invention, the current measuring means can measure the current consumption without applying a signal to the gate of each light emitting thyristor and applying a predetermined bias voltage to the anode and the cathode.

According to a fifth aspect of the present invention, there is provided a light emitting element array head having a light emitting element array and driving means for supplying a predetermined driving signal to a plurality of external terminals of the light emitting element array to sequentially drive the constituent light emitting elements. Measuring means for measuring a resistance value between a power supply terminal, a ground terminal, and the plurality of external terminals of the light emitting element array, and each of the resistance values measured by the measuring means and a normal value. And determining means for comparing the resistance value with the corresponding resistance value to determine whether a low-life element exists in the light-emitting element array head.

According to a fifth aspect of the present invention, when the determination means determines that the light emitting element array head has the electrostatic breakdown, the display control means may display the fact.

In claim 5, the measuring means may have a storing means for storing the resistance value obtained by the measurement.

In the fifth aspect, the light-emitting element constituting the light-emitting element array may be a light-emitting thyristor.

According to a ninth aspect of the present invention, there is provided a performance test apparatus according to any one of the first to fourth aspects.

According to a tenth aspect of the present invention, there is provided the performance test apparatus according to any one of the fifth to eighth aspects.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
An embodiment will be described. In FIG. 1, reference numeral 100 denotes a printer unit of the image forming apparatus. 101 is an SLED chip. An array is constituted by a plurality of SLED chips 101. Reference numeral 102 denotes an SLED drive circuit that drives each SLED chip 101. SLED drive circuit 102 and S
An SLED head is constituted by the array of the LED chips 101.

A power supply unit 103 supplies power to the SLED head and monitors the amount of current. 104
Denotes an image data processing unit which supplies image data to the SLED drive circuit 102. An image data receiving interface 105 supplies image data to the image data processing unit 104. 108, a gate selector for selecting an input to the image data processing unit 104; 107 is a display panel, SL
This is for displaying the replacement of the ED head and the like. 10
9 is a photosensitive drum.

Reference numeral 106 denotes a controller, which switches the gate selector 108 to the image data receiving interface 105 in the normal mode, and switches the gate selector 108 to the controller 106 in the service mode to reduce the performance degradation of the array of the SLED chip 101. The operation can be shifted to inspection. When the gate selector 108 is switched to the image data receiving interface 105 side, image data from a personal computer, a scanner, or the like is transferred to the image data receiving interface 105.
And the SLED via the image data processing unit 104
The SLED chip 101 is supplied to the driving circuit 102 and the SLED driving circuit 102 controls the driving of the SLED chip 101. When the SLED head emits light in accordance with the image data, a latent image is formed on the photosensitive drum 109.

Next, a method of testing the performance of an array including a plurality of SLED chips 101 will be described. Controller 10
6 controls the gate selector 108 to constantly supply all non-emission data to the image data processing unit 104, and communicates with the power supply unit 103 in a state of low current consumption with no emission current to send data to the SLED head. Detect the supply current. And
The detected current value is compared with a predetermined threshold value, and when the detected current value exceeds the predetermined threshold value, the display panel 107 displays “SLED
"Detection of chip deterioration tendency" is displayed, and the S
Prompt replacement of LED head.

When the detected current value exceeds a predetermined threshold value,
Degradation of the (reverse) withstand voltage performance of the PN junction in the SLED chip 101 starts to occur, and the five on-board pattern wirings of the signals φS, φI, φ1, φ2, and GND in the array of the SLED chip 101 and the substrate electrode 5V (back surface) 4), the leakage current gradually increases, and the total current consumption of the SLED head including the total current consumption of the SLED drive circuit 102 increases.

FIG. 2 shows an example of a temporal change of the power supply current amount detected by the above-described procedure. From FIG. 2, the current value is an appropriate value in the pre-shipment inspection, but the current value exceeds a predetermined threshold four months after the inspection date, and the SLED chip 101
It can be seen that some of the arrays suffered from performance degradation, and that the formed image was disturbed by the non-light-emitting points six months after the inspection date.

According to the image forming apparatus of the present embodiment, since an abnormality can be found four months after the inspection date before shipment, the SLED head can be replaced in advance. Troubles can be avoided.

<Second Embodiment> FIG. 3 shows a second embodiment of the present invention.
An embodiment will be described. This is an example of an image forming apparatus,
An SLED chip array 300 is provided in a printer section of the image forming apparatus.
To 5 chips of φS, φI, φ1, φ2, GND
There are three pattern wirings on the substrate, and 5 V is taken from the back surface as the substrate electrode, and there are six wirings in total. Although the SLED chips are actually repeatedly arranged on the array, FIG. 3 shows only one SLED chip for simplification of the drawing.

This image forming apparatus has a ROM (read only)
memory) 306 and RAM (random access memory) 3
05 and a CPU (central processing unit) 303
, Video interface 307, and resistance measuring unit 302
And the decoder 304 are interconnected via a system bus. A display 308 is connected to the video interface 307.

The ROM 306 stores a control program. The CPU 303 controls each unit of the image forming apparatus according to a control program in the ROM 306. The RAM 305 is used as a work area of the CPU 303.

The decoder 304 decodes a control signal for controlling the relay array 301. The relay array 301 closes one of the relays constituting the relay array in accordance with the result of decoding by the decoder 304, and outputs the signals φS, φI, φ1, φ2, GND
One of the five on-substrate wirings is selectively made conductive and connected to the resistance measuring unit 302. Resistance measurement unit 302
Is to measure a resistance value between five on-substrate pattern wirings of φS, φI, φ1, φ2, and GND and a substrate electrode.

Next, a performance test method will be described. ROM3
In accordance with the control program 06, the CPU 303
When a relay control signal for sequentially turning on the relays for the pattern wirings on the substrate of φI, φ1, φ2, φS, and GND is generated, the φI, φ1, φ2, φS of the relay array 301 are determined based on the decoding result of the decoder 304. , G
Relays for pattern wiring on ND board are sequentially turned on
The pattern wirings on the substrate of φI, φ1, φ2, φS, and GND are sequentially connected to the resistance measuring unit 302. Then, the resistance value between the on-substrate pattern wiring connected to the resistance measurement unit 302 and the substrate electrode is measured by the resistance measurement unit 302, and the measurement result is stored in the RAM 305 by the CPU 303. 5V substrate electrode, φI, φ1, φ2, φ
The pattern wiring on the substrate of S and GND is insulated by the OFF light emitting thyristor or the transfer thyristor, and the insulation resistance value of the light emitting thyristor or the transfer thyristor becomes several MΩ or more in a normal value.

When a series of measurements is completed, the CPU 303 sequentially compares the measurement result of the RAM 305 with the resistance value in a normal state, and determines whether or not there is resistance deterioration due to electrostatic destruction according to the comparison result. If an affirmative determination is made, the fact is displayed on the display 308.

A chip having a resistance value of less than 1 MΩ is considered as a chip having a tendency of resistance deterioration due to electrostatic breakdown.
It is determined to be G (no good).

FIG. 4 shows a performance test system capable of performing a performance test of an SLED chip before incorporating the SLED chip into an image forming apparatus. The surface of the SLED chip array 400 is electrode-wire-bonded with a flexible cable 406 for connecting to a driver substrate and a gold wire 405. For the pad 407 of the flexible cable, the needle electrode array 40 by the needle contact device
8 are contacted. In one operation, the needle contact device makes contact with all 336 electrodes in one chip and all 336 electrodes in all 56 chips, and the needles are provided with springs, respectively, and low contact resistance of 1Ω or less can be obtained.

A decoder 404 decodes a relay control signal from the personal computer 403. Reference numeral 401 denotes a relay array, which has φS, φI, φ1, φ2,
This is for selectively conducting one of the five GND wirings on the substrate and the multimeter 402. Reference numeral 402 denotes a multimeter, φS, φI, φ1, φ2, GND
The resistance value between the five on-board pattern wirings and the board electrodes is measured. A personal computer 403 generates a relay control signal, records a measurement result of the multimeter 402, and executes S based on the measurement result.
This is for judging the performance of the LED chip and displaying the judgment result.

Next, a performance test method will be described. First, SLE with flexible cable is attached to the needle contact device.
The D chip array is set, and the pads of the flexible cable are contacted with the needles of the needle electrode array 408. When the personal computer 403 generates a relay control signal for sequentially turning on the relays of the relay array 401 with respect to the pattern wiring on the substrate of φI, φ1, φ2, φS, and GND, based on the decoding result of the decoder 404, Relays for the φ1, φ2, φS, and GND pattern wiring on the substrate are sequentially turned on, and the φI, φ1, φ2, φS, and GND pattern wiring on the substrate are sequentially connected to the multimeter 402. Then, the resistance between the pattern wiring on the substrate connected to the multimeter 402 and the substrate electrode is measured by the multimeter 402, and the measurement result is transmitted to the personal computer 403.
Is stored in the memory. 5V substrate electrode, φI,
φ1, φ2, φS, GND pattern wiring on the board
It is insulated by the OFF light emitting thyristor or the transfer thyristor, and the insulation resistance value of the light emitting thyristor or the transfer thyristor becomes several MΩ or more in a normal value.

The measurement is automatically performed for all 280 pads for 5 chips per chip, and for all 56 chips.

When a series of measurements by the multimeter 402 is completed, the personal computer 403 sequentially compares the measurement result of the memory with the normal resistance value, and according to the comparison result, is there any resistance deterioration due to electrostatic destruction? It is determined whether or not the determination is affirmative. If the determination is affirmative, that fact is displayed on the display.

An SLED chip having a resistance value smaller than 1 MΩ is an SLED having a tendency of resistance deterioration due to electrostatic breakdown.
The chip is determined as NG (no good).

FIG. 5 shows an example of the measurement result. From FIG.
On the 21st chip, the φS wire (the 101st) showed a tendency of resistance deterioration, and on the 47th chip, all wires (φ
S, φ1, φ2, φI, GND, 231st to 235th)
, It can be seen that these resistance values are 1 MΩ or less. S of the 21st and 47th chips
The LED chip needs to be replaced with another SLED chip. After the chip replacement, the insulation resistance value is measured again in the same manner.

By performing such a performance test,
The SLED chip destroyed by the weak static electricity can be found up to the process including the wire bonding, and the SLED head can be repaired.

In this embodiment, the initial defect of the electrostatic breakdown can be easily found in a short time as compared with the conventional light-emitting instrument inspection.

[0059]

As described above, according to the present invention,
With the configuration described above, the performance of the light emitting element array head can be tested.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a measurement result according to the first embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is an external view showing a performance test system.

FIG. 5 is a diagram illustrating an example of a measurement result according to the second embodiment.

FIG. 6 is a circuit diagram showing an example of an SLED array drive control circuit.

FIG. 7 is a timing chart showing an example of the timing of a signal supplied to the SLED array drive control circuit of FIG. 6;

FIG. 8 is an external view showing an example of the external appearance of the SLED head.

FIG. 9 is an explanatory diagram for explaining a method of determining a wiring defect / operation defect of the SLED head of FIG. 8;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 printer unit 101 SLED chip 102 SLED drive circuit 103 power supply unit 104 image data processing unit 105 image data reception interface 106 controller 107 display panel 108 gate selector 109 photosensitive drum

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Mitsuo Shiraishi 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term in Canon Inc. (reference) 2G003 AA03 AA06 AB02 AF01 AF02 AF06 AH01 AH03 AH10

Claims (10)

[Claims] 1. A performance testing apparatus for a light emitting element array head, comprising: a light emitting element array; and driving means for supplying a predetermined driving signal to a plurality of external terminals of the light emitting element array to sequentially drive constituent light emitting elements. Current measuring means for supplying all non-emission data to the plurality of external terminals in place of the drive signal to measure current consumption of the light emitting element array head; A performance test device comprising: a determination unit configured to determine whether or not the performance of the light emitting element array head has deteriorated based on a result of comparison with a current consumption value at the time. 2. The performance test apparatus according to claim 1, further comprising a display control means for displaying, when the determination means determines that the performance of the light emitting element array head has deteriorated, a display to that effect. . 3. The performance test apparatus according to claim 1, wherein the light-emitting elements of the light-emitting element array are light-emitting thyristors. 4. The device according to claim 3, wherein the current measuring means does not input a signal to a gate of each of the light emitting thyristors,
A performance test device for measuring current consumption in a state where a predetermined bias voltage is applied to an anode and a cathode. 5. A performance testing apparatus for a light emitting element array head comprising: a light emitting element array; and driving means for supplying a predetermined driving signal to a plurality of external terminals of the light emitting element array to sequentially drive constituent light emitting elements. Measuring means for measuring a resistance value between a power supply terminal, a ground terminal, and the plurality of external terminals of the light emitting element array; each resistance value measured by the measuring means and each corresponding resistance in a normal state A performance test apparatus comprising: a determination unit that determines whether a low-life element exists in the light-emitting element array head by comparing the value with a value. 6. A performance test according to claim 5, further comprising display control means for displaying, when the judgment means judges that the light emitting element array head has electrostatic breakdown, a display to that effect. apparatus. 7. A performance test apparatus according to claim 5, wherein said measuring means has a storing means for storing a resistance value obtained by the measurement. 8. The performance test apparatus according to claim 5, wherein the light-emitting elements of the light-emitting element array are light-emitting thyristors. 9. An image forming apparatus comprising the performance test apparatus according to claim 1. Description: 10. An image forming apparatus comprising the performance test apparatus according to claim 5.