JP2001037258A - Inverter unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently charge the capacitor of a charge pump circuit, even when a load is driven with a low frequency. SOLUTION: A commutation control circuit 31 outputs drive signals DUP to DWN by 120 deg. conduction system, according to the rotor position of a brushless motor 19 and a speed command signal Sf. A delay circuit 32 blocks the drive signals DUP to DWN making a delay signal Sd an L signal, for a specified time after a change of an operation command signal St from L (stop) to H (operation). A charging control circuit 33 generates a charging signal Sg of a pulse-train-like signal, having a uniform width and the same period as a carrier signal Sc, and this is logically synthesized with the driving signals DUP to DWN to obtain driving FUP to FWN. Since IGBTs 9 to 11 are turned on according to the charging signal Sg, sufficient charging of capacitors 27a to 29a of a power source is always feasible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an inverter device having charge pump means for generating a power supply voltage for driving a switching element.

[0002]

2. Description of the Related Art In an inverter device of this type in which a positive switching element and a negative switching element are bridge-connected between a positive DC power supply line and a negative DC power supply line, for example, One common drive power supply is provided to drive the negative switching element. Then, a charge pump circuit serving as a charge pump means charges a capacitor (hereinafter, referred to as a power supply capacitor) serving as a driving power supply for driving the positive-side switching element based on the common driving power supply. In particular,
The positive terminal of the common driving power supply is connected to one terminal of the power supply capacitor via the anode and the cathode of the charging diode, and the other terminal of the power supply capacitor is shared by the positive side switching element and the negative side switching element. Connected to the connection point (output terminal).

In this configuration, when the negative switching element is turned on (the positive switching element is turned off), the output terminal becomes almost 0 V, and the power supply capacitor is charged from the common drive power supply through the charging diode. However, when the negative switching element is kept off, such as before the start of waveform output, charging is not performed and the power supply capacitor is in a low voltage state. It cannot be turned on. Regarding this point, in Japanese Patent Application Laid-Open No. Hei 4-21363,
A means is disclosed in which all negative switching elements are turned on once before starting waveform output and then waveform output is started.

[0004]

In the inverter device having the above-described configuration using the charge pump circuit, the power supply capacitor may be insufficiently charged not only before the waveform output is started but also during the waveform output. For example, when the three-phase inverter device drives the three-phase brushless motor in the 120 ° conduction mode, the negative switching element of each phase is one.
After being on for 20 °, it is off for 240 °. During this off period, the power supply capacitor may be able to be charged in response to the PWM off time, but basically, the power supply capacitor is not sufficiently charged.

Therefore, when the brushless motor is driven at a low speed (low frequency), or when the speed of the brushless motor is reduced due to a large load torque,
The off-period of the negative switching element becomes longer, and the power supply capacitor may be discharged during the off-period.
When the voltage of the power supply capacitor decreases due to the discharge, the positive side switching element cannot be sufficiently turned on.
As a result, the inverter output voltage cannot be obtained in accordance with the drive signal, or the drive characteristics of the motor (for example, the generated torque) can be reduced by turning on the positive side switching element in the active region.
And the positive side switching element is overheated. For these reasons, it has been difficult for a conventional inverter device using a charge pump circuit to drive a load such as a brushless motor at a low frequency.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a charge pump means for generating a power supply voltage for driving a positive-side switching element, in which a load is driven at a low frequency. An object of the present invention is to provide an inverter device that can generate a drive power supply voltage sufficient to drive a positive switching element even in such a case.

[0007]

According to a first aspect of the present invention, there is provided an inverter device comprising a positive switching element and a negative switching element disposed between a positive DC power supply line and a negative DC power supply line. A driving means for driving the positive-side switching element and the negative-side switching element; a commutation control means for controlling the driving means to supply a driving signal; and Charge pump means having a capacitor serving as a power supply for driving means of the side switching element and charging the capacitor during a period in which the negative side switching element is in an on state; and turning on the negative side switching element for a predetermined period every predetermined period. And charge control means.

According to this structure, the charging control means turns on the negative switching element for every predetermined period for a predetermined period regardless of the driving frequency and the driving method of the inverter device. Then, the capacitor is charged via the negative switching element, and the charged voltage of the capacitor does not decrease even when the inverter device is driven at a low frequency. Thereby, the positive side switching element can always be sufficiently turned on, and it is possible to prevent the output voltage of the inverter device from decreasing and the positive side switching element from being overheated.

In this case, it is preferable that the charging control means include a delay means for enabling control of the commutation control means at least after a predetermined time has elapsed from the start of the ON operation of the negative switching element. ). According to this configuration, before the commutation control unit outputs the drive signal and the switching unit starts the switching operation, the charging control unit sets the negative switching element for at least a predetermined time while the positive switching element is turned off. Is kept on for a predetermined period every predetermined period, during which time the capacitor is sufficiently charged. As a result, the switching means can output a voltage as instructed from the start of the operation, and can prevent overheating of the positive switching element.

It is preferable that the charge control means controls the time width of the predetermined period for turning on the negative switching element so as to be substantially proportional to the predetermined period. According to this configuration, even when the setting of the predetermined cycle or the predetermined period is changed, the ON time of the negative switching element per unit time is almost constant, so that the capacitor can be charged. Insufficient or useless charging periods are not secured.

Further, the charge control means is configured so that all the negative switching elements are turned on during the same period with respect to charge control, so that the same charge is applied to a plurality of negative switching elements. Since the control signal can be used, the configuration can be simplified.

In this case, the commutation control means is configured to perform PWM control of the switching means using the carrier signal, and the charging control means is configured to set the predetermined cycle equal to the cycle of the carrier signal. (Claim 5).

[0013] According to this configuration, the charge control means can use the carrier signal of the PWM control to generate the predetermined cycle, and there is no need to provide a separate signal generation circuit or the like. Further, it is possible to synchronize the PWM waveform by the PWM control with the drive waveform of the negative switching element of the charging control means, and to influence the output voltage waveform by driving the negative switching element for charging control. Can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a three-phase brushless motor is driven by using the inverter device of the present invention will be described below with reference to the drawings. In FIG.
The schematic electrical configuration of a three-phase inverter device is shown. In FIG. 1, a positive terminal and a negative terminal of a DC power supply 2 which is an input power supply of the inverter device 1 have a power supply line 3 (corresponding to a positive DC power supply line in the present invention) and a power supply line 4 (the present invention). , And an inverter main circuit 5 (corresponding to the switching means in the present invention) is connected between the power supply lines 3 and 4.

The inverter main circuit 5 includes six insulated gate type switching elements, for example, an N channel type IGB.
T6 to T11 and six freewheel diodes 12 to 17 connected in anti-parallel to the IGBTs 6 to 11, respectively, are connected in a three-phase bridge. Here, IGBTs 6 to 8 whose collectors are connected to power supply line 3 correspond to positive side switching elements, and IGBTs 9 to 11 whose emitters are connected to power supply line 4 correspond to negative side switching elements. In the following description, the positive side is referred to as an upper arm side, and the negative side is referred to as a lower arm side.

The U-phase, V-phase and W-phase of this inverter main circuit 5
The three-phase brushless motor 19 has stator windings 19u, 19u respectively connected to the output terminals 18u, 18v, 18w of the three phases.
v and 19w are connected. The brushless motor 19 serving as this load includes the stator windings 19u, 1
It is configured to include a stator (not shown) around which 9v and 19w are wound and a rotor (not shown) provided with permanent magnets.

The IGBTs 6 to 11 are provided with drive circuits 20 to 25 as drive means, respectively. These drive circuits 20 to 25 are composed of, for example, photocouplers, and their secondary sides operate using the emitters of the IGBTs 6 to 11 as reference potentials.
The drive circuits 20 to 25 insulate drive signals FUP to FWN, which will be described later, and convert the drive signals to appropriate gate drive voltage levels.
The signal is output to the gate terminals of T6 to T11.

Among the drive circuits 20 to 25, the drive circuits 23 to 25 on the lower arm side are directly supplied with a gate drive voltage from one drive power supply 26 provided in common. The drive power supply 26 has a negative terminal connected to the power supply line 4 and is configured to output a gate drive voltage large enough to drive the IGBTs 6 to 11.

On the other hand, the gate drive voltages supplied to the upper arm side drive circuits 20 to 22 are generated by charge pump circuits 27 to 29 as charge pump means. For example, UGB upper arm side IGB
The drive circuit 20 for driving T6 includes a capacitor 27a (hereinafter referred to as a power supply capacitor
7a) is connected, and a diode 27b is connected between the positive terminal of the drive power supply 26 and the positive terminal of the power supply capacitor 27a with the drive power supply 26 side as an anode. Similarly, charge pump circuits 28 and 29 also
Each of them comprises a power supply capacitor 28a and a diode 28b and a power supply capacitor 29a and a diode 29b.

A control circuit 30 for generating drive signals FUP to FWN for switching the inverter main circuit 5 comprises a commutation control circuit 31, a delay circuit 32, a charge control circuit 33, a gate block circuit 34 and the like. Have been.

For example, a commutation control circuit 31 mainly composed of a microcomputer (corresponding to a commutation control means in the present invention) is output from a position detector 19 a such as a Hall IC provided in the brushless motor 19. By inputting the position signals HU, HV, and HW, and performing a logical operation, the commutation time points (energization signals) of the IGBTs 6 to 11 using the 120 ° energization method are detected (see FIG. 5). Further, the commutation control circuit 31 includes the brushless motor 1
9 is internally provided with a speed control circuit and a PWM control circuit (neither is shown) in order to control the speed of the motor 9 in accordance with an external speed command signal Sf.

The PWM control circuit compares, for example, a triangular carrier signal Sc with a voltage command signal output from the speed control circuit, and outputs a PWM signal having a duty ratio of 0% to 100%. It has become. Then, the commutation control circuit 31 sends a drive signal D to the delay circuit 32 based on the energization signal and the PWM signal.
UP to DWN are output.

The delay circuit 32 as a delay means comprises a delay signal generation circuit 35 and AND circuits 36a to 36f. The delay signal generation circuit 35 changes the operation command signal St from the L level (stop command) to the H level (drive command).
Until the predetermined delay time Td elapses.
A high-level delay signal Sd is output, and the H-level delay signal Sd is output after the delay time Td has elapsed or while the operation command signal St is at the low level (see FIG. 6). This delay signal Sd is supplied to the AND circuit 36.
a to 36f are input to one of the input terminals.
Drive signals DUP to DWN are input to the other input terminals of the circuits 36a to 36f, respectively.

Charge control circuit 33 as charge control means
Are charging signal generation circuit 37, AND circuits 38a-38
c, OR circuits 38d to 38f, and a NOT circuit 39. The charge signal generation circuit 37 compares the above-described carrier signal Sc with the charge setting signal Se (see FIGS. 2 and 3) to generate a charge signal Sg synchronized with the carrier signal Sc, as described later in detail. Is to be generated. This charging signal Sg is supplied to the OR circuit 3
8d to 38f are input to one of the input terminals.
After the logic is inverted by the OT circuit 39, the AND circuits 38a to
38c is input to one of the input terminals. AND circuits 38a to 38c and OR circuit 3
The other input terminals 8d to 38f are connected to AND circuits 36a to 36c and 36d in the delay circuit 32, respectively.
To 36f are input.

The gate block circuit 34 includes an AND circuit 39
a to 39f. These AND circuits 39
The operation command signal St is input to one of the input terminals a to 39f, and the output signals of the AND circuits 38a to 38c and the OR circuits 38d to 38f are input to the other input terminals, respectively. I have. Drive signals FUP to F
Output terminals of these AND circuits 39a to 39f that output WN are connected to input terminals of the drive circuits 20 to 25, respectively. Here, a dead time is added to the drive signals FUP to FWN to prevent a short circuit between the upper and lower arms.

The delay circuit 32, the charge control circuit 33,
The gate block circuit 34 can be configured as hardware, or can be configured using the microcomputer that performs the function of the commutation control circuit 31.

Next, the operation when the inverter device 1 having the above configuration starts the brushless motor 19 will be described below. First, the operation of the commutation control circuit 31 is shown in FIG.
This will be described with reference to the timing chart shown in FIG. Position signals HU, HV, H output from position detector 19a
W corresponds to the rotational position of the rotor,
It is a rectangular wave having a phase difference of °. Commutation control circuit 31
Performs a logical operation on these position signals HU, HV, and HW to obtain a 120 ° width energization signal to turn on the IGBTs 6 to 11. The commutation control circuit 31 outputs the energization signal on the lower arm side as it is as drive signals DUN, DVN, DWN, and outputs a logical product signal of the energization signal on the upper arm side and the PWM signal as drive signals DUP, DVP, DWP. I do. FIGS. 5 to 7 show a case where the PWM signal has a duty ratio of 100%.

Next, referring to FIGS. 2 and 3 showing operation waveforms of the charge signal generation circuit 37 and FIGS. 6 and 7 showing timing charts at the time of starting, the generation of the charge signal Sg and the charge pump circuits 27 to 29 will be described. When a control power supply is applied to the control circuit 30, the charge signal generation circuit 37 inputs the carrier signal Sc having a constant voltage amplitude from the commutation control circuit 31, and a comparator (not shown) provided therein. , The carrier signal Sc
And a charge setting signal Se having a constant voltage value.
As a result, as shown in FIG. 2 and FIG. 3, the charging signal S is at the H level during the period when the carrier signal Sc is equal to or higher than the charging setting signal Se, and at the L level during the other periods.
g is obtained. This charging signal Sg is the carrier signal Sc
Is a train of pulse signals having a constant width equal to the period of the pulse signal.

While the charge signal Sg is at the H level, the outputs of the AND circuits 38a to 38c shown in FIG. 1 are at the L level, regardless of the levels of the drive signals DUN to DWN.
Outputs of the R circuits 38d to 38f become H level. When the operation command signal St is at the H level (operation command), the AND circuits 39a to 39 of the gate block circuit 34
f indicates that the gate is open, and as shown in FIGS. 6 and 7, the drive signals FUP to FWP on the upper arm side go low, the IGBTs 6 to 8 are turned off, and the drive signals FUN to FWN on the lower arm side. Becomes H level, and IGBTs 9 to 11 are turned on. In this state, the voltages at the output terminals 18u, 18v, 18w of the inverter main circuit 5 become almost the voltage (0 V) of the power supply line 4, so that the power supply capacitor 27a
29a are respectively connected to the drive power supply 26 and the diode 27.
By the charging current flowing through b to 29b, the charge is almost charged to the gate drive voltage of the drive power supply 26.

On the other hand, while the charge signal Sg is at the L level, the gates of the AND circuits 38a to 38c and the OR circuits 38d to 38f are opened based on the logic thereof, and these function simply as buffers. Therefore, when the operation command signal St is at the H level (operation command), the drive signals FUP to FWN are output from the commutation control circuit 31 except during a delay operation described later.
Are equal to the drive signals DUP to DWN output from the inverter, and the output voltage of the inverter main circuit 5 can be controlled in accordance with the voltage command signal.

When the operation command signal St is at the L level (stop command), regardless of the level of the charging signal Sg, the AND circuits 39a to 39-3 of the gate block circuit 34
Since 9f is in the gate closed state (gate block state), all of the drive signals FUP to FWN are at L level and the IGBT
6 to 11 are all turned off.

By the way, in the present configuration, the charging signal S
g is at the H level during the time when the power supply capacitors 27a to 27a-2
The charging time is set so that the charging time for the IGBTs 9 to 11 on the lower arm side to be turned on per unit time is at least a predetermined time, which is a time sufficient to charge the battery 9a. For example, there are cases where the frequency of the carrier signal Sc is variably set as shown in FIG. 2 or FIG. Even in this case, the charge signal generation circuit 37 outputs the carrier signal Sc having a constant voltage amplitude.
And the charge setting signal Se having a constant voltage value, the charge signal Sg is obtained, so that the charge time per unit time by the charge signal Sg remains unchanged. Specifically, FIG. 3 shows a state where the frequency of the carrier signal Sc is lower than that in FIG.
In, the cycle of each pulse signal constituting the charging signal Sg becomes longer, but the width (period) of each pulse signal increases in proportion thereto, so that the charging time per unit time does not change after all.

Next, the delay operation at the time of startup will be described with reference to FIG. As described above, during the period when the operation command signal St is at the L level (stop command), although the charging signal Sg is output, all of the IGBTs 6 to 11 are in the off state because they are in the gate block state. . Therefore, the power supply capacitors 27a to 29a are not charged and have a voltage lower than the gate drive voltage (0 V in FIG. 4). In this state, the operation command signal S
When t changes from the L level (stop command) to the H level (drive command), the delay signal Sd becomes the power supply capacitor 27a.
To a low level for a delay time Td sufficient to complete the initial charging of .about.29a, and blocks the drive signals DUP to DWN output from the commutation control circuit 31. During this delay period, the upper arm IGBTs 6 to 8 are not driven to be turned on, and only the lower arm IGBTs 9 to 11 are turned on in accordance with the above-described charging signal Sg, and the power supply capacitor 27
a to 29a are initially charged. 6 and 7
After the delay time Td has elapsed, the delay signal Sd goes high, and the drive signals DUP to DWN from the commutation control circuit 31 are sent to the charge control circuit 33 as they are.

As described above, according to the inverter device 1 of the present embodiment, charging synchronized with the drive signals DUP to DWN generated based on the rotor position and speed command signal Sf of the brushless motor 19 and the carrier signal Sc. Signal Sg
And the drive signals FUN to FWN obtained by logically synthesizing
Since T6 to T11 are driven, the IGBTs 9 to 11 on the lower arm side are turned on for a certain period or more for each cycle of the carrier signal Sc, and the power supply capacitors 27a to 29a constituting the charge pump circuits 27 to 29 are charged.

Thus, even when the brushless motor 19 is driven at a low speed in the 120 ° conduction mode or when the speed of the brushless motor 19 is reduced due to a large load torque, the power supply capacitor 27a
29a can be prevented from being insufficiently charged. As a result, the IGBTs 6 to 11 are reliably and sufficiently turned on, and in particular, it is possible to prevent the IGBTs 6 to 8 from overheating or operating in the unsaturated region. Further, the inverter main circuit 5 includes:
Since the operation is reliably performed according to the drive signals FUN to FWN, the drive characteristics (for example, generated torque) of the brushless motor 19 do not deteriorate even in the case of low-speed drive.

In this case, the charge signal Sg is the carrier signal S
c, the drive signal DUP
~ When the PWM waveform included in DWP is at L level (I
The point in time when the GBTs 6 to 8 are in the off state and the point in time when the charging signal Sg is at the H level (the point in time when the IGBTs 9 to 11 are in the on state) match. Therefore, in performing the voltage control by the PWM control, it is possible to minimize the influence of the charging control for turning on the lower arm IGBTs 9 to 11 at a constant cycle on the output voltage waveform of the inverter device 1 as much as possible.

Further, since the charging signal Sg is obtained by comparing the carrier signal Sc having a constant voltage amplitude with the charging setting signal Se having a constant voltage value, even if the frequency of the carrier signal Sc changes, a unit based on the charging signal Sg is obtained. The charging time per hour is constant. Since the fixed charging time is set to a time sufficient for charging the power supply capacitors 27a to 29a, it is possible to prevent insufficient charging or useless charging period.

Further, at the time of startup, the delay circuit 32 drives the drive signals DUP to DWN until a delay time Td sufficient to charge the power supply capacitors 27a to 29a elapses after the operation command is given. IGBT6-1 according to
1 operation is prohibited. As a result, it is possible to drive the IGBTs 6 to 8 sufficiently even immediately after startup.
It is possible to prevent start-up failure, overheating of the IGBTs 6 to 8, and the like.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. As the switching element, an insulated gate element is particularly desirable, and a MOS transistor or the like other than the IGBT may be used. Further, the inverter main circuit 5 is not limited to a three-phase configuration, and may be a single-phase inverter circuit or a general multi-phase inverter circuit.

The carrier signal Sc is not limited to a triangular wave but may be, for example, a sawtooth wave. Further, the charging signal Sg may be generated by using a signal generation circuit provided separately or a timer function provided in the microcomputer without using the carrier signal Sc. Further, the charging signal Sg is
It is good that the charging time per unit time is secured for a predetermined time or more, and the power supply capacitors 27a to 29a are set so as not to be insufficiently charged. Absent.

The load of the inverter device 1 is not limited to the brushless motor 19, but may be, for example, an induction motor, a synchronous motor, or a load other than the motor. In this case, the configuration of the commutation control circuit 31 may be appropriately changed according to the load.

[0042]

As described above, the inverter device of the present invention includes the charge pump means for charging the capacitor serving as the power source for the driving means of the positive switching element when the negative switching element is turned on. Are turned on for a predetermined period every predetermined period, so that even when the inverter device is driven at a low frequency, charging of the capacitor does not become insufficient. As a result, the positive switching element can always be sufficiently turned on, and it is possible to prevent the output voltage of the inverter device from decreasing and the positive switching element from being overheated against the drive signal.

[Brief description of the drawings]

FIG. 1 is an electrical configuration diagram of an inverter device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation of a charge signal generation circuit (part 1).

FIG. 3 is an explanatory diagram of the operation of the charge signal generation circuit (part 2).

FIG. 4 is a timing chart showing a delay operation at startup.

FIG. 5 is a timing chart showing a position signal and a drive signal generated by a commutation control circuit.

FIG. 6 is a timing chart showing signals of various parts of the inverter device.

FIG. 7 is a time enlarged view of the timing chart shown in FIG. 6;

[Explanation of symbols]

1 is an inverter device, 3 is a power line (positive DC power line),
4 is a power supply line (negative DC power supply line), 5 is an inverter main circuit (switching means), 6, 7, 8 are IGBTs (positive switching elements), 9, 10, 11 are IGBTs (negative switching elements), 20 to 25 are drive circuits (drive means); 27 to 29 are charge pump circuits (charge pump means); 27a to 29a are capacitors (drive means power supply); 31 is a commutation control circuit (commutation control means); Is a delay circuit (delay means), and 33 is a charge control circuit (charge control means).

Claims (5)

[Claims] 1. A switching means comprising a bridge connection of a positive switching element and a negative switching element between a positive DC power supply line and a negative DC power supply line; and the positive switching element and the negative switching element. A driving means for driving the driving means; a commutation control means for controlling a driving signal to be supplied to the driving means; and a capacitor serving as a power supply for a driving means for the positive switching element, wherein the negative switching element is turned on. An inverter device comprising: charge pump means for charging the capacitor during a period in a state; and charge control means for turning on the negative switching element for a predetermined period every predetermined period. 2. A device according to claim 1, further comprising delay means for enabling control of the commutation control means at least after a predetermined time has elapsed from the start of the ON operation of the negative switching element by the charge control means. 2. The inverter device according to 1. 3. The inverter according to claim 1, wherein the charging control means controls a time width of the predetermined period for turning on the negative switching element so as to be substantially proportional to the predetermined period. apparatus. 4. The inverter device according to claim 1, wherein the charge control unit turns on all the negative switching elements for the same period during the charge control. 5. The commutation control unit performs PWM control on the switching unit using a carrier signal, and the charging control unit sets the predetermined period for turning on the negative switching element to be equal to the period of the carrier signal. The inverter device according to claim 4, wherein: