JP2001036077A - Mos-type semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a MOS-type semiconductor device and its manufacture, in which a BPSG film is applied to an interlayer dielectric, and a faulty transmission of a lamp-annealing process chamber is restricted. SOLUTION: A gate electrode 15 is formed via a gate oxidized film 14 on a prescribed channel region 13 on a semiconductor substrate 11 enclosed with an element isolation oxide film 12, and a source/drain diffusion layer 16 is formed on the both-side substrates, and the gate electrode 15 is coated with dielectric 17. A BPSG film 18 embeds an undercut of at least the gate electrode 15 as the interlayer dielectric, and a cap oxide film 19 is formed thereon. There is formed a contact hole 20 selectively reaching the source/drain diffusion layer 16 via the BPSG film 18 on the cap oxide film 19, and a metal film 21 coming into contact with the source/drain diffusion layer 16 is connected to a metal wiring 22 on the cap oxide film 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog IC, and more particularly, to a MOS type semiconductor device requiring a threshold accuracy, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the progress of large-scale integration and miniaturization of semiconductor integrated circuits and the generalization of various portable devices on the market, analog IC products, especially operational amplifiers, include amplifiers, integrators, and active filters. Widely applied to circuits, etc.
The demand for miniaturization is also severe.

[0003] When miniaturizing operational amplifier products, it is very useful to configure the active element with a MOSFET because the circuit occupation area becomes smaller than that of a bipolar transistor.

[0004] A conventional method for manufacturing a MOSFET will be described below. After channel ion implantation is performed on a semiconductor substrate and surrounded by an element isolation insulating film, a gate oxide film is formed. Next, a predetermined gate electrode is patterned on the gate oxide film using a known lithography technique and etching technique. After that, source / drain diffusion layers are formed, and an interlayer insulating film covering the gate electrode is deposited. The interlayer insulating film is composed of a SOG (Spin On Glass) film (non-doped SiO ₂ film). Next, a curing process is performed to flatten and harden the interlayer insulating film (SOG film).

After that, a planarized interlayer insulating film (SO
A contact hole for exposing the substrate surface of the source / drain diffusion layer is formed in a predetermined region of the (G film), and a source / drain electrode is formed.

[0006]

SUMMARY OF THE INVENTION The above MOSF
In a method of manufacturing a semiconductor device including ET, application of forming a BPSG (Boron-phosphorus Silicate Glass) film as an interlayer insulating film has been considered.

[0007] The reason is that since the BPSG film contains P atoms and B atoms, the BPSG film has a trapping effect of alkali ions which causes a drift of the flat band voltage. Thus, the shift of the threshold voltage of the MOSFET can be reduced, which is advantageous for commercializing analog ICs such as operational amplifiers. Another reason for using a BPSG film is that the BPSG film is more excellent in flatness than using an SOG film.

[0008] Further, as the design rules are required to be reduced due to the downsizing of products, the area of the source / drain diffusion layers is also becoming smaller. Therefore, it is becoming difficult to obtain a contact margin. Accordingly, in order to cope with misalignment of the formation of the contact hole in the source / drain diffusion layer, a method of performing ion implantation again after the formation of the contact hole is adopted.

As a result, the source / drain diffusion layer is re-formed, and the region of the source / drain diffusion layer is surely exposed at the bottom of the contact hole. After performing the ion implantation again, rapid thermal annealing is performed to activate the source / drain diffusion layers. In that case, lamp annealing treatment is suitable.

However, when lamp annealing is performed after depositing a BPSG film, degassed gas (a gas containing B atoms and P atoms) from the BPSG film adheres to the inside of the processing chamber.

The above-mentioned processing chamber is a quartz chamber, and the gas is remarkably devitrified when it adheres to the inner wall of the chamber. As a result, there is a problem that the heat transfer efficiency is reduced due to the interruption of the light, and a rapid source / drain activation process cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a problem thereof is that even if a BPSG film is used as an interlayer insulating film, devitrification of a lamp annealing chamber is suppressed, and an appropriate MOSFET is configured for an operational amplifier. An object of the present invention is to provide a MOS type semiconductor device and a method of manufacturing the same.

[0013]

According to the present invention, there is provided a MOS type semiconductor device comprising: a gate electrode formed on a predetermined channel region on a semiconductor substrate surrounded by an element isolation region via a gate oxide film; A source / drain diffusion layer formed on the substrate with a region therebetween, a BPSG film formed on the substrate to fill at least a step of the gate electrode, and a cap oxide film formed on the BPSG film. And a metal wiring layer connected to the source / drain diffusion layers formed on the cap oxide film.

According to the method of manufacturing a MOS type semiconductor device of the present invention, a step of implanting channel ions into a predetermined channel region on a semiconductor substrate surrounded by element isolation regions and a step of forming a gate oxide film on the semiconductor substrate Patterning a predetermined gate electrode on the gate oxide film above the channel region; forming a source / drain diffusion layer on the substrate with the channel region interposed therebetween; and forming at least the gate on the substrate. Forming a BPSG film so as to fill a step of the electrode;
A cap step of forming an oxide film having a thickness of 100 nm or more on the film, and an annealing step of performing a lamp annealing treatment after the cap step are provided.

According to the present invention, by capping the BPSG film with an oxide film before the lamp annealing process,
During the lamp annealing, the degassed B atoms and P atoms are blocked by the oxide film and are prevented from being diffused outside.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing a structure of a main part of a MOSFET according to a basic embodiment of the present invention. An element isolation oxide film 12 composed of a LOCOS oxide film (an oxide film formed by selective oxidation) is formed on a semiconductor substrate 11. A gate oxide film 14 is formed on a predetermined channel region 13 on a semiconductor substrate surrounded by an isolation oxide film 12.
A gate electrode 15 is formed through the gate electrode. Source / drain diffusion layers 16 are formed on the substrate on both sides of the gate electrode 15 with a channel region 13 therebetween. Gate electrode 1
Reference numeral 5 is covered with an insulating film 17 such as an oxide film (or a nitride film).

BPSG (Boron-phosphorus Silicate Gl)
The ass) film 18 is formed as an interlayer insulating film so as to fill at least a step of the gate electrode 15. This BP
An oxide film (cap oxide film) 19 is formed on the SG film 18 as a cap material. A contact hole 20 is formed on the cap oxide film 19 to selectively reach the source / drain diffusion layer 16 via the BPSG film 18, and the contact hole 20 is filled with a metal film 21 contacting the source / drain diffusion layer 16. The metal wiring 22 on the cap oxide film 19 is connected.

According to the above embodiment, the cap oxide film 19 is formed on the BPSG film 18. This allows
B atoms and P atoms that are outgassed from the BPSG film 18 during the lamp annealing process are blocked by the cap oxide film 19 and diffusion to the outside is suppressed.

Also, a BPS containing a B atom and a P atom
The G film has an alkali ion trapping effect that drifts a flat band voltage that affects the shift of the threshold voltage of the MOSFET. Therefore, a highly reliable MOSFET that can be expected to reduce the threshold shift as an operational amplifier product can be configured.

FIGS. 2A to 2C are cross-sectional views sequentially showing main parts of a process relating to a method for manufacturing a MOSFET according to an embodiment of the present invention. The same parts as those in FIG. 1 are described with the same reference numerals.

First, as shown in FIG. 2A, a selective oxidation method (LOC) is formed on a semiconductor substrate 11 made of single crystal silicon.
The element isolation insulating film 12 is formed by the OS method. Next, channel ion implantation for obtaining a desired threshold is performed in a predetermined region of the substrate 11 surrounded by the element isolation insulating film 12 (13). After that, a gate oxide film 14 is formed on the substrate 11.

Next, as shown in FIG. 2B, for example, polysilicon is deposited on the gate oxide film 14 and a predetermined gate electrode 1 is formed using a lithography technique and an etching technique.
5 is patterned. Thereafter, source / drain diffusion layers 16 are formed by implanting impurity ions using the gate electrode 15 as a mask.

Next, as shown in FIG. 2C, an insulating film 17 made of an oxide film or a nitride film is formed by oxidizing or thermal nitriding again. After that, an annealing process is performed to activate the source / drain diffusion layers 16. This annealing treatment is achieved by lamp annealing, for example, 1
The process is performed at 040 ° C. for about 10 seconds.

After that, a BPSG film 18 is formed to fill the level difference of the gate electrode 15 and flatten it. This BPSG
Cure at the time of forming the film 18 is, for example, 900 ° C., 20 ° C.
This is performed on the order of minutes.

After flattening the BPSG film 18, an oxide film 19 for a cap is formed on the BPSG film 18 (cap oxide film 19). The cap oxide film 19 is effective when a subsequent lamp annealing process is added.

For example, as shown in the enlarged view of FIG.
When the contact hole 20 is formed on a predetermined region of the source / drain diffusion layer 16, the source / drain diffusion layer 1
6 may be misaligned. Therefore, ion implantation is performed again after the formation of the contact hole 20 (1).
6t). The source / drain re-formation ensures that the source / drain diffusion layer 16 is exposed at the bottom of the contact hole 20.

After performing the ion implantation again with the source / drain reformation, the source / drain diffusion layer 1 is formed.
In order to promote the activation of 6 (16t) again, rapid thermal annealing, that is, lamp annealing is performed.
The conditions are, for example, about 1040 ° C. and about 10 seconds.

At this time, most of the surface of the BPSG film 18 is covered with the cap oxide film 19. That is, BP
The exposed portion of the SG film 18 is only the side wall portion of the contact hole 20. For this reason, the amount of outgas from the BPSG film 18 during the lamp annealing process is very small. This is because B atoms and P atoms in outgassing are almost blocked by the cap oxide film 18.

That is, the cap oxide film 18 is 100 n
If m or more, B atoms and P atoms will not be transmitted during the time (about 10 seconds) during the lamp annealing process. As a result, devitrification of a quartz chamber (not shown) used in lamp annealing can be significantly reduced.

Thereafter, as shown in FIG. 1, the contact hole 20 is filled with a buried metal 21. After etching back the filled metal 21, the upper metal wiring is patterned to form source / drain electrodes (or wiring) 2.
2 are formed.

The source / drain electrode (or wiring)
The source / drain electrode (or wiring) 22 that contacts the bottom of the contact hole 20 without using the buried metal 21 may be configured without being limited to the above manufacturing method.

According to each of the above embodiments, lamp annealing can be easily performed even when a BPSG film is used as an interlayer insulating film in a semiconductor device including a MOSFET. That is, since the cap oxide film is formed on the BPSG film, the devitrification of the chamber during the lamp annealing can be suppressed. This is not limited to the re-formation of the source / drain region (16t) as shown in FIG.

The BPSG film, unlike the SOG film, does not require a step of evaporating moisture in the curing process. SO
In the case of the G film, a step of removing water at a predetermined temperature for a considerable period of time is required before hardening. The curing process can be accomplished in about half the time if there is no step.

In addition, as described above, the BPSG film containing B atoms and P atoms has a trapping effect of alkali ions that drifts a flat band voltage which affects the shift of the threshold voltage of the MOSFET. As a result, as an operational amplifier product, it is possible to easily manufacture a MOSFET expected to reduce the threshold shift with high reliability.

[0035]

As described above, according to the present invention,
By capping the BPSG film with an oxide film, the MOS
A problem in the manufacture of the FET, that is, promotion of devitrification of the chamber during lamp annealing can be suppressed. As a result, it is possible to easily realize a highly reliable MOSFET in which the threshold shift is suppressed as much as possible by applying the BPSG film to the interlayer insulating film, and to provide a MOS semiconductor device applicable to operational amplifier products and a method of manufacturing the same. be able to.

[Brief description of the drawings]

FIG. 1 shows a MOSFET according to a basic embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a configuration of a main part of FIG.

FIGS. 2A to 2C are cross-sectional views sequentially showing main parts of a process relating to a method for manufacturing a MOSFET according to an embodiment of the present invention.

FIG. 3 is an enlarged sectional view of a main part relating to the manufacture of the MOSFET, following FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate, 12 ... Element isolation insulating film, 13 ... Channel ion implantation area, 14 ... Gate oxide film, 15 ... Gate electrode, 16 ... Source / drain diffusion layer, 17 ... Insulating film, 18 ... BPSG film, 19 ... Cap oxide film, 20 ...
Contact holes, 21 embedded metal, 22 source / drain electrodes (or wiring).

Claims (3)

[Claims] A gate electrode formed on a predetermined channel region on a semiconductor substrate surrounded by an element isolation region via a gate oxide film; and a source electrode formed on the substrate with the channel region interposed therebetween.
A drain diffusion layer; a BPSG film formed on the substrate to fill at least a step of the gate electrode; a cap oxide film formed on the BPSG film; and the source formed on the cap oxide film And a metal wiring layer connected to the drain diffusion layer. A step of implanting a channel ion into a predetermined channel region on a semiconductor substrate surrounded by an isolation region; a step of forming a gate oxide film on the semiconductor substrate; and a step of forming a gate oxide film on the channel region. Patterning a predetermined gate electrode on the film, forming a source / drain diffusion layer on the substrate with the channel region interposed therebetween, and forming a BPSG film on the substrate so as to fill at least a step of the gate electrode. A MOS type semiconductor comprising: a forming step; a capping step of forming an oxide film having a thickness of 100 nm or more on the BPSG film; and an annealing step of performing a lamp annealing treatment after the capping step. Device manufacturing method. 3. A step of selectively forming a contact hole reaching the surface of the substrate including the source / drain diffusion layer between the capping step and the annealing step; 3. The method according to claim 2, further comprising an ion implantation step for expanding a region of the source / drain diffusion layer.