JP2001036035A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the most use of an inner wall face of a cylinder for increasing the capacity of a trench cylinder roughened surface capacitor by preventing a conductive layer near an opening of the cylinder against scraping in manufacturing processes. SOLUTION: A through-hole 8AK of a BPTEOS layer 8A is smaller than a through-hole 4AK of a SiN layer 4A and therefore an end part near the through-hole 8AK or peripheral part 8AT forms a hood structure for the through-hole 4AK. A storage node electrode 6A comprises a bottom face section 6AH and a sidewall section 6AV formed on a sidewall 4AW of the through hole 4AK in connection with an edge section 6AE1 of the bottom face section 6AH. The sidewall section 6AV is formed on the entire surface of the wall face 4AW, and an edge section 6AE2 on the opposite side from the edge section 6AE1 comes in contact with the hood section 8AT. During manufacturing processes, the silicon film 6A near the opening of a cylinder 1AK is protected by the hood section 8AT so that there is no scraping.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a technique for increasing the capacity of a capacitor included in a semiconductor memory.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration of devices, the chip size has been reduced, and it has become necessary to increase the capacity of semiconductor memories. 64MDRAM (Dynamic Rand
In om Access Memory, a method is used in which the surface of the storage node electrode is subjected to surface roughening treatment to increase the surface area of the electrode, thereby increasing the capacitance of the capacitor.

FIG. 27 is a longitudinal sectional view of a conventional semiconductor memory 100P. As shown in FIG. 27, the conventional semiconductor memory 100P is roughly divided into a MOS transistor 101 functioning as a transfer gate and a capacitor CP. The MOS transistor 101 includes a gate electrode 102 and two diffusion regions 103a and 103b. A polysilicon plug 1 is formed on one diffusion region 103b.
11b is formed, and the bit line 112 is formed on the plug 111b. Also, the other diffusion region 1
03a, a polysilicon plug 111a is formed on the contact hole 110 provided in the interlayer insulating film 110 covering the gate electrode 102 and the like.
Storage node electrode 6A of capacitor CP via K
It is in contact with P. In a silicon substrate 121, an element isolation oxide film 114, a P well 122, a bottom N well 123
Etc. are formed. Such a MOS transistor 101
Are formed by DRAM technology with a minimum dimension of 0.18 μm.

The capacitor CP of the semiconductor memory 100P
Has a so-called hollow cylindrical rough surface capacitor structure. More specifically, as shown in FIG. 27, a BPTEOS (Boro Phosp
ho Tetra Ethyle Ortho Silicate) Layer 4AP and TEO
S (Tetra Ethyle Ortho Silicate) layer (cap layer)
58AP has a cylindrical through hole (hereinafter, also referred to as a cylinder) 1P connected to the contact hole 110K. Then, a polysilicon film 6AP having a roughened surface is formed on a region that fills the inside of the contact hole 110K and extends from the inside of the contact hole 110K to the vicinity of the opening of the wall surface of the cylinder 1P. The silicon film 6AP forms a storage node electrode. Further, a capacitor dielectric film (not shown) is formed on the roughened surface of the silicon film 6AP, and is made of polysilicon so as to be in contact with the capacitor dielectric film and to fill the inside of the cylinder 1P. A cell plate electrode 36P is formed.

[0005] An interlayer insulating film 210 is formed on the cell plate electrode 36 P, and a wiring 212 is formed on the surface of the interlayer insulating film 210. In addition, the wiring 212
An interlayer insulating film 211 is formed so as to cover the wiring, and a wiring 213 is formed on the surface thereof.

Next, a method of manufacturing the conventional semiconductor memory 100P, particularly, a method of forming the storage node electrode 6AP of the capacitor CP will be described.

First, a silicon substrate 121 in which elements such as a MOS transistor 101 are formed and covered with an insulating film 110 is prepared. A contact hole 110K is formed in the interlayer insulating film 110, and the contact hole 110K is filled with polysilicon 56 (see FIG. 28).

Thereafter, as shown in FIG. 28, a BPTEOS layer 4BP (1.8 μm in thickness) is formed on the interlayer insulating film 110 by a normal pressure CVD method and annealed.
The TEOS layer 58BP (thickness 100) is formed on the TEOS layer 4BP.
Angstrom) is formed by a low pressure CVD method. Next, after photolithography, T
The EOS film 58BP and the BPTEOS4BP are dry-etched to form the cylinder 1P shown in FIG.

Then, after a doped amorphous silicon film and a non-doped amorphous silicon film are sequentially laminated, a surface temperature of 520 ° C. and a flow rate of disilane gas of 20 ° C.
A surface roughening process is performed under the conditions of sccm and a pressure inside the reaction furnace of 2 Torr to form a silicon film 6BP having polycrystalline grains as shown in FIG.

Next, a resist 50AP is applied on the exposed surface of the substrate in the state of FIG. 30 (see FIG. 31).
The entire surface of 0AP is exposed. At this time, resist 50AP
Is located far from the exposed surface of the resist 50AP, and is not exposed, and is left as a resist 50BP after development (see FIG. 32). Thereafter, in a dry etching apparatus, anisotropic etching is performed on the exposed surface of the substrate in the state of FIG. 32 using the resist 50BP as a mask. Thereby, as shown in FIG. 33, the portion of the silicon film 6BP that is not covered with the resist 50BP is removed, while the portion that is covered with the resist 50BP is left as the silicon film or the storage node electrode 6AP. After that, the resist 50BP is removed.

[0011]

According to the conventional method of forming a rough cylindrical capacitor having a rough surface, scattered light may enter the cylinder 1P when exposing the resist 50AP shown in FIG. In such a case, the resist 50AP near the opening of the cylinder 1P opposite to the silicon substrate 121 is developed, and the resist 50BP is left only in a region deeper than the vicinity of the opening. That is, as shown in FIG. 32, the silicon film 6BP in the cylinder 1P is a resist 50BP.
Not completely covered by. In the conventional manufacturing method, since the silicon film 6BP is subjected to anisotropic etching in this state, as shown in FIG. 33, after the etching, the silicon film 6BP is moved from the upper surface (upper end) of the opening to a range of about 1000 angstroms. No film is left (see the etched silicon film 6AP). Therefore, it cannot be said that the conventional capacitor CP makes full use of the shape of the cylinder 1P, and there is a problem that the capacitance is small by the absence of the storage node electrode near the opening.

Further, in the conventional manufacturing method, the capacitor C
Since the capacitance of P is greatly affected by the amount of the resist 50BP buried in the cylinder 1P and the amount of overetching of the silicon film 6BP, there is a problem that it is difficult to stably form a capacitor having a desired capacitance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a larger electrode area than a capacitor of a conventional semiconductor device by making the most of a predetermined wall surface on which an electrode is formed. It is an object to provide a semiconductor device having a capacitor and to provide a manufacturing method capable of stably and reliably manufacturing such a semiconductor device.

[0014]

(1) A semiconductor device according to the first aspect of the present invention is a semiconductor device having a capacitor, wherein the capacitor has a bottom portion and an edge portion of the bottom portion. Coupled, having a concave electrode composed of a side wall formed on a predetermined wall surface, the semiconductor device,
An eaves portion is provided, which is disposed in contact with an edge portion of the side wall portion opposite to the edge portion and extends to the central portion of the concave shape.

(2) The semiconductor device according to the second aspect of the present invention is the semiconductor device according to the first aspect, wherein the eave portion has a lower etching rate than a material forming the wall surface. It is characterized by being composed of a body.

(3) The semiconductor device according to the third aspect of the present invention is the semiconductor device according to the first aspect, wherein the eaves portion is the edge of the side wall portion opposite to the edge portion. And forming a part of the electrode by being coupled to a portion.

(4) The semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the wall surface is between the two edge portions of the side wall portion. And projecting toward the central portion of the concave shape.

(5) A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein a surface of the side wall portion opposite to the wall surface is rough. It is characterized by being surfaced.

(6) A method of manufacturing a semiconductor device according to a sixth aspect of the present invention is a method of manufacturing a semiconductor device having a capacitor, comprising: (a) at least a first dielectric layer having a recess. Forming a dielectric layer, (b) forming a conductive layer covering the dielectric layer, and (c) extending from the edge of the opening to the center of the opening in the opening of the recess. Forming an existing eaves portion, and (d) etching the conductive layer using a first mask that covers at least a portion of the conductive layer in the recess, and removing the remaining conductive layer. And a step of forming an electrode of the capacitor.

(7) The method of manufacturing a semiconductor device according to the invention of claim 7 is the method of manufacturing a semiconductor device of claim 6, wherein the first mask fills the recess. A resist is disposed so as to cover the entire conductive layer, the resist is exposed from the exposed surface side of the resist, and the resist is left after development.

(8) The method for manufacturing a semiconductor device according to the invention described in claim 8 is the method for manufacturing a semiconductor device according to claim 6 or 7, wherein in the step (a), the first dielectric is used. Forming a body layer and a second dielectric layer having an etching rate smaller than that of the first dielectric layer and forming the dielectric layer together with the first dielectric layer in this order; Forming the recess so as to penetrate a layer and reach into the first dielectric layer; and after the step (a), the step (c) is performed.
In the step (c), the first and second dielectric layers are subjected to isotropic etching to form the eaves portion composed of the second dielectric layer, and after the step (c), Step (b) is performed.

(9) The method of manufacturing a semiconductor device according to the ninth aspect of the present invention is the method of manufacturing a semiconductor device of the sixth or seventh aspect, wherein the step (b) comprises the step of (b-1) A) forming a first conductive layer covering the dielectric layer; and (b-2) forming a second portion of the first conductive layer except for the opening and its surroundings.
Covering with a mask, and (b-3) forming a second conductive layer that is in contact with the first conductive layer around the opening and forms the conductive layer together with the first conductive layer, In the step (c), the second mask and the second conductive layer on the second mask are removed.

(10) The method of manufacturing a semiconductor device according to the invention according to claim 10 is the method of manufacturing a semiconductor device according to any one of claims 6 to 9, wherein (e) the inner surface of the recess. The method further comprises a step of forming a protrusion on the upper part.

(11) The method for manufacturing a semiconductor device according to the invention described in claim 11 is the method for manufacturing a semiconductor device according to claim 10, wherein the step (e) comprises: In the step (a), a third dielectric layer made of a dielectric having a lower etching rate than the first dielectric layer is formed in the dielectric layer, and the third dielectric layer penetrates through the third dielectric layer. And (e-2) performing isotropic etching on the dielectric layer after the step (e-1).

(12) A method of manufacturing a semiconductor device according to the invention of claim 12 is the method of manufacturing a semiconductor device according to any of claims 6 to 11, wherein the step (b)
Wherein the exposed surface of the conductive layer is roughened.

(13) A semiconductor device according to a thirteenth aspect of the present invention is manufactured by the method of manufacturing a semiconductor device according to any one of the sixth to twelfth aspects.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A1. Configuration of Semiconductor Device FIG. 1 shows a schematic vertical sectional view of a semiconductor memory (for example, DRAM) 100A as a semiconductor device according to the first embodiment.

As shown in FIG. 1, the semiconductor memory 100A
Are roughly divided into MOs that function as transfer gates.
It comprises an S transistor 101 and a capacitor C1. The MOS transistor 101 has a silicon substrate 121
A gate electrode 102 formed thereon and covered with a sidewall spacer or a protective film 104; and an end near the lower end of each end of the gate electrode 102 in the surface of the silicon substrate 121, and moving away from the gate electrode 102. And two diffusion regions 103a and 103b extending in the direction. A plug 111b made of, for example, polysilicon is formed on one diffusion region 103b.
A bit line 112 is formed on 11b. A plug 111a made of, for example, polysilicon is formed on the other diffusion region 103a. The interlayer insulating film 110 includes a gate electrode 102, a protective film 104, and plugs 111a, 1
11b, which covers the bit line 112, the plug 111a is in contact with the storage node electrode or the lower electrode 6A which is the (one) electrode of the capacitor C1 in the contact hole 110K. In the silicon substrate 121, an element isolation or isolation oxide film 114, a P well 1
22, a bottom N well 123 and the like.

Next, in addition to FIG.
The capacitor C1, which is a feature of the semiconductor memory 100A, will be described with reference to FIG. As shown in FIGS. 1 and 2, BPTEOS (Boro) is formed on the surface of the interlayer insulating film 110 opposite to the silicon substrate 121.
Phospho Tetra Ethyle Ortho Silicate) layer (first dielectric layer) 4A composed of oxide (hereinafter simply referred to as “BPTEOS”) and layer (second dielectric substance) composed of silicon nitride (hereinafter also referred to as “SiN”) A dielectric layer 48A having a two-layer structure in which the layers 8A are stacked in this order is formed.

In particular, the BPTEOS layer 4A has a cylindrical or frustum-shaped through hole 4AK formed in its thickness direction, and similarly, the SiN layer 8A has a through hole 8AK formed therein. At this time, the through holes 4AK and 8AK and the contact hole 110K are formed side by side in a direction perpendicular to the surface of the silicon substrate 121. In particular, the edge of the through hole 8AK of the SiN layer 8A is aligned with the through hole 4AK of the BPTEOS layer 4A.
Is surrounded by the edge at the end on the side of the SiN layer 8A, and the through-hole 8A
The end or the periphery 8AT near K forms an eave structure with respect to the through hole 4AK. In the following description,
The end portion or the peripheral portion 8AT is also referred to as an “eave portion 8AT”.

The through hole composed of the through holes 4AK and 8AK is also called "cylinder 1AK". At this time, the cylinder 1AK is S
The iN layer 8A has a concave shape with respect to the surface on the side opposite to the BPTEOS layer 4A. For example, through holes 8AK, 4A
K can be formed in the shape of a cylinder or a truncated cone.

Then, the surface of the interlayer insulating film 110 which is in contact with the plug 111a and continues to the contact hole 110K and B
Wall surface 4A of PTEOS layer 4A (or through hole 4AK)
A silicon film forming the storage node electrode 6A, for example, a polysilicon film is formed so as to be in contact with the entire surface of W (for this reason, the "silicon film 6A" is denoted by the same reference numeral).
Also called). Specifically, the storage node electrode 6A is
Bottom portion 6AH substantially perpendicular to wall surface 4AW of through hole 4AK
And a side wall portion 6AV formed on the wall surface 4AW and connected to the edge portion 6AE1 of the bottom surface portion 6AH. The edge 6AE1 has a bottom surface 6AH and a side wall 6A.
Shared with AV. In particular, the side wall 6AV is a wall 4A.
The edge 6AE2 of the side wall 6AV opposite to the edge 6AE1 is formed on the entire surface of W.
Contacting AT. The surface 6AVS of the side wall 6AV opposite to the wall surface 4AW and the surface 6AHS of the bottom surface 6AH following the surface 6AVS, that is, the surface 6AS facing the inside of the through hole 4AK of the silicon film 6A are roughened. I have. Due to the increase in the surface area due to the roughening, the capacitance of the capacitor C1 is larger than that of the capacitor whose surface is not roughened, so that the semiconductor memory 100A can realize a higher memory operation.

Further, a capacitor dielectric film 10 such as a silicon nitride film, a silicon oxide film or a silicon oxynitride film is formed on at least the surface 6AS of the silicon film 6A. A conductive film material such as polysilicon is disposed so as to be in contact with the capacitor dielectric film 10 to fill the inside of the cylinder 1AK, and the silicon or the like is a cell plate electrode or the other electrode of the capacitor C1. An upper electrode 36 is formed.

An interlayer insulating film 210 is formed on the cell plate electrode 36, and a wiring 212 made of a conductive material such as aluminum is formed on the surface of the interlayer insulating film 210 opposite to the silicon substrate 121. I have. Also,
An interlayer insulating film 211 is formed on interlayer insulating film 210 so as to cover wiring 212, and similar wiring 2 is formed on the surface thereof.
13 are formed.

As can be seen by comparing FIGS. 1 and 2 with FIG. 27 described above, the conventional capacitor CP does not have the silicon film 6AP near the opening on the opposite side of the silicon substrate 121 of the cylinder 1P. On the other hand, in the capacitor C1 according to the first embodiment, the silicon film or the side wall portion 6AV of the storage node electrode 6A is in contact with the eave portion 8AT,
A silicon film 6A is formed on the entire surface of the wall surface 4AW. That is, the capacitor C1 has a capacity that makes maximum use of the surface area of the wall surface 4AW. Therefore, according to the capacitor C1 according to the first embodiment, the conventional capacitor C1
A capacity larger than P can be obtained. As a result, the semiconductor memory 100A can achieve a highly reliable operation in which a memory operation problem that may occur because the semiconductor memory 100A does not have a sufficient capacity is eliminated.

B1. Next, a method for manufacturing the semiconductor memory 100A will be described. As described above, the semiconductor memory 100A has the capacitor C
Since the configuration of the first embodiment, particularly the configuration of the storage node electrode 6A, is characterized, the description will be focused on the method of forming the storage node electrode 6A.

Step B1-1. First, a substrate for forming the capacitor C1 is prepared. Here, the silicon substrate 121 in the state shown in FIG.
A substrate is prepared on which elements such as the OS transistor 101, an interlayer insulating film 110 having a contact hole 110K, and a plug 56 formed in the contact hole 110K and forming a part of the silicon film 6A later. For example, silicon can be used as the material of the plug 56, and in particular, polysilicon can be used. Since the substrate in such a state varies depending on the standard and design of the semiconductor memory, the detailed description of the manufacturing method is omitted, but the substrate can be manufactured using a well-known film forming technique, patterning technique, or the like.

Step B1-2. Step of Forming Dielectric Layer On the exposed surface of the substrate in the state shown in FIG. 3, BPTEOS having a thickness of about 1.8 μm is deposited by, for example, normal pressure CVD, and annealed, thereby obtaining a BPT as shown in FIG.
An EOS layer 4B is formed. Then, the BPTEOS layer 4B
S on the exposed surface of
The iN layer 8B is formed by, for example, a low pressure CVD method.

Then, a cylindrical or frustum-shaped, for example, cylindrical through-hole (recess) 1CK (hereinafter also referred to as “cylindrical 1CK”) is formed from the exposed surface of the SiN layer 8B to the interlayer insulating film 110 (hereinafter, also referred to as “cylindrical 1CK”). (See FIG. 5). At this time, the through hole 1C
The formation position of the through hole 1CK is determined so that the plug 56 is exposed in the opening of the K on the silicon substrate 121 side. The through hole 1CK is formed, for example, as follows. First,
A resist (not shown) is applied to the entire surface of the exposed surface of the SiN layer 8A shown in FIG. 4, and is patterned by photolithography. Then, the two layers 8B and 4B are dry-etched using the patterned resist as a mask. As a result, as shown in FIG.
A dielectric layer 48C composed of the OS layer 4C and the SiN layer 8C is formed. The cylinder formed by hollowing out the dielectric layer in this manner is also referred to as a “cut cylinder”.

Step B1-3. Step of Forming Eaves After that, the substrate in the state shown in FIG. 5 is subjected to wet etching using a diluted hydrofluoric acid (HF) solution. At this time, Si
An eaves portion 8AT is formed as shown in FIG. 6 due to the difference in the etching rate between N and BPTEOS.
Specifically, a diluted hydrofluoric acid solution having a dilution ratio of 100: 1 (hereinafter, referred to as a dilute hydrofluoric acid solution)
When "100: 1 HF solution" is used, the BPT
The EOS layer 4C is etched at an etching rate of about 350 Å / min, for example, while the Si
The N layer 8C is hardly etched. For this reason, after the etching, the BPTEOS layer 4C of FIG. 5 is etched to form the BPTEOS layer 4A as shown in FIG.
However, the SiN layer 8C is hardly etched to form the SiN layer 8A shown in FIG. As a result, the eaves 8AT having an overhang length of about 500 angstroms by etching for about 1.5 minutes,
It can be easily formed in the through hole 8AK (see FIG. 2) corresponding to the opening of the cylinder 1AK.

Step B1-4. Step of Forming Silicon Film for Storage Node Electrode Next, a doped amorphous silicon film (about 250 angstroms thick) and a non-doped amorphous silicon film (thickness 2
About 50 Å) in this order,
As shown in FIG. 7, a silicon film (conductive layer) 6B made of both amorphous silicon films is formed. At this time, the plug 56 in the contact hole 110K is
Integrate with B.

Thereafter, the exposed surface of the silicon film 6B was roughened under the conditions of a surface temperature of 520 ° C., a flow rate of disilane gas of 20 sccm, and a pressure inside the reaction furnace of 2 Torr, and as shown in FIG. A silicon film 6C having an unevenness of about 500 angstroms is formed.

Step B1-5. Thereafter, a resist 50A is deposited so as to cover the entire exposed surface of the substrate in the state of FIG. 8 (see FIG. 9), and the entire surface is exposed from the exposed surface side of the resist 50A. At this time, the portion of the resist 50A inside the cylinder 1AK is
It is not exposed because it is far from the exposed surface of
After development, it is left as a resist (first mask) 50B (see FIG. 10). In other words, by the exposure and development, as shown in FIG.
The application amount of the resist 50A is determined so as to fill with B.

In particular, according to the present manufacturing method, the eaves portion 8A
Compared with the opening of the conventional cylinder 1P having no T (see FIG. 32), the area of the opening is reduced by the length of the eaves 8AT, so that the scattered light that enters the cylinder 1AK during exposure. Can be significantly reduced. Therefore, the silicon layer 6C in the cylinder 1AK can be surely covered with the resist 50B as well as the eaves portion 8AT.

Thereafter, dry etching (anisotropic etching) is performed on the exposed surface of the substrate in the state shown in FIG. At this time, since the silicon film 6C in the cylinder 1AK is protected by the resist 50B and the eaves 8AT, the silicon film 6C can be surely and stably left, while the portion not covered with the resist 50B is removed. Therefore, after the etching and the removal of the resist 50, FIG.
As shown in FIG. 7, the silicon film 6A described above, that is, the storage node electrode 6A is formed.

Step B1-6. Step of Forming Cell Plate Electrode, etc. Then, capacitor dielectric 10 is formed on surface 6AS of silicon film 6A (see FIG. 2). The dielectric 10 is
For example, by forming a dielectric film such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film by a CVD method, or by thermally oxidizing the roughened surface 6AS (see FIG. 2) of the silicon film 6A, It is formed by forming an oxide film. Further, for example, a multilayer structure such as a two-layer structure of a SiN film and a silicon oxide film may be employed.

Subsequently, the inside of the cylinder 1AK is completely embedded,
Further, polysilicon or the like is deposited by, for example, a CVD method so as to cover the SiN layer 8A to form the cell plate electrode 36 (see FIG. 1). After that, an interlayer insulating film 210 is formed on the cell plate electrode 36, and a predetermined wiring 212 is formed on the film 210. Further, an interlayer insulating film 211 is formed on the interlayer insulating film 210 so as to cover the wiring 212, and a wiring 213 is formed, whereby the semiconductor memory 100A shown in FIG. 1 is completed.

As described above, according to the present manufacturing method, the silicon film or the side wall 6AV of the storage node electrode 6A is formed.
Can be formed in contact with the eaves portion 8AT. That is, the silicon film 6A can be formed on the entire surface of the wall surface 4AW. Therefore, it is possible to manufacture the semiconductor memory 100A having the effects of increasing the capacity and increasing the reliability of the memory operation as described above.

In the above description, the case where the surface 6AS of the storage node electrode 6A is roughened has been described. However, as in the semiconductor memory 100B shown in FIG. 12, the storage node electrode 6AA of the capacitor C2 (FIG. Even if the surface 6AAS of the storage node electrode 6A is not roughened, it is possible to obtain the above-described effects of increasing the capacity and improving the reliability of the memory operation caused by the eaves portion 8AT. it can. The semiconductor memory 100B can be manufactured by omitting the execution of the surface roughening process in the process B1-4 in the above-described manufacturing method.

<Second Embodiment> In the first embodiment, the BPTEOS layers 4A and 4A having different opening sizes are used.
The case where the eave portion 8AT is formed by the iN layer 8A has been described. Here, the BPTE is formed in the eaves forming step B1-3.
In view of the fact that the eaves portion 8AT is formed by utilizing the difference between the etching rates of OS and SiN with respect to diluted hydrofluoric acid,
By applying a configuration in which a first dielectric layer corresponding to the BPTEOS layer and a second dielectric layer corresponding to the SiN layer having an etching rate smaller than that of the first dielectric layer are stacked in this order, An eave portion can be formed. Although various combinations of such first and second dielectric layers are conceivable, a manufacturing method in the case where both the first and second dielectric layers are made of TEOS will be described in the second embodiment.

More specifically, the aforementioned dielectric layer forming step B1-2
In the above, a BPTEOS layer 4B formed by the normal pressure CVD method as described above is formed as a first dielectric layer, and a TEOS layer (having a thickness of 100
(About 0 Å). 1 as described above
The etching rate of BPTEOS for the 00: 1 HF solution is about 350 Å / min, while the etching rate of the reduced-pressure TEOS layer forming the second dielectric layer is about 200 Å / min. Therefore, if the etching rate difference is used in the eaves forming step B1-3, the etching with the 100: 1 HF solution for about 3.5 minutes can be performed to form the 500 angstrom formed by the periphery of the opening of the reduced-pressure TEOS layer. A degree of eaves can be formed. As a result, a capacitor having a larger capacity than the conventional capacitor CP can be formed,
As a result, a semiconductor memory with high reliability in memory operation can be manufactured.

<Third Embodiment> FIG. 13 is a schematic longitudinal sectional view of a semiconductor memory 100C as a semiconductor device according to a third embodiment, and FIG.
The principal part enlarged view of C is shown. The same components as those described above are denoted by the same reference numerals, and the detailed description thereof will be referred to. This applies to the fourth embodiment described later.

A3. Configuration of Semiconductor Device As shown in FIG. 13 and FIG.
Is the BPTEOS layer 4 forming the dielectric layer 48A shown in FIG.
A includes a dielectric layer 48D having a structure in which a SiN layer (third dielectric layer) 18D is inserted. Specifically, the dielectric layer 48
D is a BPT having a cylindrical or frustum-shaped through hole 4D1K.
EOS layer 4D1, SiN layer 18D having through hole 18DK, and SiN layer 4D2 having through hole 4D2K
And the SiN layer 8A described above. The contact hole 110K and the four through holes 4D1K, 18
DK, 4D2K, and 8AK are arranged in a direction substantially perpendicular to the surface of the silicon substrate 121, and the respective layers 4D1, 18
D, 4D2 and 8A are formed in this order. The edges of the through holes 18DK and 8AK are Si of the through hole 4D1 respectively.
It is surrounded by the edge at the end on the N layer 18D side and the edge at the edge on the SiN layer 8A side of the through hole 4D2. Two through holes 1
8DK and 8AK may have substantially the same size. In addition,
In the following description, four through holes 4D1K, 18DK, 4
The through-hole made of D2K and 8AK is called “cylinder 1DK”.
At this time, the cylinder 1DK has a concave shape with respect to the surface of the SiN layer 8A on the side opposite to the BPTEOS layer 4D1.

As described above, the end or the periphery 18DT of the SiN layer 18D protrudes into the cylinder 1DK. For this reason, the wall surfaces 4D1W, 4D2W of the respective through holes 4D1, 4D2.
In addition, the surface area of the wall surface (also the wall surface of the cylinder 1DK) 49DW of the dielectric layer 48D composed of the surface 18DTS of the protrusion 18DT corresponds to the protrusion 18DT more than the same wall 4AW of the capacitor C1 (see FIG. 2). Therefore, the surface area of the storage node electrode 6D formed on the wall surface 49DW is equal to the storage node electrode 6A described above.
(See FIG. 1). Therefore, the semiconductor memory 10
According to the capacitor C3 of 0C, the capacitor C1 described above is used.
A larger capacity can be obtained as compared with (see FIG. 1). As a result, a semiconductor memory with high memory operation reliability can be provided.

B3. Next, a method of manufacturing the semiconductor memory 100C will be described with a focus on a method of forming the capacitor C3. First, in the substrate preparing step B1-1 described above, a substrate in the state shown in FIG. 3 is prepared (step B3-1).

Step B3-2. Step of Forming Dielectric Layer Then, as shown in FIG. 15, the BPTEOS layer 4E1, the SiN layer 18E, the BPTEOS layer 4E2, and the SiN layer 8B are formed in this order so as to cover the exposed surface of the interlayer insulating film 110. Laminate.

Then, a through hole 1FK extending from the exposed surface of the SiN layer 8B to the interlayer insulating film 110 is formed in the same manner as the above-described cylinder 1AK (see FIG. 5) (see FIG. 16). Thereby, as shown in FIG. 16, the remaining BPTEOS layer 4F
1, 4F2, the SiN layer 8A, and the SiN layer 18F (the above-described S
A dielectric layer 48F (same as the iN layer 18D) is formed.

Step B3-3. Step of Forming Eaves and Protrusions Next, similarly to the step of forming the eaves B1-3 described above, FIG.
By performing wet etching with a dilute hydrofluoric acid (HF) solution on the substrate in the state described above, the above-described cylinder 1DK is formed as shown in FIG. As described above, the protrusion can be easily formed by isotropic etching utilizing the difference in the etching rate between the silicon nitride and the BPTEOS oxide.

Thereafter, the semiconductor memory 100C shown in FIG. 13 is completed by performing the above-described step B1-4 of forming a silicon film for storage node electrodes to step B1-6 of forming a cell plate electrode and the like.

In the second embodiment, the dielectric layer 48D includes the BPTEOS layers 4D1 and 4D2 and the SiN layers 8A and 8D.
Although the case of the four-layer structure made of D has been described, a plurality of protrusions can be formed by making the BPTEOS layer and the SiN layer more multilayer in the above-described dielectric layer forming step B3-2.

<Embodiment 4> A4. Configuration of Semiconductor Device FIG. 18 is a schematic longitudinal sectional view of a semiconductor memory 100D as a semiconductor device according to the fourth embodiment. As can be seen by comparing FIG. 18 with the above-described FIGS. 1 and 2, the semiconductor memory 100D includes the SiN layer 8 in the semiconductor memory 100A.
A, while the capacitor C of the memory 100D is not provided.
Reference numeral 4 has a storage node electrode or a storage node electrode 26G having a structure in which a silicon film 16G made of rough poly grains is formed in an eaves shape at the end 6AE2 (see FIG. 2) of the silicon film 6A. Specifically, as shown in FIG. 18, the storage node electrode 26G
A silicon film 6G corresponding to the above-described silicon film 6A formed on the entire surface of the wall surface 4AW of the PTEOS 4A and an edge 6GE2 of the silicon film 6G (corresponding to the edge 6AE2 of the silicon film 6A shown in FIG. 2). Silicon film or eave portion 16G made of the roughened poly-grain.

Therefore, according to the storage node electrode 26G, the capacitance can be increased more than the conventional capacitor CP by maximizing the surface area of the wall surface 4AW of the BPTEOS layer 4A, and has no eaves. Eaves portion 16G rather than a capacitor (for example, capacitor C1 described above)
The capacity can be increased by an amount corresponding to the surface area of the substrate. For this reason, according to the semiconductor memory 100D, a highly reliable operation can be realized in which an increase in capacity eliminates a memory operation problem that may occur due to insufficient capacity.

Hereinafter, a method of manufacturing the semiconductor memory 100D will be described focusing on a method of forming the capacitor C4.

B4. First, in the substrate preparing step B1-1 described above, a substrate in the state of FIG. 3 is prepared (step B4-1).

Step B4-2. Step of forming dielectric layer Then, BP is formed so as to cover the exposed surface of interlayer insulating film 110.
After laminating the TEOS layer, as shown in FIG. 19, a cylindrical through-hole (recess) 4AK from the exposed surface of the BPTEOS layer to the interlayer insulating film 110 is formed, and the BPT is formed.
An EOS layer (dielectric layer) 4A is formed.

Step B4-3. Step of Forming Silicon Film for Storage Node Electrode Subsequently, similarly to the above-described step B1-4, a doped amorphous silicon film and a non-doped amorphous silicon film are formed on the exposed surface of the substrate in the state of FIG. A silicon film (first conductive layer) laminated in order is formed.
Thereafter, the exposed surface of the silicon film is roughened under the same forming conditions as in the above-described step B1-4 to form a silicon film 6H shown in FIG.

Thereafter, BPTEOS (for example, a boron concentration of 3.0 wt% and a phosphorus concentration of 7.0 mol / liter) is deposited so as to cover the exposed surface of the silicon film 6H. Then, the BPTEOS is flattened by performing an annealing process at a temperature of, for example, 750 ° C. in a diffusion furnace to form a BPTEOS film 51A as shown in FIG.

Next, the BPTEOS film 51A is patterned by photolithography and dry etching,
The BPTEOS film (second mask) 51B is formed by removing the opening of the through hole 4AK on the side opposite to the silicon substrate 121 and the periphery thereof in the BPTEOS film 51A (see FIG. 22). That is, as shown in FIG. 22, by this patterning, the vicinity of the opening far from the silicon substrate 121 in the silicon film 6H, that is, the shoulder is exposed.

Then, a surface temperature of 520 ° C. and a flow rate of disilane gas of 20 sc were applied to the substrate in the state shown in FIG.
cm, and a silicon pressure of 2 Torr in the reactor.
The exposed surface of the shoulder of H is further roughened (see FIG. 23).
As a result, as shown in FIG. 23, a silicon film (second conductive layer) 16H made of rough poly-particles bonded to the shoulder of the silicon film 6H is formed. The unevenness difference is about 300 angstroms. At this time, since a new silicon film corresponding to the silicon film 6B (see FIG. 7) is not formed for forming the silicon film 16H, the BPTEOS 51B is completely covered by the silicon film (rough surface poly-grain) 16H. There is no. The above two silicon films 6H, 1
6H is also collectively referred to as “silicon film (conductive layer) 26H”.

Thereafter, the BPTEOS film 51B is removed by etching with a 100: 1 HF solution. At this time, the silicon film (rough surface poly-grain) 16H on the BPTEOS film 51B is removed together with the BPTEOS film 51B (lifted off), while the portion of the silicon film 16H bonded to the shoulder of the silicon film 6H is removed. The silicon film 16I is left without being formed (see FIG. 24). As a result, a silicon film 26I composed of the silicon film 16I and the silicon film 6H is formed.

Step B4-4. Next, as shown in FIG. 25, after filling the inside of the cylinder 4AK with the resist 50B, the exposed surface is dried in the same manner as the storage node electrode forming step B1-5 described above. When etching (anisotropic etching) is performed, portions of the silicon film 6H and the silicon film 16I that are not covered with the resist 50B are removed, and the silicon film 6H and the silicon film 16G are changed to the silicon film 6G and the silicon film 16G shown in FIG. 26, respectively. At this time,
Since the silicon film 16I forming the shoulder of the silicon film 26H shown in FIG. 25 has a large thickness along the direction perpendicular to the substrate, the silicon film 16G is left in an eaves without being entirely etched away. (See FIG. 26). Thus, according to the present manufacturing process, the eaves portion 16G can be formed reliably and stably. Then, the resist 50B is removed. Thus, a storage node electrode 26G made of the silicon films 6G and 16G is formed.

Thereafter, by performing the above-described step B1-6 of forming a cell plate electrode and the like, the semiconductor memory 100D shown in FIG. 18 is completed.

As described above, according to the present manufacturing method, it is possible to manufacture the semiconductor memory 100D having the effects of increasing the capacitance of the capacitor and improving the reliability of the memory operation.

The BPTEO of the semiconductor memory 100D
Protrusions 18DT shown in FIG. 13 may be provided in the S layer 4A, or a silicon film whose surface on the cell plate electrode 36 side is not roughened may be used as the storage node electrode 26G.

[0075]

(1) According to the first aspect of the present invention, the side wall of the electrode of the capacitor is in contact with the eaves. For this reason, by providing the eaves portion at the end of the wall surface on which the side wall portion is formed, a capacitor having electrodes formed on the entire surface of the wall surface can be formed. Therefore, it is possible to obtain a capacitor having a large capacity that makes full use of the surface area of the wall surface. As a result, for example, when the semiconductor device is a semiconductor memory, a semiconductor memory with high memory operation reliability can be provided.

(2) According to the second aspect of the present invention, the etching rate of the dielectric forming the eaves portion is smaller than that of the material forming the wall surface. For this reason, the material forming the wall surface and the dielectric material forming the eave portion are laminated in this order, and a concave portion penetrating through the dielectric material forming the eave portion and reaching the material forming the wall surface is formed, and then isotropically formed with respect to the concave portion. By performing the reactive etching, the eaves portion can be easily formed by utilizing the difference between the etching rates of the two materials.

(3) According to the third aspect of the present invention, since the eaves form a part of the electrode, the capacity is larger than the capacitor having no eaves by an amount corresponding to the surface area of the eaves. . Therefore, for example, when the semiconductor device is a semiconductor memory, the reliability of the memory operation can be further improved.

(4) According to the fourth aspect of the present invention, the capacitance of the capacitor is larger by an amount corresponding to the surface area of the protruding shape than in the case without the protruding shape. Therefore, for example, when the semiconductor device is a semiconductor memory, the reliability of the memory operation can be further improved.

(5) According to the fifth aspect of the present invention, the electrode has a large surface area by the roughened surface. Therefore, the capacitance of the capacitor including the electrode can be further increased. As a result, for example, when the semiconductor device is a semiconductor memory, a semiconductor memory with higher reliability in memory operation can be provided.

(6) According to the sixth aspect of the present invention, the step (c) of forming the eaves, the step (b) of forming the conductive layer, and the step (d) of etching the conductive layer are performed in this order. Accordingly, in the step (d), the conductive layer in the concave portion is covered with the first mask and the eaves. Therefore, the conductive layer in the concave portion is not removed by the etching in the step (d). Therefore, since the conductive layer can be formed on the entire inner surface of the concave portion, it is possible to form a capacitor having a capacitance that makes full use of the shape of the concave portion. At this time, the conductive layer in the vicinity of the opening of the concave portion can be reliably and stably left as compared with the conventional manufacturing method that does not have the eaves forming step (c). As a result, for example, when the semiconductor device is a semiconductor memory, a semiconductor memory with high memory operation reliability can be manufactured.

(7) According to the seventh aspect of the present invention, the resist is filled in the concave portion and exposed and developed. At this time, since the area of the opening is narrowed by the length of the eaves portion compared to the opening of the conventional concave portion without the eaves, the amount of scattered light entering the recess at the time of exposure is significantly reduced. be able to. Thereby, not only the eaves portion but also the conductive layer in the concave portion can be reliably covered with the resist as the first mask. For this reason, even after the etching in the step (d), the conductive layer in the concave portion can be reliably left.
Therefore, the effect (6) can be reliably obtained.

(8) According to the invention according to claim 8, the second
Since the etching rate of the dielectric layer is lower than that of the first dielectric layer, the eaves can be easily formed by the isotropic etching in the step (c). as a result,
The effect of the above (6) can be obtained.

(9) According to the ninth aspect, the second conductive layer left after the step (c) forms an eave portion. Therefore, in addition to the effect (6), the capacitance of the capacitor can be increased by the amount of the remaining second conductive layer.

(10) According to the tenth aspect,
By performing the conductive layer forming step (b) after forming the protrusion in the step (e), the capacitance of the capacitor can be increased according to the surface area of the protrusion. As a result, for example, when the semiconductor device is a semiconductor memory, a semiconductor memory with high memory operation reliability can be manufactured.

(11) According to the eleventh aspect,
Since the etching rate of the third dielectric layer is lower than that of the first dielectric layer, the protrusion can be easily formed by the isotropic etching in the step (e-2). As a result, the effect (10) can be obtained.

(12) According to the twelfth aspect,
By increasing the surface area by roughening the conductive layer, the capacitance of the capacitor can be further increased. As a result, for example, when the semiconductor device is a semiconductor memory, a semiconductor memory with high memory operation reliability can be manufactured.

(13) According to the thirteenth aspect,
By exhibiting any of the effects (6) to (12), for example, when the semiconductor device is a semiconductor memory, a semiconductor memory with high reliability in memory operation can be provided.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view schematically showing a semiconductor device according to a first embodiment.

FIG. 2 is a schematic longitudinal sectional view showing an enlarged main part of the semiconductor device according to the first embodiment;

FIG. 3 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 4 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 5 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 6 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 7 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 8 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 9 is a schematic longitudinal sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 10 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 11 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 12 is a longitudinal sectional view schematically showing another configuration of the semiconductor device according to the first embodiment.

FIG. 13 is a longitudinal sectional view schematically showing a semiconductor device according to a third embodiment.

FIG. 14 is a schematic longitudinal sectional view showing an enlarged main part of a semiconductor device according to a third embodiment.

FIG. 15 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 16 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 17 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment.

FIG. 18 is a longitudinal sectional view schematically showing a semiconductor device according to a fourth embodiment.

FIG. 19 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 20 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 21 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 22 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 23 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 24 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 25 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 26 is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 27 is a longitudinal sectional view schematically showing a semiconductor device according to a conventional technique.

FIG. 28 is a schematic longitudinal sectional view for explaining a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 29 is a schematic longitudinal sectional view for explaining a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 30 is a schematic longitudinal sectional view for describing a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 31 is a schematic longitudinal sectional view for illustrating a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 32 is a schematic longitudinal sectional view for illustrating a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 33 is a schematic longitudinal sectional view for explaining a method of manufacturing a semiconductor device according to a conventional technique.

[Explanation of symbols]

1AK, 1CK, 1DK, 1FK, 4AK cylinder (recess), 4A-4D, 4D1-4F1, 4D2-4D2
BPTEOS layer (first dielectric layer), 4AW, 4D1W,
4D2W, 49DW wall surface, 6A, 6AA, 6D, 26
G storage node electrode, 6A to 6F, 6AA, 26
H silicon film (conductive layer), 6B, 6C, 6H silicon film (first conductive layer), 6AH bottom, 6AE1, 6A
E2, 6GE2 edge, 6AV side wall, 6AS,
6AHS, 6AVS surface, 8A-8C silicon nitride layer (second dielectric layer), 8AT, 16G eaves, 16
G, 16I silicon film, 16H silicon film (second conductive layer) 18D-18F silicon nitride layer (third dielectric layer), 18DT protrusion, 18DTS surface, 48A,
48C, 48D, 48F Dielectric layer, 50A, 50B
Resist (first mask), 51A, 51B BPTEO
S film (second mask), 100A to 100D semiconductor memory (semiconductor device), C1 to C4 capacitors.

Claims (13)

[Claims] 1. A semiconductor device provided with a capacitor, wherein the capacitor has a concave electrode having a bottom surface and a side wall formed on a predetermined wall surface and coupled to an edge of the bottom surface. The semiconductor device is characterized in that it comprises an eaves portion arranged in contact with an edge portion of the side wall portion opposite to the edge portion, and extending to the central portion of the concave shape, Semiconductor device. 2. The semiconductor device according to claim 1, wherein the eave portion is made of a dielectric having an etching rate smaller than a material forming the wall surface. 3. The semiconductor device according to claim 1, wherein the eave portion is coupled to the edge portion of the side wall portion opposite to the edge portion to form a part of the electrode. A semiconductor device, which is characterized by the following. 4. The semiconductor device according to claim 1, wherein said wall surface protrudes toward said central portion of said concave shape between said edge portions of said side wall portion. A semiconductor device, which is characterized by the following. 5. The semiconductor device according to claim 1, wherein a surface of said side wall portion opposite to said wall surface is roughened. 6. A method for manufacturing a semiconductor device having a capacitor, comprising: (a) forming a dielectric layer having at least a first dielectric layer and having a recess; and (b) forming the dielectric layer. (C) forming an eave portion extending from the edge of the opening to the center of the opening in the opening of the recess; and (d) forming the eaves portion in the opening of the recess. Performing etching on the conductive layer using a first mask that covers at least a portion in the recess, and using the remaining conductive layer as an electrode of the capacitor. Device manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the first mask is arranged with a resist so as to fill the recess and cover the entire conductive layer. A method for manufacturing a semiconductor device, comprising: exposing the resist from an exposed surface side and leaving the resist after development. 8. The method for manufacturing a semiconductor device according to claim 6, wherein in the step (a), the first dielectric layer and an etching rate smaller than the first dielectric layer are used. And forming a second dielectric layer forming the dielectric layer together with the first dielectric layer in this order, so as to penetrate through the second dielectric layer and reach the inside of the first dielectric layer. Forming the recess, performing the step (c) after the step (a), and in the step (c), performing isotropic etching on the first and second dielectric layers to form the second dielectric layer. A method of manufacturing a semiconductor device, comprising: forming the eave portion made of a layer; and performing the step (b) after the step (c). 9. The method of manufacturing a semiconductor device according to claim 6, wherein the step (b) comprises: (b-1) forming a first conductive layer covering the dielectric layer; (B-2) a step of covering the opening portion and its periphery in the first conductive layer with a second mask, and (b-3) contacting the first conductive layer around the opening portion with the second mask, Forming a second conductive layer that forms the conductive layer together with the first conductive layer, wherein in the step (c), the second mask and the second conductive layer on the second mask are removed. A method for manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 6, wherein (e) forming a protruding portion on an inner surface of the concave portion,
A method for manufacturing a semiconductor device, further comprising: 11. The method for manufacturing a semiconductor device according to claim 10, wherein the step (e) comprises: (e-1) the step (a), wherein the etching rate is higher than that of the first dielectric layer in the step (a). A third dielectric layer of a small dielectric forming the dielectric layer interposed in the layer;
Forming the concave portion so as to penetrate the dielectric layer; and (e-2) performing isotropic etching on the dielectric layer after the step (e-1). , A method of manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (b), the exposed surface of the conductive layer is roughened. Device manufacturing method. 13. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 6. Description: