JP2001035948A - High frequency semiconductor element - Google Patents
High frequency semiconductor elementInfo
- Publication number
- JP2001035948A JP2001035948A JP20867099A JP20867099A JP2001035948A JP 2001035948 A JP2001035948 A JP 2001035948A JP 20867099 A JP20867099 A JP 20867099A JP 20867099 A JP20867099 A JP 20867099A JP 2001035948 A JP2001035948 A JP 2001035948A
- Authority
- JP
- Japan
- Prior art keywords
- base substrate
- frequency semiconductor
- semiconductor chip
- thermal expansion
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高周波半導体素子の
構造に関するものである。The present invention relates to a structure of a high-frequency semiconductor device.
【０００２】[0002]
【従来の技術】従来より高周波半導体素子は、ハーメチ
ックシール構造をとるのが一般的である。例えば特開平
０５−２９１４２５号記載のようにベース基板にCu／Mo
／Cuクラッド材などを用いてSiあるいはGaAsからなる高
周波半導体チップを搭載し、低融点ガラスなどで封止し
たリードフレームにワイヤで接続し、金属あるいはセラ
ミックからなるキャップが設けられている。特に、ベー
ス基板材料には放熱性や半導体チップとの熱膨張率の整
合性が求められ、Cu／Mo／Cuの他にもアルミナセラミッ
クスやインバー／Cu／インバー等が用いられている。2. Description of the Related Art Conventionally, high frequency semiconductor devices generally have a hermetic seal structure. For example, as described in JP-A-05-291425, Cu / Mo
A high-frequency semiconductor chip made of Si or GaAs is mounted using a / Cu clad material or the like, connected to a lead frame sealed with low-melting glass or the like by a wire, and a cap made of metal or ceramic is provided. In particular, the base substrate material is required to have a heat radiation property and consistency of the coefficient of thermal expansion with the semiconductor chip, and alumina ceramics, invar / Cu / invar, and the like are used in addition to Cu / Mo / Cu.
【０００３】[0003]
【発明が解決しようとする課題】近年、高周波半導体素
子の性能向上と普及に伴い、これに適用される半導体パ
ッケージについても放熱性や半導体チップとの熱膨張率
の整合性に加えて、加工容易性や軽量、低コストがます
ます求められている。しかし、上記従来技術のベース基
板構造ではこれらの要求を十分満足することができず更
なる改善が求められていた。In recent years, as the performance of high-frequency semiconductor devices has been improved and spread, semiconductor packages applied to these devices have been required to be easy to process in addition to heat dissipation and matching of thermal expansion coefficient with semiconductor chips. There is an increasing demand for flexibility, light weight and low cost. However, the above-mentioned prior art base substrate structure cannot sufficiently satisfy these requirements, and further improvement is required.
【０００４】本発明の目的は、放熱性、半導体チップと
の熱膨張率整合性、加工容易性、軽量性、低価格性に優
れた半導体パッケージ、及び、これを適用した高性能、
高出力の高周波半導体素子の構造を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package having excellent heat dissipation, thermal expansion coefficient matching with a semiconductor chip, easy processing, light weight, and low cost, and high performance using the same.
An object of the present invention is to provide a structure of a high-output high-frequency semiconductor device.
【０００５】[0005]
【課題を解決するための手段】本発明の目的を達成する
ため、高周波半導体素子のパッケージにおいては、少な
くともベース基板を熱膨張係数が15x10~6／℃以下、熱
伝導率が130W／mK以上、ビッカース硬度が300以下の部
材から構成した。さらに、ベース基板の材質は、Cuを主
体とした複合材で、特にCuとCu2Oの複合材Cu Cu2Oから
なる構造とした。あるいは、ベース基板の材質は、Cuと
Al2O3の複合材、 CuとSiO2の複合材、あるいはCuとCu2O
とAl2O3の複合材からなる構造とした。In order to achieve the object of the present invention, in a package of a high-frequency semiconductor device, at least a base substrate has a thermal expansion coefficient of 15 × 10 to 6 / ° C. or less, a thermal conductivity of 130 W / mK or more, The Vickers hardness was 300 or less. Further, the material of the base substrate was a composite material mainly composed of Cu, particularly a structure composed of a composite material of Cu and Cu2O, CuCu2O. Alternatively, the material of the base substrate is Cu
Al2O3 composite, Cu and SiO2 composite, or Cu and Cu2O
And a structure made of a composite material of Al2O3.
【０００６】高周波半導体素子のパッケージのベース基
板を熱膨張係数が15x10~6／℃以下、熱伝導率が130W／m
K以上、ビッカース硬度が300以下の部材から構成するこ
とにより高性能、高出力高周波半導体素子の放熱性を確
保し、半導体チップとの熱膨張率整合性を確保すると同
時に、ビッカース硬度が300以下であることにより加工
が容易なため、パッケージ構造の設計自由度が向上し部
品数を低減して素子を製作できる。また、ベース基板の
材質は、Cuを主体とした複合材で、特にCuとCu2Oの複合
材Cu Cu2Oからなる構造、あるいは、CuとAl2O3の複合
材、CuとSiO2の複合材、CuとCu2OとAl2O3の複合材から
なる構造とすることにより、軽量で低価格を実現でき
る。A base substrate of a high-frequency semiconductor device package has a thermal expansion coefficient of 15 × 10 6 / ° C. or less and a thermal conductivity of 130 W / m 2.
K or more, Vickers hardness of 300 or less is used to ensure high performance, high power high-frequency high-frequency semiconductor element heat dissipation and thermal expansion coefficient matching with semiconductor chip, and Vickers hardness of 300 or less Because of this, processing is easy, so that the degree of freedom in designing the package structure is improved, and the number of components can be reduced to manufacture an element. The material of the base substrate is a composite material mainly composed of Cu, particularly a structure composed of a composite material Cu and Cu2O, or a composite material of Cu and Al2O3, a composite material of Cu and SiO2, and a composite material of Cu and Cu2O. By using a structure made of a composite material of Al2O3, light weight and low cost can be realized.
【０００７】[0007]
【発明の実施の形態】以下本発明の実施例を図面を用い
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【０００８】図１は本発明の一実施例の高周波半導体素
子の断面図を示したものである。FIG. 1 is a sectional view of a high-frequency semiconductor device according to one embodiment of the present invention.
【０００９】ＳｉあるいはＧａＡｓ等からなる高周波半
導体チップ101はCuとCu2O の複合材Cu Cu2Oからなるベ
ース基板102上に半田などのロウ材113を用いて接合され
ている。高周波半導体チップ101表面の電極はワイヤ103
によって端子104に接続されている。端子104はセラミッ
クやガラスからなる絶縁材105でロウ材110，111を用い
て封止されている。さらに枠体106、シール材107がロー
材112で接合され、シール材107と蓋体108と溶接接合さ
れることにより高周波半導体素子が完成する。高周波半
導体チップ101は高周波、高出力で動作させるため発生
する熱を効率よく放散する必要があり、また、温度上昇
によるチップ101への熱応力や温度変化によるロー材113
への繰り返し熱歪みを低減することが必要である。ベー
ス基板102が熱膨張係数が15x10~6／℃以下、熱伝導率が
130W／mK以上の材料、例えば、CuとCu2Oの複合材Cu Cu2
Oから構成されているため放熱性がよく、また、高周波
半導体チップ101との熱膨張係数差が小さいため熱応力
が小さい。従って、高周波半導体素子を高周波、高出力
で効率よく安定に動作させることができ高信頼性を確保
できる。また、Cu Cu2O材は800℃程度の高温熱処理にも
耐えることができるため高融点ロー材を適用することも
可能である。また、200℃から500℃といった高温で動作
可能な半導体チップを搭載する場合にも好適である。ベ
ース基板102と枠体106、及びシール材107は異なった部
材から構成されても一体構造であっても構わないが、本
発明の構成によれば、ビッカース硬度が300以下である
ことにより加工が容易なためベース基板102と枠体106、
あるいは、ベース基板102と枠体106とシール材107を一
体構造とした方が部品点数を低減し工程が低減できるた
めより好ましい構造である。A high-frequency semiconductor chip 101 made of Si or GaAs is bonded to a base substrate 102 made of a composite material of Cu and Cu2O using a brazing material 113 such as solder. The electrode on the surface of the high-frequency semiconductor chip 101 is a wire 103
Connected to the terminal 104. The terminal 104 is sealed with an insulating material 105 made of ceramic or glass using brazing materials 110 and 111. Further, the frame body 106 and the sealing material 107 are joined by the brazing material 112, and the sealing material 107 and the lid 108 are welded and joined, thereby completing the high-frequency semiconductor element. The high-frequency semiconductor chip 101 needs to efficiently dissipate the heat generated in order to operate at high frequency and high output. In addition, the thermal stress on the chip 101 due to the temperature rise and the brazing material 113 due to the temperature change
It is necessary to reduce repetitive thermal strain. The base substrate 102 has a coefficient of thermal expansion of 15x10 ~ 6 / ℃ or less,
130W / mK or higher material, for example, Cu and Cu2O composite Cu Cu2
Since it is made of O, it has good heat radiation properties, and has a small thermal expansion coefficient difference from the high-frequency semiconductor chip 101, so that thermal stress is small. Accordingly, the high-frequency semiconductor element can be operated stably with high frequency and high output, and high reliability can be secured. Further, since the Cu Cu2O material can withstand a high temperature heat treatment of about 800 ° C., a high melting point brazing material can be applied. It is also suitable for mounting a semiconductor chip that can operate at a high temperature of 200 ° C. to 500 ° C. The base substrate 102, the frame body 106, and the sealant 107 may be formed of different members or may be of an integrated structure. However, according to the configuration of the present invention, the processing is performed because the Vickers hardness is 300 or less. For ease, base substrate 102 and frame 106,
Alternatively, it is more preferable to form the base substrate 102, the frame body 106, and the sealant 107 into an integrated structure because the number of components can be reduced and the number of steps can be reduced.
【００１０】図２は熱膨張係数が15x10~6／℃以下、熱
伝導率が130W／mK以上、ビッカース硬度が300以下の部
材でベース基板102と枠体106を一体構造としたケース20
1を用いた場合の実施例の斜視図を示している。Cu Cu2O
材で高周波半導体チップが囲まれているため電磁シール
ドとして機能し、電磁ノイズが漏洩することもなく安定
に動作できる。FIG. 2 shows a case 20 in which the base substrate 102 and the frame 106 are integrally formed of a member having a coefficient of thermal expansion of 15 × 10 6 / ° C. or less, a thermal conductivity of 130 W / mK or more, and a Vickers hardness of 300 or less.
FIG. 2 shows a perspective view of the embodiment when 1 is used. Cu Cu2O
Since the high-frequency semiconductor chip is surrounded by the material, it functions as an electromagnetic shield and can operate stably without leakage of electromagnetic noise.
【００１１】図３は本発明の他の実施例を示したもので
ある。本発明ではベース基板301のビッカース硬度が300
以下であることにより加工が容易であることから各種の
突起を設けている。すなわちベース基板301に突起303、
及び溝302が設けられている。これらの突起や溝はチッ
プ101の周辺、及び、端子104を封止する絶縁材105の周
辺に設けられている。このため、高周波半導体チップ10
1のロー材113の流れ出しを防止し、更にチップ位置合わ
せを行うことが容易である。さらに、突起303によって
ロー材110についても流れ出しが防止されている。この
効果はロー材110を用いずガラスによって直接封止され
ている場合も同様に得られるものである。また、溝302
によってチップ直下のベース厚を薄くしているため熱抵
抗が小さく放熱性が優れている。これらの形状の工夫に
より部材間の位置精度が向上し高周波半導体素子の寸法
を小さくすることも可能である。FIG. 3 shows another embodiment of the present invention. In the present invention, the Vickers hardness of the base substrate 301 is 300.
Various projections are provided because processing is easy by the following. That is, the protrusion 303 on the base substrate 301,
And a groove 302 are provided. These protrusions and grooves are provided around the chip 101 and around the insulating material 105 that seals the terminals 104. Therefore, the high-frequency semiconductor chip 10
It is easy to prevent the solder material 113 from flowing out and to perform chip alignment. Further, the protrusion 303 also prevents the brazing material 110 from flowing out. This effect can be obtained in the same manner even when the glass is directly sealed without using the brazing material 110. Also, groove 302
As a result, the base thickness immediately below the chip is reduced, so that the heat resistance is small and the heat dissipation is excellent. By devising these shapes, the positional accuracy between members is improved, and the size of the high-frequency semiconductor element can be reduced.
【００１２】以上では、熱膨張係数が15x10~6／℃以
下、熱伝導率が130W／mK以上、ビッカース硬度が300以
下の部材としてCuとCu2Oの複合材Cu Cu2Oについて説明
したが、上記の数値範囲を満たすものならばCuとAl2O3
の複合材、 CuとSiO2の複合材、CuとCu2OとAl2O3の複合
材等でも構わない。In the above, a composite material of Cu and Cu2O Cu Cu2O has been described as a member having a coefficient of thermal expansion of 15 × 10 6 / ° C. or less, a thermal conductivity of 130 W / mK or more, and a Vickers hardness of 300 or less. Cu and Al2O3 if they satisfy the range
Composite material, a composite material of Cu and SiO2, a composite material of Cu, Cu2O, and Al2O3.
【００１３】また、高周波半導体素子はＳｉやＧａＡｓ
としたがＧａＮ、ＳｉＣ、ダイアモンド等の他の高周波
半導体素子であっても同様の効果が得られる。The high frequency semiconductor element is made of Si or GaAs.
However, similar effects can be obtained with other high-frequency semiconductor elements such as GaN, SiC, and diamond.
【００１４】[0014]
【発明の効果】以上に述べたように、本発明によれば高
周波半導体素子のパッケージの少なくともベース基板を
熱膨張係数が15x10~6／℃以下、熱伝導率が130W／mK以
上、ビッカース硬度が300以下の部材から構成すること
により放熱性を確保し、半導体チップとの熱膨張率整合
性を確保すると同時にパッケージ構造の設計自由度が向
上し部品数を低減して素子を製作できるため軽量で低価
格な高信頼性高性能、高出力高周波半導体素子を実現で
きる効果がある。As described above, according to the present invention, at least the base substrate of the package of the high-frequency semiconductor device has a thermal expansion coefficient of 15 × 10 6 / ° C. or less, a thermal conductivity of 130 W / mK or more, and a Vickers hardness of at least 130 W / mK. By constructing from 300 or less members, heat dissipation is ensured, and thermal expansion coefficient matching with the semiconductor chip is ensured. There is an effect that a low-cost high-reliability high-performance, high-output high-frequency semiconductor device can be realized.
【図1】本発明の一実施例の高周波半導体素子の断面
図。FIG. 1 is a sectional view of a high-frequency semiconductor device according to one embodiment of the present invention.
【図2】本発明の一実施例の高周波半導体素子の斜視
図。FIG. 2 is a perspective view of a high-frequency semiconductor device according to one embodiment of the present invention.
【図3】本発明の他の実施例の高周波半導体素子の断面
図。FIG. 3 is a cross-sectional view of a high-frequency semiconductor device according to another embodiment of the present invention.
101…高周波半導体チップ、102，301…ベース基板、103
…ワイヤ、104…端子、105…セラミックやガラスからな
る絶縁材、106…枠体、107…シール材、108…蓋体、11
0，111，112，113…ロウ材、201…一体型ケース、302…
溝、303…突起。101: High frequency semiconductor chip, 102, 301: Base substrate, 103
... wires, 104 ... terminals, 105 ... insulating material made of ceramic or glass, 106 ... frame, 107 ... sealing material, 108 ... lid, 11
0, 111, 112, 113 ... brazing material, 201 ... integrated case, 302 ...
Groove, 303 ... projection.
Claims (5)
を封入するパッケージからなる半導体素子において、少
なくとも前期高周波半導体チップを搭載するベース基板
は熱膨張係数が15x10~6／℃以下、熱伝導率が130W／mK
以上、ビッカース硬度が300以下の部材からなることを
特徴とする高周波半導体素子。1. A semiconductor device comprising a high-frequency semiconductor chip, external terminals and a package enclosing them, at least a base substrate on which the high-frequency semiconductor chip is mounted has a coefficient of thermal expansion of 15 × 10 6 / ° C. or less and a thermal conductivity of 130 W / MK
As described above, a high-frequency semiconductor device comprising a member having a Vickers hardness of 300 or less.
からなることを特徴とする請求項１記載の半導体装置。2. The base substrate is a composite material of Cu and Cu2O, Cu Cu2O.
2. The semiconductor device according to claim 1, comprising:
るいはSiO2あるいはこれらの混合物とからなる複合材で
あることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the base substrate is a composite material comprising Cu and Cu2O, Al2O3, SiO2, or a mixture thereof.
するための突起が設けられていることを特徴とする請求
項１から請求項３のいずれか１項記載の半導体装置。4. The semiconductor device according to claim 1, wherein a projection for positioning the semiconductor element is provided on the base substrate.
わせするための突起が設けられていることを特徴とする
請求項１から請求項４のいずれか１項記載の半導体装
置。5. The semiconductor device according to claim 1, wherein the base substrate is provided with a projection for aligning the terminal and the insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20867099A JP3460631B2 (en) | 1999-07-23 | 1999-07-23 | High frequency semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20867099A JP3460631B2 (en) | 1999-07-23 | 1999-07-23 | High frequency semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001035948A true JP2001035948A (en) | 2001-02-09 |
| JP3460631B2 JP3460631B2 (en) | 2003-10-27 |
Family
ID=16560124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20867099A Expired - Fee Related JP3460631B2 (en) | 1999-07-23 | 1999-07-23 | High frequency semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3460631B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007266417A (en) * | 2006-03-29 | 2007-10-11 | Toshiba Corp | Semiconductor package |
-
1999
- 1999-07-23 JP JP20867099A patent/JP3460631B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007266417A (en) * | 2006-03-29 | 2007-10-11 | Toshiba Corp | Semiconductor package |
| US7838990B2 (en) | 2006-03-29 | 2010-11-23 | Kabushiki Kaisha Toshiba | High-frequency hermetically-sealed circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3460631B2 (en) | 2003-10-27 |
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