JP2001035175A - Designing method for non-voltage semiconductor memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a designing method capable of preventing the read of wrong data by reducing the apparent shift quantity of a threshold value concerning a non-volatile semiconductor memory circuit provided with a non-volatile memory cell (memory cell) for storing data corresponding to the level of a threshold voltage. SOLUTION: In the case of newly developing the non-volatile memory circuit of large storage capacity in the same circuit form, when the precharge voltage of a bit line in the memory circuit, to which reliability is already confirmed, is defined as Vp1, the parasitic capacitance of the bit line is defined as Cs1, the discharge time of the bit line is defined as Td1, the precharge voltage of a bit line in the memory circuit to be developed is defined as Vp2, the parasitic capacitance of the bit line is defined as Cs2 and the discharge time of the bit line is defined as Td2, the circuit is designed by setting the bit line precharge voltage Vp2, the parasitic capacitance Cs2 of the bit line and the bit line discharge time Td2 so as to keep the relation of (Vp1.Cs1)/Td1=(Vp2.Cs2)/Td2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a nonvolatile semiconductor memory circuit comprising a nonvolatile memory element for storing data at a high or low threshold voltage, and to prevent a shift of the threshold voltage of the memory element. For example, the present invention relates to a technology that is effective when a plurality of pieces of stored information are used in a nonvolatile storage device (hereinafter, simply referred to as a flash memory) that can be electrically erased collectively.

[0002]

2. Description of the Related Art A flash memory uses a nonvolatile memory element having a control gate and a floating gate as a memory cell, and the memory cell can be constituted by one transistor. In such a flash memory, in the erasing operation, the source and well regions are set to, for example, 0 V (volt), the control gate is set to a high voltage such as 16 V, and negative charges are injected into the floating gate to increase the threshold voltage ( Logic "1")
To In the write operation, the drain voltage of the nonvolatile memory element is set to, for example, 4 V, and the word line to which the control gate is connected is set to, for example, -12 V, whereby charges are drawn from the floating gate to the drain region, and the threshold voltage is lowered. State (logic "0"). Thus, one bit of data is stored in one storage element.

As shown in FIG. 2, for example, as shown in FIG. 2, n pieces (for example, 128) of a parallel type are arranged in a column direction and a source and a drain are commonly connected.
Memory cells (MO having a floating gate)
There is a memory array in which a plurality of memory blocks each including a plurality of memory columns MCCs (SFETs) MC1 to MCn arranged in a row direction (direction of a word line WL) are arranged.

Further, in the flash memory of FIG. 2, a memory column MCC has n memory cells MC1 to MC
n are connected to a common local bit line LBL and a common local source line LSL, respectively, and the local bit line LBL is connected to a selection MOSFET.
The main bit line MBL can be connected to the common source line CSL via Qs1, and the local source line LSL can be connected to the common source line CSL via the selection MOSFET Qs2. As described above, the memory array is divided into a plurality of blocks, and the local bit line LBL provided for each block is
By being connected to the main bit line MBL via Qs1, the power consumption required for precharging the bit line can be reduced.

[0005]

To read data from the memory array having the above structure, one word line WL in a block is set to a selected level and a selected MOSFET on a local bit line LBL to which a selected memory cell is connected.
By turning on Qs1, the local bit line LBL is connected to the main bit line MBL, and the potential of the main bit line that changes according to the threshold voltage of the selected memory cell is sense amplifier (S
LT). Note that the potential of the word line at the time of data reading is, as shown in FIG. 4A, a memory cell storing data corresponding to logic "1" and a memory cell storing data corresponding to logic "0". Are substantially equal to each other, the voltage VRc is set at a substantially intermediate level VRc in the distribution of the threshold voltage of each memory cell.

However, the threshold voltages of the memory cells MC connected to one word line WL are not always substantially the same, and for example, as shown in FIG. In some cases, the number of memory cells to store is extremely large, and in the case of FIG. 4C, the number of memory cells to store data corresponding to logic “0” is extremely large.
If a word line having an extremely large number of memory cells storing data corresponding to logic “0” is selected, an extremely large current may flow toward the common source line CSL. When such a large current flows through the common source line CSL, the potential of the local source line LSL rises due to its parasitic resistance, and the apparent threshold voltage of the memory cell increases as shown by the broken line in FIG. Would.

On the other hand, as shown in FIG. 4B, when a word line having an extremely large number of memory cells storing data corresponding to logic "1" is selected, a current flowing through the common source line CSL is reduced. Very low. As a result, the voltage drop due to the parasitic resistance of the common source line CSL decreases, the potential of the local source line LSL sinks, and the apparent threshold voltage of the memory cell decreases as indicated by the broken line in FIG. (Hereinafter, such a phenomenon is referred to as a threshold shift.) As a result, if the distribution of the memory cells storing the data corresponding to the logic “1” and the distribution of the memory cells storing the data corresponding to the logic “0” are not steep and the interval between the distribution of the memory cells storing the data corresponding to the logic “0” is narrow, It has been clarified that there is a problem that erroneous data may be read. In addition, it has been found that the shift amount of the threshold value increases as the length of the bit line or the source line increases as the capacity of the memory array increases.

An object of the present invention is to provide a nonvolatile semiconductor memory circuit including a nonvolatile memory element (memory cell) having a floating gate and storing data depending on the level of a threshold voltage. An object of the present invention is to provide a design method capable of preventing reading of erroneous data by reducing a value shift amount.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of typical inventions disclosed in the present application.

The present inventors have developed a memory cell storing data corresponding to logic "1" and a logic "0" in the same row of a memory array comprising nonvolatile storage elements for storing data at high and low threshold voltages. As a result of examining the apparent threshold voltage shift phenomenon of the memory cell due to the imbalance of the memory cell storing the data corresponding to the data, the apparent threshold shift amount of the memory cell was ΔVth, and the bit line precharge was performed. The voltage is Vp and the parasitic capacitance of the bit line is C
s, and the time required to discharge the bit line is Td, it has been found that there is a relationship of approximately ΔVth∝ (Vp · Cs) / Td.

The present invention has been made on the basis of the above-described knowledge, and when developing a nonvolatile semiconductor memory circuit having a large storage capacity in the same circuit format as a memory circuit whose reliability has already been confirmed, the reliability has been improved. , The bit line precharge voltage is Vp1, the bit line parasitic capacitance is Cs1, the bit line discharge time is Td1, and the bit line precharge voltage of the storage circuit to be developed is Vp2. , The parasitic capacitance of the bit line is Cs
2. When the discharge time of the bit line is Td2, (Vp1 · Cs1) / Td1 = (Vp2 · Cs2)
The circuit is designed such that the bit line precharge voltage Vp2, the bit line parasitic capacitance Cs2, and the bit line discharge time Td2 are set so that the relationship of / Td2 is maintained.

More specifically, the parasitic capacitance Cs2 of the bit line becomes larger than the parasitic capacitance Cs1 of the bit line of the conventional circuit due to the increase in the capacity of the memory array. A design is made to lower the charge voltage Vp2. Here, as a method of extending the discharge time Td2 of the bit line, for example, the timing at which the reference-side voltage (Vp / 2) is cut off is delayed, or the reference-side precharge voltage is reduced (to Vp / 2 or less). And so on. Even if the bit line precharge voltage Vp2 is lowered to its lower limit, (Vp1 · Cs1) / Td1 = (Vp2
When the relationship of Cs2) / Td2 cannot be maintained, the design is made so that the bit line precharge voltage Vp2 is lowered and the bit line discharge time Td2 is lengthened.

As a method of suppressing the shift amount of the threshold value of the storage element, besides the method of decreasing the bit line precharge voltage Vp2 and the method of increasing the discharge time Td2 of the bit line, Parasitic capacitance C
A method of reducing s2, that is, increasing the number of blocks (the number of divisions) of the memory array may be considered. However, if the number of blocks is increased, the number of selected MOSFETs is increased and the area occupied by the memory array is increased. Therefore, in order to reduce the chip size and suppress the cost increase, the bit line precharge voltage Vp2 must be increased as described above. It is desirable to design such that the discharge time Td2 of the bit line becomes longer or the discharge time Td2 becomes longer.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a flash memory will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a flash memory to which the present invention is applied. Although not particularly limited,
Each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon.

In FIG. 1, reference numeral 11 denotes a memory array in which memory cells as nonvolatile storage elements each composed of a MOSFET having a floating gate are arranged in a matrix, and 12 denotes data of one sector read from the memory array 11. A data register 13 for holding or holding write data input from the outside is a write circuit provided between the memory array 11 and the data register 12 for performing data conversion at the time of writing.

Reference numeral 14 denotes an address register for holding an externally input address signal. Reference numeral 15 denotes one of word lines in the memory array 11 corresponding to an address taken into the address register 14. The selected X decoder 16 sequentially transfers write data from the outside to the data register 12 or the data register 1.
2 is a Y address counter for generating a Y address signal (bit line selection signal) for outputting the data read out to the outside. The Y address counter 16 has a function of sequentially updating and outputting from the start address to the end address of one sector. Reference numeral 17 denotes a Y decoder that decodes the generated Y address and selects one data in one sector, and 18 denotes a main amplifier that amplifies the data read to the data register 12 and outputs the amplified data to the outside.

Although not particularly limited, the flash memory of this embodiment holds a command given from an external CPU or the like and decodes it based on a command register & decoder 21 and a decoding result of the command register & decoder 21. A control circuit (sequencer) 22 for sequentially forming and outputting control signals for each circuit in the memory in order to execute a process corresponding to the command, and when a command is given, decodes it and automatically It is configured to start a corresponding process.

The control circuit 22 is, for example, a ROM (read only memory) storing a series of microinstructions necessary for executing a command (instruction), similarly to a control unit of a microprogram type CPU. , The command register & decoder 21 generates a head address of a microinstruction group corresponding to the command and supplies the head address to the control circuit 22 so that the microprogram is started.

Further, in addition to the above circuits, an I / O buffer circuit 23 for inputting / outputting an address signal and a data signal, and a control signal supplied from an external CPU or the like are input to the flash memory of this embodiment. A control signal input buffer circuit 24 for generating a voltage required inside the chip such as a write voltage, an erase voltage, a read voltage and a verify voltage based on a power supply voltage Vcc supplied from the outside.
5. A desired voltage is selected from these voltages according to the operation state of the memory, and the memory array 11 and the X decoder 15 are selected.
And a power supply switching circuit 26 for supplying power to the power supply.

Although not particularly limited, the flash memory of this embodiment shares an external terminal (pin) I / O for an address signal, a write data signal, and a command input. Therefore, the I / O buffer circuit 23 is configured to discriminate and input these input signals in accordance with the control signal from the control signal input buffer circuit 24 and supply them to a predetermined internal circuit.

Control signals input from an external CPU or the like to the flash memory of this embodiment include, for example, a reset signal RES, a chip select signal CE, and a write control signal W.
E, an output control signal OE, a command enable signal C for indicating a command or data input or an address input
DE, system clock SC, and the like.

As an external device for controlling the flash memory of the above embodiment, a general-purpose microcomputer LSI can be used as long as it has an address generation function and a command generation function.

FIG. 2 shows a specific example of the memory array 11. The memory array 11 of this embodiment is composed of two mats, and FIG. 2 shows a specific example of one of the memory mats. As shown in the figure, each memory mat has n (for example, 128) memory cells (a MOSFE having a floating gate) arranged in a column direction and having a source and a drain connected in common in a parallel form.
T) A plurality of memory columns MCC including MC1 to MCn are arranged in a row direction (word line WL direction) and a column direction (bit line MBL direction).

Each memory column MCC has n memory cells M
The drains and sources of C1 to MCn are connected to a common local bit line LBL and a common local source line LSL, respectively.
The main bit line MBL can be connected to the common source line CSL via the SFET Qs1 and the local source line LSL via the selection MOSFET Qs2. The memory array is divided into a plurality of blocks, and a local bit line LBL provided for each block is connected to a selection MOSFET.
By being connected to the main bit line MBL via Qs1, the power consumption required for precharging the bit line can be reduced.

Of the plurality of memory columns MCC sharing the local bit line LBL and the local source line LSL, those arranged in the word line direction (referred to as one block) have the same well on the semiconductor substrate. Area WE
LL, and when erasing data, the well region W
A potential such as 0 V is applied to the ELL and the local source line LSL, and 16.5 is applied to the word line sharing the well region.
By applying a voltage such as V, batch erasing can be performed in block units.

When erasing data, select MOSFET
Qs2 is turned on, and 0 is applied to the source of each memory cell.
It is configured such that a potential of V is applied. At this time, the selection MOSFET Qs1 is turned off, and the drain is applied with a high voltage of 16.5 V to the control gate, so that the voltage on the source side is transmitted through the channel of the memory cell that is turned on, so that the voltage is set to 0 V. Potential.

On the other hand, at the time of data writing, a negative voltage such as -12.6 V is applied to the word line connected to the selected memory cell, and the main bit line MBL corresponding to the selected memory cell is set at 4 V. Bit line LBL connected to the selected memory cell and set to the potential
The upper selection MOSFET Qs1 is turned on, and 4 V is applied to the drain. However, at this time, the selection MOSFET Qs2 on the local source line LSL is off.

At the time of data reading, a voltage such as a read voltage VRc (for example, 2.5 V) is applied to the word line connected to the selected memory cell, and the main bit corresponding to the selected memory cell is read. Line MBL is 1V
Select MOSFE on the local bit line LBL which is precharged to a potential as described above and to which the selected memory cell is connected.
T Qs1 is turned on. Then, at this time, the selection MOSFET Qs2 on the local source line LSL is turned on, and the ground potential (0 V) is applied.

FIG. 3 shows the timing of reading data from the memory array.

When the read control sequence is started, first, the selected word line WL is raised to a read level such as 2.5 V, and the control signal SiD is changed to a high level to select a block in the block having the selected word line. MOS
The FET Qs1 is turned on (timing t1). Next, the precharge MOSFET Qp1 is turned on by setting the control signal RPCL to the high level, and the main bit line MBL and the local bit line LBL connected to the turned on Qs1 are precharged at 1V. Precharged to voltage Vp (at timing t
2).

Subsequently, the precharge control signal RPCR of the mat opposite to the selected mat, that is, the mat on the reference side is set to a high level, so that the precharge MOSF
ETQp2 is turned on, and main bit line MBL is precharged (timing t3). At this time, the precharge voltage of the reference side mat is Vp / 2 (= half of the precharge voltage Vp (= 1 V) of the selected side mat.
0.5V). Thereafter, the precharge control signals RPCL and RPCR are changed to low level, so that the precharge MOSFETs Qp1 and Qp2 are turned off (timing t4).

Then, the control signal SiS is changed to the high level, and the common source side selection MOSFET Qs2 is turned on (timing t5). Then, in a memory cell having a low threshold voltage according to the threshold voltage of the memory cell selected at that time, a current flows from the bit line to the common source line, and the potential of the main bit line MBL is set to the ground point ( 0V), and no current flows in the selected memory cell having a high threshold voltage, so that the potential of the bit line does not decrease and is 1
V. The potential of the bit line and the potential of the bit line of the mat on the opposite side (0.5 V) are amplified by sense latch circuit SLT, and the read data is read by sense latch SLT
Is held. The data held in the sense latch SLT is thereafter transmitted to an output circuit when a column switch (not shown) connected to the main bit line MBL is turned on, and is output to the outside.

Next, a description will be given of a design method for developing a nonvolatile semiconductor memory circuit having a large storage capacity while maintaining the same circuit format in the flash memory having the above configuration.

As described above, the logic in the same row
Memory cell and logic for storing data corresponding to "1"
The apparent threshold voltage of the memory cell shifts due to imbalance of the memory cell storing the data corresponding to "0", the apparent threshold shift amount of the memory cell is ΔVth, and the bit line pre- Assuming that the charge voltage is Vp, the parasitic capacitance of the bit line is Cs, and the time required for discharging the bit line is Td, approximately ΔVthｐ (Vp · Cs)
/ Td. Therefore, if simply increasing the number of memory cells connected to one local bit line LBL, the parasitic capacitance Cs of the bit line increases, and the threshold shift amount ΔVth increases from the above relational expression. You can see that.

On the other hand, there is a correlation between the threshold shift amount ΔVth and the bit line discharge time Td as shown in FIG. That is, the longer the discharge time Td, the smaller the threshold shift amount ΔVth can be. Further, it has been found that the correlation between the shift amount ΔVth of the threshold value and the bit line discharge time Td changes depending on the magnitude of the bit line precharge voltage Vp.

FIG. 6 shows a correlation curve between the threshold shift amount ΔVth and the bit line discharge time Td when the precharge voltage Vp of the bit line is changed. In FIG. 6, the uppermost curve A shows the correlation when the precharge voltage Vp is high, the lowermost curve C shows the correlation when the precharge voltage Vp is low, and the middle curve B shows the correlation when the precharge voltage Vp is intermediate. The correlation is shown. Note that the precharge voltage Vp
Is changed accordingly, the precharge voltage of the bit line on the opposite side, that is, the reference side is also changed, and is set to a value such as Vp / 2.

In this embodiment, the precharge voltage of the bit line is Vp1, the parasitic capacitance of the bit line is Cs1, the discharge of the bit line is Cs1, and the bit line is discharged in the memory array having the configuration as shown in FIG. Time Td
1, the precharge voltage of the bit line of the storage circuit to be developed is Vp2, and the parasitic capacitance of the bit line is Cp.
s2, and when the discharge time of the bit line is Td2, (Vp1 · Cs1) / Td1 = (Vp2 · Cs)
2) The circuit is designed such that the bit line precharge voltage Vp2, the bit line parasitic capacitance Cs2, and the bit line discharge time Td2 are set so that the relationship of / Td2 is maintained.

More specifically, since the parasitic capacitance Cs2 of the bit line becomes larger than the parasitic capacitance Cs1 of the bit line of the conventional circuit due to the increase in the capacity of the memory array, the discharge time Td2 of the bit line is increased or the bit line pre-charge time is reduced. A design is performed such that the charge voltage Vp2 is reduced to a target threshold shift amount. Further, when the target threshold shift amount cannot be obtained even if the discharge time Td2 of the bit line is extended to the allowable limit, the bit line precharge voltage Vp2 is lowered to the target threshold shift amount. Perform such a design.

That is, if the discharge time Td2 of the bit line is too long, the write time becomes longer and the design specification is not satisfied, so that there is an allowable limit naturally.
Therefore, as shown in FIG. 7, first, the discharge time of the bit line is increased to the allowable limit Tdc, and when the discharge time does not reach the target threshold shift amount adjustment range (the hatched area in FIG. 7), As shown in FIG. 8, a design is made such that the amount of shift of the threshold value is reduced to the matching range by lowering the bit line precharge voltage Vp2.

As described above, if the target threshold shift amount cannot be obtained even if the discharge time Td2 of the bit line is first extended to the allowable limit, instead of lowering the bit line precharge voltage Vp2. First, the bit line precharge voltage Vp2 is lowered to its lower limit,
Still (Vp1 · Cs1) / Td1 = (Vp2 · Cs)
2) When the relationship of / Td2 cannot be maintained, the design may be made so that the bit line precharge voltage Vp2 is lowered and the bit line discharge time Td2 is lengthened.

Here, the bit line precharge voltage Vp
As a method of adjusting 2, for example, there is a method of changing a resistance ratio when a precharge voltage is generated by a resistance dividing circuit. Also, the bit line discharge time T
As a method of increasing the length d2, for example, the gate control signal RPCR of the precharge MOSFET (Qpc2 in FIG. 2) on the reference side falls and the reference voltage (V
A method of delaying the timing of cutting p / 2) or lowering the precharge voltage on the reference side (to Vp / 2 or less) can be considered.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, a case has been described in which the present invention is applied to a flash memory in which data "1" corresponds to a high threshold voltage of a storage element and the threshold voltage of the storage element is lowered by writing. The present invention is not limited thereto, and is also applicable to a case where data "0" corresponds to a high threshold voltage of a storage element or a flash memory of a type in which the threshold voltage of a storage element is increased by writing. be able to.

Further, in the present invention, when the threshold voltage of a memory cell is changed to four levels of threshold voltages as shown in FIG. 9, four-valued data, ie, 2-bit data, is stored in one memory cell. Can also be applied. VR1,
VR2 and VR3 are word line levels at the time of reading. In such a multi-level flash memory, the interval between the peaks of the threshold distribution is narrower than in the case of binary, and the shift amount of the threshold due to the magnitude of the current flowing toward the common source line is large. If so, erroneous reading of data is likely to occur, so it is effective to apply the present invention to suppress the shift amount of the threshold.

In the above description, mainly the case where the invention made by the present inventor is applied to a batch erase type flash memory which is a field of application as the background has been described. However, the present invention is not limited to this. The design of a non-volatile memory circuit having a storage element having a control gate and a floating gate can be widely used in general.

[0047]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, in a nonvolatile semiconductor memory circuit including a nonvolatile memory element (memory cell) having a floating gate and storing data depending on the level of a threshold voltage, an apparent threshold of the memory element is provided. It is possible to prevent reading of erroneous data by reducing the amount of value shift.

[Brief description of the drawings]

FIG. 1 is an overall block diagram schematically showing an embodiment of a flash memory to which the present invention is applied.

FIG. 2 is a circuit diagram showing a configuration example of a memory array of a flash memory to which the present invention is applied.

FIG. 3 is a timing chart showing timings of various signals at the time of reading data in the memory array of the embodiment.

FIG. 4 is an explanatory diagram showing how an apparent threshold value of a memory cell shifts according to the magnitude of a current flowing to a common source line in a flash memory.

FIG. 5 is a graph showing a relationship between a shift amount of a threshold value of a memory cell and a discharge time of a bit line in a flash memory.

FIG. 6 is a graph showing a relationship between a shift amount of a threshold value of a memory cell and a bit line discharge time when a bit line precharge voltage is changed in a flash memory.

FIG. 7 is a graph showing how a shift amount of a threshold value of a memory cell changes when a bit line discharge time is lengthened in a flash memory.

FIG. 8 is a graph showing how a shift amount of a threshold value of a memory cell changes when a bit line precharge voltage is reduced in a flash memory.

FIG. 9 is a graph showing a relationship between a threshold voltage distribution of a memory cell and a read voltage in a multilevel (quaternary) flash memory.

[Description of Signs] 11 Memory array 12 Data register 13 Write circuit 14 Address register 15 X decoder 21 Command register & decoder 22 Sequencer WL Word line MC Memory cell MBL Main bit line LBL Local bit line LSL Local source line CSL Common source line SLT Sense latch circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AA03 AB01 AC01 AD05 AD11 AE08 5F001 AA01 AB02 AC02 AD51 AE03 AF05 5F083 EP02 EP22 ER03 ER06 ER09 ER14 ER15 ER22 ER30 GA11 LA09 LA10 LA20

Claims (5)

[Claims] When developing a nonvolatile semiconductor memory circuit having a large storage capacity in the same circuit format as a memory circuit whose reliability has already been confirmed, including a nonvolatile memory element for storing data at a high or low threshold voltage. The precharge voltage of the bit line of the memory circuit whose reliability has already been confirmed is Vp1,
The parasitic capacitance of the bit line is Cs1, the discharge time of the bit line is Td1, the precharge voltage of the bit line of the storage circuit to be developed is Vp2, the parasitic capacitance of the bit line is Cs2, and the discharge time of the bit line is Td1.
When d2, (Vp1 · Cs1) / Td1 = (V
p2 · Cs2) / Td2 so that the bit line precharge voltage Vp2 and the bit line parasitic capacitance Cs are maintained.
2. A method of designing a nonvolatile semiconductor memory circuit, wherein a circuit is designed with a bit line discharge time Td2 set. 2. (Vp1 · Cs1) / Td1 = (Vp2
2. The method for designing a nonvolatile semiconductor memory circuit according to claim 1, wherein a design is made to extend the discharge time Td2 of the bit line so that the relationship of Cs2) / Td2 is maintained. 3. (Vp1 · Cs1) / Td1 = (Vp2
2. The method for designing a nonvolatile semiconductor memory circuit according to claim 1, wherein a design for lowering the bit line precharge voltage Vp2 is performed so that a relationship of Cs2) / Td2 is maintained. 4. First, a bit line discharge time Td
3. The design of the nonvolatile semiconductor memory circuit according to claim 2, wherein a design is made to extend the bit line precharge voltage Vp2 if the relation of the above equation is not obtained even if the relation of the above equation is not obtained. Method. 5. The method according to claim 1, wherein the bit line precharge voltage Vp2 is first reduced to its permissible limit, and if the relation of the above equation is not obtained, the bit line discharge time Td2 is lengthened. 4. The method for designing a nonvolatile semiconductor memory circuit according to item 3.