JP2001035089A - Disk player - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfactorily achieve the correcting of the phase of a reproducing clock even when a dropout is generated in reference patterns for correcting the phase of the reproducing clock. SOLUTION: The reproducing clock PLCK generated in a PLL circuit 108 in accordance with the mark signal (TPP) on a disk 101 is normally phase- corrected in a clock phase correcting circuit 112 in accordance with the phase deviation value ERR of reference patterns, however, when a dropout is detected in the reference patterns, the updating of a correcting amount by a correcting amount judging circuit 111 is prohibited and the phase of the reproducing clock PCLK is corrected in accordance with a existing correcting amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk drive for generating an external clock based on a reproduction signal from a disk and reproducing data using the external clock.

[0002]

2. Description of the Related Art Conventionally, in a disk medium such as a magneto-optical disk, phase information (mark) such as a clock pit or a clock mark is previously formed on a recording track. It is generated based on a reproduction mark signal of a pit or a clock mark.

FIG. 2 shows an example of a magneto-optical disk on which clock marks have been formed in advance. In such a disk, spiral grooves (grooves) are formed at a predetermined pitch, and data is recorded on this groove and a plane portion (land) between adjacent grooves.

As shown in FIG. 2, fine clock marks (FCM) are formed on the grooves and the lands so as to be radially arranged. Among them, the FCM on the groove is on the same plane as the land, and the FCM on the land is a depression having the same depth as the groove.

When recording or reproducing data, the FC
As the beam scans M, the intensity of the reflected beam changes in a pulsed fashion, thus producing a pulse signal at the sensor output that receives the reflected beam. The external clock is generated by a PLL (Phase Locked Loop) circuit based on the pulse signal.

However, when a clock is generated based on external phase information (reproduced mark signal) as described above, the generated clock and the reproduced clock may vary depending on the temperature characteristics of the disk, recording conditions, or various characteristics of the disk recording / reproducing apparatus. A phase shift may occur with the signal.

Therefore, a reference pattern is recorded in advance in a head area of each data area (an area between one clock mark and the next clock mark), and the external clock is recorded based on a reproduction signal of the reference pattern. Is performed.

[0008]

However, in the method of adjusting the phase of an external clock using the above-described reference pattern, if a dropout occurs in a recording portion of the reference pattern, the phase is shifted so as to promote a phase shift. Corrections may be made. For this reason, in the above-described conventional technology, there is a problem that data in the data area in which the dropout has occurred cannot be satisfactorily reproduced.

In view of the above, the present invention is intended to generate a phase correction of a reproduced clock satisfactorily even if a dropout occurs in an area of a reference pattern.

[0010]

Means for Solving the Problems In order to solve the above problems, the present invention has the following features.

According to a first aspect of the present invention, there is provided a disk reproducing apparatus for reproducing data from a disk in which a mark serving as a reference for clock generation is formed on a track, a clock generating means for generating a reproduction clock based on a reproduction signal of the mark, A clock correction unit configured to correct a phase shift of the clock based on reference pattern data recorded on the track; a dropout detection unit configured to detect a dropout on the track; Clock correction inhibiting means for inhibiting the correction of the clock phase by the clock correcting means.

According to a second aspect of the present invention, in the first aspect, the reference pattern data is recorded at the beginning of a recording frame unit, and the clock correction means corrects the clock phase when reproducing the reference pattern data. It is characterized in that the value is updated.

According to a third aspect of the present invention, in the second aspect, the clock correction prohibiting unit prohibits updating of the clock phase correction value during the dropout detection period, and the clock correction unit executes the updating. During the prohibition period, the clock phase is corrected based on the existing correction value.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

First, the configuration of the magneto-optical disk according to the present embodiment will be described with reference to FIGS.

FIG. 2 shows the configuration of a magneto-optical disk. As described in the above related art, a groove and a land are spirally formed on the disk, and a fine clock mark (FCM) is formed on the groove and the land at a constant rotation angle. ) Is formed. Here, a segment is assigned with one FCM to the next FCM as one recording unit. Then, one frame is constituted by collecting a series of 39 segments.

FIG. 3 shows the structure of the frame. As shown, each segment is 522 DCB (Da
ta Clock Bit). Note that the FCM field to which the FCM is assigned is set to 12 DCB.

The first segment (Segment) in each frame
0) is for recording the address of the frame. The record of the address is stored in the address field (Addr
In ess), the amplitude on one side of the groove or land in the radial direction of the disk according to the address value (wobble)
This is done by letting The segment (Se
In the address field of gment0), data recording / reproduction by the magneto-optical effect is not performed, and only address recording by the wobble is performed.

The second to 39th segments from the top (Segment1 to Segment38) are for recording a header and user data. The second segment (Segment1) includes an FCM field (FCM), a prewrite field (Pre-write), and a header field (H
eader), a data field (Data), and a post-write field (Post-write). In addition, the 3rd to 39th (Segment2 to Segment38)
Field (FCM), pre-write field (Pre-writ
e), a data field (Data), and a post-write field (Post-write) are assigned.

The number of data clock bits in each field is as shown. Here, the pre-write field (Pr
e-write), header field (Header), data field (Data), post-write field (Post-write)
Is recorded using the magneto-optical effect.

Of the above fields, pre-write (Pre-
write) is a fixed pattern for indicating the writing of data, for example, data of “0011” is recorded.
The post-write (Post-write) is a fixed pattern for indicating the end of data, for example, data of "1100" is recorded. In addition, the data field contains
For example, user data from an external source is recorded.

In the header field, a fixed pattern for confirming the start position of the data field and a fixed pattern for performing phase correction of the reproduction clock are recorded. Among them, the latter fixed pattern (training pattern) for phase correction repeats “1100” a predetermined number of times. When the training pattern is reproduced at the time of data reproduction, a sinusoidal reproduction RF signal having a period of 4 DCB is obtained. The phase correction of the reproduced clock is performed based on the reproduced RF signal of the training pattern.

Next, the principle of such phase correction will be described with reference to FIG.
This will be described with reference to FIGS.

The waveform signal shown in the figure is a reproduced RF signal when the above-mentioned training pattern is reproduced. Also, the circles in the figure are the clock timings of the reproduction clock. 5 shows a case where the clock phase is proper, FIG. 6 shows a case where the clock phase is ahead of the reproduced RF signal, and FIG. 7 shows a case where the clock phase is delayed with respect to the reproduced RF signal. Xi + 1, Xi, and Xi-1 are sample values when the reproduced RF signal is sampled at the clock timing. Yi is an average value of the sample values Xi-1 and Xi + 1.

ERR is the difference between Xi and Yi (ERR = Yi−
Xi), and represents the phase shift amount between the reproduced RF signal and the clock. That is, when the clock phase is proper (FIG. 5), ERR = 0, and the phase shift between the two is zero. On the other hand, when the clock phase is ahead of the reproduced RF signal (FIG. 6), ERR> 0, and when the clock phase is delayed with respect to the reproduced RF signal (FIG. 7), ERR. <0. Therefore, if ERR> 0, the clock is controlled to be delayed, and if ERR <0, the clock is controlled to be advanced, so that an appropriate corrected clock can be obtained by approaching the state shown in FIG. become able to.

In the above phase correction, if a dropout occurs due to a scratch or the like in the training pattern area,
The reproduced RF signal is deformed as shown in FIG. 8 or FIG. 9, and accordingly, ERR is disturbed. For example, FIG. 8 shows that dropout occurs when the clock phase precedes the reproduced RF signal (corresponding to FIG. 6 above). In this case, ERR <0, and dropout occurs. The polarity will be exactly opposite to the ERR when it does not occur.

FIG. 9 shows a case where a dropout occurs when the clock phase is proper (corresponding to FIG. 5). In this case, ERR <0 despite the proper phase. And the inconvenience that the clock is corrected occurs.

In this embodiment, the inconvenience at the time of occurrence of the dropout is eliminated by employing the configuration shown in FIG. Hereinafter, a magneto-optical reproducing device according to an embodiment will be described with reference to the drawings.

In FIG. 1, reference numeral 101 denotes the above-mentioned magneto-optical disk. Here, the magneto-optical disk 101 employs a signal transmission method based on PR (partial response). That is, when the recording density of the magneto-optical disk 101 is increased, code interference occurs between adjacent reproduced RF signals.
A method of transmitting a signal with intersymbol interference without preventing such intersymbol interference is a partial response system.
Therefore, a reproduced RF signal when reproducing the magneto-optical disk 101 is a PR system (for example, a PR (1, 1) system).
, A signal waveform in which intersymbol interference occurs is obtained. Obtaining binary reproduction data of "1" and "0" from the reproduced RF signal is achieved by Viterbi decoding sample value (multi-level) data of the reproduced RF signal, as described later.

Reference numeral 102 denotes a pickup which outputs a reproduced RF signal, a tangential push-pull signal (TPP) and a sum signal (SUM) by optically scanning the magneto-optical disk.

The reproduction RF signal is a signal corresponding to the Kerr rotation angle of the reproduction beam due to the magneto-optical effect.
(Partial response) method. The TPP signal is a signal corresponding to the intensity distribution in the scanning direction (the intensity distribution in the longitudinal direction of the groove or the land) in the reflected beam reflected from the disk. The SUM signal is a signal corresponding to the intensity of the reflected beam reflected from the disk.

Since the specific configuration of the pickup 102 is well known, description thereof will be omitted.

Reference numeral 103 denotes an equalizer, which includes a filter for equalizing the waveform so that the reproduced RF signal has a frequency characteristic that can be demodulated. That is, the reproduced RF signal is shaped so as to approximate a PR system interference waveform.

Reference numeral 104 denotes an AD converter, and an equalizer 103
Is output as sampled value (multi-valued) data obtained by sampling the output of FIG.

A header detection circuit 105 detects the position of the header field of Segment1 from the sample value,
A timing signal is output to each signal processing unit. Here, the header field is detected by detecting the fixed pattern (fixed pattern for confirming the start position of the data field) recorded in the header field.

Reference numeral 106 denotes a data demodulation circuit which demodulates data in a data field of each segment in accordance with a timing signal from the header detection circuit 105 and outputs reproduced data. Here, the data demodulation circuit 106 is the AD converter 1
It performs Viterbi decoding of the sample value (multi-value) data from No. 04 to convert it into binary, and performs digital demodulation for demodulating digital modulation performed at the time of recording.

An error correction circuit 107 corrects an error in the demodulated data using an error correction code added to the demodulated data. The error-corrected demodulated data is transferred to a reproduction circuit (not shown).

Reference numeral 108 denotes a PLL circuit,
The data clock PCLK is generated from the TPP signal from the second TPP. Here, the TPP signal has a pulse waveform at the timing when the reproduction beam scans the FCM. PLL circuit 10
8 is a data clock PCL corresponding to the pulse waveform.
Generate K.

Reference numeral 109 denotes a dropout detection circuit,
Detect dropout by monitoring M signal,
It outputs a dropout detection signal (DP). here,
The SUM signal has a pulse waveform at the timing when the reproduction beam scans the dropout. The dropout detection circuit 109 outputs a DP signal according to the detection of the pulse waveform.

Reference numeral 110 denotes a phase shift detection circuit, which is shown in FIGS.
Based on the phase shift detection principle described with reference to FIG.
The phase shift amount ERR is output. The generation of the phase shift amount is executed during a period in which the training pattern of the header field of the above-described Segment 1 is reproduced. The timing signal indicating the training pattern reproduction period is input from the header detection unit 105 to the phase shift detection circuit 110.

Reference numeral 111 denotes a correction amount determination circuit which outputs a clock PC from the PLL circuit 108 in accordance with the phase shift amount ERR.
The LK correction control data SELCK is updated and output. However, when the dropout detection circuit 109
While the P signal is being output, the updating of the correction control data is stopped. The correction control data SE
The update and output of LCK are executed during a period in which the training pattern of the header field in Segment 1 is reproduced. The timing signal TN indicating the training pattern reproduction period is input from the header detection unit 105 to the correction amount determination circuit 111.

A clock phase correction circuit 112 receives the correction control data SELCK from the correction amount determination circuit 111 and corrects the phase of the clock PCLK from the PLL circuit 108.

According to the magneto-optical reproducing apparatus shown in FIG. 1, even when the reproducing apparatus is reproducing a training pattern, the correction amount is determined while the drop-out is detected by the drop-out detecting circuit 109. Circuit 1
11, the correction control data SELCK is not updated. Therefore, even if the reproduced RF signal is disturbed due to, for example, dropout as shown in FIG. 8 or FIG. 9, erroneous clock correction is not performed. Output can be realized. When no dropout occurs in the training pattern, the correction control data SELCK is sequentially updated in the correction amount determination circuit 111, and the phase of the clock PCLK is corrected by the clock phase correction circuit 112 in response to the update. Since the reproduction RF signal of the data field is properly sampled by the AD converter 104 by the correction clock RCLK, the data of the frame can be reproduced properly.

FIG. 4 is a diagram showing a specific configuration example of the phase shift detection circuit 110.

In the figure, reference numerals 41 and 42 denote flip-flops, 43 denotes an adder, and 44 denotes the output value of the adder 43 by 1/2.
A reference numeral 45 denotes a subtractor. Xi-1, Xi, Xi + 1, and Yi shown in FIGS.
Are output on the signal lines shown in FIG. Therefore, the phase shift amount ERR is output from the subtractor 45.

FIG. 10 is a diagram showing a specific configuration example of the correction amount determination circuit 111.

In the figure, reference numeral 51 denotes a level judging circuit which operates according to the timing signal TN to obtain a phase shift amount ER.
It is determined whether R is within a predetermined range (within a range of plus and minus thresholds), is larger than the range, or is smaller than the range. Here, the operation signal is output to the gate 52 only when the phase shift amount ERR is out of the predetermined range. At this time, when ERR is larger than a predetermined range, m
An up command is issued to the + 1-ary counter 53, and a down command is issued to the m + 1-ary counter 53 when the ERR is smaller than a predetermined range.

Reference numeral 52 denotes a gate, which outputs an operation instruction to the m + 1-ary counter 53 when an operation signal is input from the level determination circuit 51 and the DP signal is at a high level (a state in which no dropout is detected).

Numeral 53 denotes an (m + 1) -number counter.
2 and an up command or a down command is input from the level determination circuit 51,
The count value is incremented or decremented by one, and correction control data SELCK, which is the count value, is output. Here, the correction control data is an m + 1 modular multiplication system in which “1” is added or subtracted by a count-up or count-down command. Therefore, by preparing and selecting m + 1 types of clocks having a phase obtained by dividing one cycle of the reproduction clock by m + 1, a correction clock RCLK can be obtained.

According to the correction amount determination circuit shown in FIG. 10, the counter 53 does not operate when a dropout occurs, and the value of the correction control data SELCK is held and output as it is. Therefore, the disturbance of the correction clock due to dropout can be suppressed.

FIG. 10 shows an example of a correction amount judgment circuit using a counter. Instead, a configuration using a loop filter, a phase judgment based on an average phase shift amount, or the like is adopted. Is also possible.

FIG. 11 shows a specific configuration example of the phase correction circuit 112.

In the figure, reference numeral 61 denotes a phase delay circuit which receives a reproduced clock PCLK as an input and has a delay amount m at equal intervals.
+1 types of delayed clock signals CLK0 to CLKm are output. Reference numeral 62 denotes a selection circuit which outputs a delay clock CL according to the correction control data input from the correction amount determination circuit 111.
One of K0-CLKm is selected and the correction clock RC
Output as LK. Here, the correction control data SELC
If K is data output from the m + 1-ary counter 53 shown in FIG. 10, a clock corresponding to the value indicated by the data is selected from the delay clocks CLK0 to CLKm. Therefore, the correction control data SELC
As the value of K increases, a more delayed clock is selected.

The phase correction circuit 112 can be variously modified in addition to the configuration shown in FIG. For example, it is also possible to adopt a configuration in which the PLL is multiplied based on the reproduction clock PCLK and the phase is adjusted by adding an offset according to the correction control signal SELCK.

Although the embodiment of the present invention has been described above, the present invention is not limited to the embodiment, and various other modifications are possible.

For example, in the configuration shown in FIG.
Is performed before the AD conversion processing. Alternatively, the equalization processing according to the PR may be performed after the AD conversion processing. FIG. 12 shows an example of the configuration in the case of FIG. In the figure, reference numeral 120 denotes a digital equalizer which performs equalization processing according to PR on sampled value (multi-valued) data sampled by the AD converter 104. According to this configuration, the sampling value data that has not been subjected to the PR equalization processing is supplied to the phase shift detection circuit 110, and the reproduced RF signal when the training pattern is reproduced is a repetition data of “1100”. Therefore, the influence of the waveform interference is small, and therefore, a sine wave signal having a period of 4 DCB is obtained without performing PR equalization. Therefore, when the training pattern is reproduced, substantially the same sample value data as in the above embodiment is supplied to the phase shift detection circuit 110.

Of course, the sample value data after the PR equalization by the digital equalizer 120 may be supplied to the phase shift detection circuit 110. In FIG.
A configuration example in such a case will be described.

In FIGS. 12 and 13, FIG.
The same reference numerals are given to the same parts as those described above, and the description is omitted.

In addition, it goes without saying that the present invention can be variously modified within the scope of the technical idea.
For example, although the above description has been given by taking the PR type magneto-optical disk as an example, the present invention may be applied to a data transmission type magneto-optical disk in which waveform interference is suppressed, and a recording / reproducing apparatus of a phase change type disk. It is also possible to apply

In the above embodiment, the SUM signal is used for dropout detection. However, a signal having a similar effect, such as a focus error signal or a tracking error signal, may be used.

[0061]

As described above, according to the present invention, when the dropout is detected, the correction of the clock phase by the phase correction data is prohibited, so that the reproduced signal is disturbed by the dropout and the phase shift of the reproduced clock is promoted. Therefore, data can be reproduced with an appropriate clock.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a magneto-optical reproducing device according to an embodiment.

FIG. 2 is a configuration diagram of a magneto-optical disk according to the embodiment.

FIG. 3 is a data configuration diagram of a magneto-optical disk according to the embodiment.

FIG. 4 is a configuration diagram of a phase shift detection circuit according to the embodiment;

FIG. 5 is a diagram illustrating a principle of detecting a phase shift according to the embodiment;

FIG. 6 is a diagram illustrating a principle of detecting a phase shift according to the embodiment;

FIG. 7 illustrates a principle of detecting a phase shift according to the embodiment.

FIG. 8 is a diagram illustrating a principle of detecting a phase shift according to the embodiment;

FIG. 9 is a diagram illustrating a principle of detecting a phase shift according to the embodiment;

FIG. 10 is a configuration diagram of a correction amount determination circuit according to the embodiment.

FIG. 11 is a configuration diagram of a phase correction circuit according to an embodiment.

FIG. 12 is a configuration diagram of a magneto-optical reproducing device according to another embodiment.

FIG. 13 is a configuration diagram of a magneto-optical reproducing device according to another embodiment.

[Explanation of symbols]

 Reference Signs List 101 magneto-optical disk 102 pickup 103 equalizer 104 AD converter 105 header detection circuit 106 data demodulation circuit 107 error correction circuit 108 PLL circuit 109 dropout detection circuit 110 phase shift detection circuit 111 correction amount determination circuit 112 clock phase correction circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiki Kuma 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 5D044 BC02 CC04 GM19

Claims (3)

[Claims] 1. A disk reproducing apparatus for reproducing data from a disk having a mark formed on a track as a reference for clock generation, a clock generating means for generating a reproduction clock based on a reproduction signal of the mark, and recording on the track. Clock correction means for correcting a phase shift of the clock based on the obtained reference pattern data; dropout detection means for detecting dropout on the track; and a clock by the clock correction means in response to the detection of the dropout. A disk reproducing apparatus comprising: a clock correction prohibiting unit that prohibits phase correction. 2. The method according to claim 1, wherein the reference pattern data is recorded at a head of a recording frame unit, and the clock correction unit updates the correction value of the clock phase when reproducing the reference pattern data. A disk reproducing device characterized by the above-mentioned. 3. The clock correction prohibiting unit according to claim 2, wherein the clock correction prohibiting unit prohibits updating of the clock phase correction value during the dropout detection period,
The disk reproducing apparatus according to claim 1, wherein the clock correction unit corrects a clock phase based on an existing correction value during the update prohibition period.