JPH056619A - Digital-data recording and reproducing apparatus - Google Patents

Abstract

PURPOSE:To judge the logics of multiple values in a partial response method accurately by judging the theory of digital data based on the levels of the reference data corresponding to the highest frequency and the lowest frequency. CONSTITUTION:The data outputted from an AD converter 48 are supplied into averaging circuits 61-64 of an operating circuit 52. A timing generator 42 generates clocks CLK1-CLK5 in synchronization with the data clocks from a PLL circuit 41 and supplies the clocks into the circuits 61-64. The rising edges of the clocks CLK1 and CLK2 are generated at the timings corresponding to the positive and negative peak values of a regenerating reference signal corresponding to the highest frequency. The rising edges of CLK3 and CLK4 are generated at the timings corresponding to the negative and positive peak values of a regenerating reference signal corresponding to the lowest frequency. The averaging circuits 61-64 operate the average value of these peak values. Subtracting circuits 65 and 66 obtain the amplitudes G and F of the reference signals corresponding to the highest and lowest frequencies. A dividing circuit 67 operates the numerical aperture G/F and stores the result in ROMs 68 and 69.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data recording / reproducing apparatus suitable for use in, for example, a magneto-optical disk device.

[0002]

2. Description of the Related Art In a magneto-optical disk, a partial response method may be used when recording data digitally. When the recording is performed by the partial response method, the reproduction signal is a ternary signal of 1, 0 or -1. When reading this reproduction signal, threshold levels are set between -1 and 0 and between 0 and 1, respectively, and it is determined which logic is based on the threshold level.

[0003]

Information is not always recorded continuously on a magneto-optical disk.
After the predetermined information is recorded, some days have passed and then other information is recorded. Therefore, the recording condition is not always constant. For example, when the power of the laser beam during information recording changes, the size of the mark (pit) formed on the magneto-optical disk also changes. Further, since the magneto-optical disk once recorded is not always reproduced in the same device, its reproduction condition (for example, frequency characteristic) may vary during reproduction.

As described above, since the level of the reproduced signal changes when the conditions during recording or reproduction change,
If the threshold level for determining the logic is fixed, there is a risk that the logic may be erroneously determined.

The present invention has been made in view of such a situation, and makes it possible to accurately determine a logic.

[0006]

A digital data recording apparatus according to the present invention is a digital data recording apparatus, wherein, of frequencies included in digital data,
Reference data corresponding to the highest frequency, generating means for generating reference data corresponding to a sufficiently low frequency, and recording means for arranging the reference data at the beginning of a predetermined data block and recording it on a recording medium are provided. Characterize.

In the embodiment, this generating means is composed of a reference generating circuit 51, and the recording means is composed of a write encoder 37, a drive circuit 36 and a magnetic head 35.

The digital data reproducing apparatus of the present invention has a reading means for reading reference data corresponding to the highest frequency and a sufficiently low frequency among frequencies included in the digital data, a level of the reference data corresponding to the highest frequency, and a sufficient level. It is characterized by further comprising: a determining unit that determines a threshold level for determining the logic of the digital data from the level of the reference data corresponding to the low frequency.

In the embodiment, the reading means is composed of averaging circuits 61 to 64, and the determining means is composed of an arithmetic circuit 67 and ROMs 68 and 69.

[0010]

In the digital data recording apparatus having the above structure, the reference data corresponding to the highest frequency among the frequencies included in the digital data and the reference data corresponding to the sufficiently low frequency are recorded on the recording medium. Therefore, it becomes possible to realize a recording medium capable of accurately determining the logic of digital data.

In the digital data reproducing device having the above structure, the threshold level for determining the logic of digital data is determined from the level of the reference data corresponding to the highest frequency and the level of the reference data corresponding to the sufficiently low frequency. . Therefore, it becomes possible to accurately determine the logic of digital data.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION In the digital data recording and reproducing apparatus of the present invention, digital data is recorded and reproduced by the partial response method. Therefore, first, the principle of recording / reproducing in the partial response system will be described.

FIG. 2 is a block diagram for explaining the principle of recording and reproduction by the partial response method. The encoder 1 encodes write data input from a circuit (not shown). The data encoded by the encoder 1 is supplied to and recorded on the magneto-optical disc 2. Then, the data reproduced from the magneto-optical disk 2 is supplied to the decoder 3, is decoded, and the data output from the decoder 3 is input to the multi-level discriminating circuit 4, and the logical 1
It is determined whether it is 0 or -1, and it is output as demodulated data.

Now, for example, the NRZI system (PR (1,-
Assuming that the digital data is modulated according to 1)), the encoder 1 can be configured as shown in FIG. That is, the encoder 1 includes an adder 11 that performs modulo 2 addition and a delay circuit 12 that delays the input data by 1 bit and outputs the delayed data. The adder 11 adds modulo 2 to the input data and the data supplied from the delay circuit 12, and outputs the result. The delay circuit 12 delays the output of the adder 11 and outputs it to the adder 11 again. In this way, for example, 0100110 as shown in FIG.
The input digital data consisting of 01000 is 01110
It is supplied to the magneto-optical disk 2 as 1110,000 and recorded.

On the other hand, the decoder 3 is composed of a subtractor 21 and a delay circuit 22, as shown in FIG. 4, for example. The data reproduced from the magneto-optical disk 2 is supplied to the subtractor 21, and after being delayed by one bit by the delay circuit 22, it is supplied to the subtractor 21. The subtractor 21 calculates the difference between the two inputs and outputs it to the multi-level discriminating circuit 4.

As a result, for example, 0111 shown in FIG.
The recording data of the magneto-optical disk 2 including the data of 01110000 is processed by the decoder 3 and 0100-1
Multi-value discrimination circuit 4 as ternary data of 100-1000
Will be supplied to.

The eye pattern of the data input to the multi-level discrimination circuit 4 is as shown in FIG. Multi-value discrimination circuit 4
Determines whether the data is -1 or 0 with reference to the threshold level TH1 in FIG. 6, and with reference to the threshold level TH2,
It is determined whether it is 0 or 1.

The decoder 3 shown in FIG. 4 can be omitted if it is substantially formed by a magnetic head, an amplifier, a high frequency compensating circuit, etc. in the reproducing system.

Next, an embodiment of the digital data recording and reproducing apparatus of the present invention will be described with reference to FIG.
In the figure, for example, a sample servo type magneto-optical disk 31 (corresponding to the magneto-optical disk 2 in FIG. 2).
Is rotated by a spindle motor 32 controlled by a spindle servo circuit 33, and data is recorded by an optical head 34 and a magnetic head 35.

The drive circuit 36 includes a write encoder 37.
The magnetic head 35 is driven according to the output of the. The write encoder 37 drives a laser drive circuit 39 via a laser power control circuit 38 to drive a laser diode (not shown) built in the optical head 34.

The signal reproduced from the magneto-optical disk 31 by the optical head 34 is input to the matrix amplifier 40 and reproduced from the magneto-optical area and the sum signal (PRF signal) obtained from the servo byte section of the magneto-optical disk 31. Signal (MORF signal) and a focus error signal. The PRF signal is input to the PLL circuit 41 and the A / D converter 43. The servo clock generated by the PLL circuit 41 is supplied to the timing generator 42, the A / D converter 43, the address decoder 44, the tracking error signal generation circuit 45, the tracking and focus servo circuit 46, and the gray code decoder 47, respectively. The data clock generated by the PLL circuit 41 is supplied to the write encoder 37, the timing generator 42, the A / D converter 48, the MO decoder 49, the reference generation circuit 51, the arithmetic circuit 52, and the like.

The output of the A / D converter 43 is supplied to the address decoder 44, the tracking error signal generation circuit 45, and the gray code decoder 47. Various timing signals generated by the timing generator 42 are supplied to the write encoder 37, the laser power control circuit 38, the SCSI / ECC circuit 50, the reference generation circuit 51, the arithmetic circuit 52, and the like.

The MORF signal is supplied to the MO decoder 49 via the A / D converter 48. The output of the MO decoder 49 is supplied to the SCSI / ECC circuit 50. The SCSI / ECC circuit 50 exchanges data with a host interface (not shown).

The arithmetic circuit 52 separates the reference data from the MORF signal, calculates the threshold levels TH1 and TH2 from the reference data, and supplies the threshold levels TH1 and TH2 to the multi-level discrimination circuit 4 of the MO decoder 49.

Next, the operation will be described. In the recording mode, recording data is input to the SCSI / ECC circuit 50 via a host interface (not shown). The SCSI / ECC circuit 50 performs processing such as adding an error detection code and interleaving on the input digital data, and outputs it to the write encoder 37. The write encoder 37 performs the above-described processing of the partial response system (processing of the encoder 1 in FIG. 2) on the input data, and then, the drive circuit 3 corresponding to the data.
The magnetic head 35 is driven via 6. Magnetic head 35
Applies an N pole (for example, logic 1) or S pole (logic 0) magnetic field to the magneto-optical disk 31 in accordance with the recording data.

On the other hand, the laser power control circuit 38
When a write command is input from the write encoder 37, the optical head 34 is transmitted via the laser drive circuit 39.
The laser diode of is emitted at the level in the recording mode. As a result, the laser light emitted from the optical head 34 is applied to the magneto-optical disk 31. In this way, digital data is recorded on the magneto-optical disk 31 by the so-called magnetic field modulation method.

Next, in the reproduction mode, the laser power control circuit 38 drives the laser diode of the optical head 34 via the laser drive circuit 39, and the level of the laser light emitted from the laser diode is changed to the reproduction level (level during recording). Weaker level). Then, the optical head 34 receives the reflected light of the laser light with which the magneto-optical disk 31 is irradiated, and the matrix amplifier 40
Outputs a MORF signal. This MORF signal is a signal reproduced from the magneto-optical recording layer on the magneto-optical disk 31. This MORF signal is converted to A by the A / D converter 48.
After being D / D converted, it is input to the MO decoder 49.

The MO decoder 49 operates the decoder 3 and the multilevel discriminator circuit 4 shown in FIG. The MO decoder 49 further decodes the data demodulated into three values of 1, 0 and -1 into the original digital data of 1 and 0. Then, the output of the MO decoder 49 is input to the SCSI / ECC circuit 50, subjected to processing such as deinterleaving, error detection and correction, and then output to a device (not shown) via the host interface.

In the above recording mode and reproduction mode, the servo circuit 46 causes the optical head 34 to operate based on the focus error signal output from the matrix amplifier 40.
The objective lens built in is driven to perform focus control. Further, the tracking error signal generation circuit 45 has a PR corresponding to the wobbled pit in the servo byte section.
Generate a tracking error signal from the F signal level,
It is output to the servo circuit 46. The servo circuit 46 controls the tracking of the optical head 34 in response to the tracking error signal. The address decoder 44 also reads the address data in the servo byte section and outputs the read result to the timing generator 42. The timing generator 42 supplies a timing signal to each part at a predetermined timing corresponding to the input address data.

Further, the gray code decoder 47 detects the gray code in the servo byte section and outputs the detection result to the servo circuit 46. The servo circuit 46 is
The position of the optical head 34 is determined from the output of the Gray code decoder 47, and the optical head 34 is moved to a desired track.

The PLL circuit 41 extracts from the output of the matrix amplifier 40 a signal from a clock pit that serves as a reference for executing various operations as described above, and generates a clock signal in synchronization with this. Then, this clock signal is supplied to various circuits.

Next, a method of setting the threshold level in the above embodiment will be described.

For example, the partial response P (1,1)
When is used, the eye pattern of the reproduction data is as shown in FIG. The threshold level TH1 for judging logic -1 and 0 is set on the line connecting the points A1 and A2, and the threshold level TH2 for judging logic 0 and logic 1 is set.
Is set on the line connecting the points B1 and B2. When the threshold level is set at this position, even if the clock shifts before and after it due to the jitter, the margin becomes maximum and the threshold becomes strong against the jitter. For example, it is possible to set each threshold level to a level intermediate between -1 and 0, or 0 and 1, but in that case, the width in the horizontal direction at the threshold level becomes narrower,
The margin for jitter is reduced accordingly. Therefore, it is preferable to set the threshold level on the line connecting the points A1 and A2 and the points B1 and B2 as in the embodiment.

The component with the smallest amplitude change in this eye pattern corresponds to the highest frequency among the frequency components included in the digital data. The component whose amplitude changes most greatly corresponds to the lowest frequency (or sufficiently low frequency). A value G obtained by dividing the amplitude G corresponding to the highest frequency by the amplitude F corresponding to the lowest frequency
/ F represents the aperture ratio. The aperture ratio corresponds to the MTF, and when the aperture ratio is determined, the threshold levels TH1 and TH2 corresponding thereto can be uniquely determined. That is, the threshold levels TH1 and TH2 can be obtained by calculating the aperture ratio.

Therefore, in this embodiment, the reference data corresponding to the highest frequency and the reference data corresponding to the lowest frequency (sufficiently low frequency) are recorded in advance on the magneto-optical disk 31.

The magneto-optical disk 31 is divided into a plurality of sectors, and data is recorded in each sector according to the format shown in FIG. That is, 1
Each sector is composed of 152 rows, and one row is composed of 5 bytes of data. Of the continuous 10 bytes of 2 rows, the first 2 bytes are the servo bytes, and the subsequent 8 bytes are the data bytes for recording various data. An ID code including an address and the like is arranged in the first two rows of data bytes. The second 2-row data byte contains the ALPC for controlling the preamble and laser power intensity.
The data is located. The third 2 rows of data bytes are used as a reference area, and reference data for setting the threshold level is recorded therein.

In the data bytes of the following 130 rows,
Data (video data, audio data, etc.) that should originally be recorded and reproduced is recorded. Then, the error detection and correction code (ECC) is added to the data bytes of the last 16 rows.
Is recorded.

The above-mentioned ID code is formed in advance on the magneto-optical disk 31 as pre-pits, and various data after the second row of the second row is recorded on the magneto-optical recording layer of the magneto-optical disk 31 whenever necessary. Will be recorded above.

Reference generation circuit 51 shown in FIG.
Generates reference data in synchronization with the clock generated by the PLL circuit 41, and outputs the reference data to the write encoder 37. The write encoder 37 arranges this reference data in the reference area of the format shown in FIG. 9, supplies it to the magnetic head 35 via the drive circuit 36, and records it on the magneto-optical disk 31. That is, the reference data is recorded at the beginning of each sector.

At the time of reproduction, the MO decoder 49 incorporates the multi-level discrimination circuit 4 shown in FIG. 2 in order to set the threshold level by referring to the reference data.
In this embodiment, an arithmetic circuit 52 is provided to generate the threshold levels TH1 and TH2 used in the multi-level discriminating circuit 4.

The arithmetic circuit 52 is constructed, for example, as shown in FIG. In this embodiment, the data output from the A / D converter 48 is supplied to the averaging circuits 61 to 64. The timing generator 42 generates clocks CLK1 to CLK5 in synchronization with the data clock input from the PLL circuit 41. Of these, the clocks CLK1 to CLK4 are supplied to the averaging circuits 61 to 64, respectively. As shown in FIG. 10, the clock CLK1 has a timing t corresponding to the positive peak value of the reproduction reference signal corresponding to the highest frequency.
The rising edges are generated at 1, t3, t5, and t7, and the rising edges of the clock CLK2 are generated at timings t2, t4, and t6 corresponding to the negative peak value of the reference signal corresponding to the highest frequency. Further, the rising edge of the clock CLK3 is generated at the timings t8, t9, t10 corresponding to the negative peak value of the reproduction reference signal corresponding to the lowest frequency, and the rising edge of the clock CLK4 is generated at the reproduction reference signal corresponding to the lowest frequency. Is generated at the timings t11, t12, t13, and t14 corresponding to the positive peak value of.

As a result, the averaging circuit 61 averages the level corresponding to the positive peak value of the reference signal corresponding to the highest frequency. Further, the averaging circuit 62 averages the negative peak value of the reference signal corresponding to the highest frequency. Further, the averaging circuits 63 and 64 calculate the average value of the negative peak value and the average value of the positive peak value of the reference signal corresponding to the lowest frequency, respectively.

The subtraction circuit 65 subtracts the output of the averaging circuit 62 from the output of the averaging circuit 61 to obtain the amplitude G (see FIG. 8) of the reference signal corresponding to the highest frequency. Further, the subtraction circuit 66 subtracts the output of the averaging circuit 63 from the output of the averaging circuit 64 to obtain the amplitude F (see FIG. 8) of the reference signal corresponding to the lowest frequency. Division circuit 6
Reference numeral 7 divides the output of the subtraction circuit 65 by the output of the subtraction circuit 66 to calculate the aperture ratio G / F.

The aperture ratio calculated by the division circuit 67 is stored in the ROM.
It is output to 68 and 69. The ROMs 68 and 69 respectively include threshold levels TH1 and T1 corresponding to the aperture ratio.
H2 is stored in advance. And ROM68,69
The threshold levels TH1 and TH2 corresponding to the aperture ratio G / F read by the registers 70 and 71, respectively.
Is supplied to. Registers 70 and 71 have timing t
The clock CLK5 generated in 15 is input, and the ROM is read at the timing of its rising edge.
Threshold level TH input from 68, 69
Latch 1 and TH2. The threshold levels TH1 and TH2 thus obtained are supplied to the multi-level discriminating circuit 4 of the MO decoder 49.

The ROMs 68 and 69 may be arithmetic circuits, and the threshold level corresponding to the input aperture ratio may be calculated each time.

As shown in FIG. 10, the clocks CLK1 to CLK5 are the period T1 immediately after the reference signal is reproduced, and the period T in which the reference signal corresponding to the highest frequency changes to the reference signal corresponding to the lowest frequency.
2. Do not occur during the period T3 in which the negative peak of the reference signal corresponding to the lowest frequency changes from the positive peak to the positive peak, and in the period T4 in which the positive peak of the reference signal corresponding to the lowest frequency changes to the negative peak. Has been done. That is, since these periods are transitional periods, the value of the reference signal is not stable. Therefore, reading of the reference data during these periods is prohibited. This enables accurate reading of the reference data.

When detecting the positive and negative peaks of the reference signal corresponding to the highest frequency and the reference signal corresponding to the lowest frequency, only the data in the range of ± α of each level is averaged. ing. As a result, is it abnormally large due to noise, etc.?
Alternatively, an abnormally small level is prevented from affecting the average value.

The averaging circuits 61 to 64 are shown in FIG.
Can be configured as shown in. In this embodiment, the data output from the A / D converter 48 is latched by the registers 81 to 84 in synchronization with the clock CLK1. The positive peak value of the reference signal corresponding to the highest frequency latched in these registers 81 to 84 is supplied to the average value calculation circuit 85, and the average value is calculated there. This average value is further latched in the register 86 at the subsequent stage. And this register 8
The average value latched in 6 is supplied to the subtraction circuit 65.

On the other hand, the data latched by the register 86 is supplied to the subtraction circuit 87 and the addition circuit 88. The subtraction circuit 87 subtracts a predetermined value α from the data supplied from the register 86. Further, the adder circuit 88 adds a predetermined value α to the output of the register 86. This allows
A level lower than the data latched in the register 86 by the subtraction circuit 87 and the addition circuit 88 by α,
Only a large level will be set.

The comparison circuits 89 and 90 are provided with the data latched by the register 81, the subtraction circuit 87 and the addition circuit 88.
The output data are compared with each other. The comparison circuit 89 outputs a logic 1 when the data latched in the register 81 is larger than the data input from the subtraction circuit 87, and outputs a logic 0 when the data is small. In addition, the comparison circuit 90
Indicates that the data supplied from the register 81 is the adder circuit 88.
Outputs a logic 1 when less than the supplied data,
When it is larger, a logical 0 is output.

The outputs of the comparison circuits 89 and 90 are both supplied to the AND gate 91, and the logical product thereof is calculated. That is, the output of the AND gate 91 is in a range defined by the low level reference level set by the subtraction circuit 87 and the high level reference level set by the addition circuit 88 in which the value of the data latched in the register 81 is set. When it is within the range, it becomes a logic 1, and when it is outside this range, it becomes a logic 0. The output of the AND gate 91 is supplied to the registers 82 to 84 and 86, respectively, and these registers can be operated only when the logic 1 is input from the AND gate 91. Therefore, these registers are prevented from latching noise-like levels outside the range set by ± α.

The registers 83, 84 and 86 are set to predetermined initial values in the initial state.

Although the averaging circuit 61 has been described as a typical example in the above, the same operation is performed in the averaging circuits 62 to 64.

If the clock and the reproduction reference signal are out of phase, the aperture ratio cannot be accurately calculated. Therefore, in order to match the phases of both, the amplitude may be maximized at the highest frequency, or the reproduction levels at the timings of the clocks may be equalized.

When it is necessary to adjust the gain and offset of the amplitude of the reproduced digital data, the positive and negative peak values of the reference signal corresponding to the lowest frequency can be used as the reference.

In the above description, when the digital data is recorded, the reference data for setting the threshold level is recorded at the same time. However, the reference data may be recorded in advance for the read-only ROM data. You can Further, in the above embodiment, the case where the data is recorded by the magnetic field modulation method has been described as an example, but the present invention can be applied to the case where the data is recorded by the optical modulation method.

In the above embodiment, the reference data is recorded in units of sectors.
Not limited to the sector, it can be placed at the beginning of a predetermined block.

[0058]

As described above, according to the digital data recording apparatus of the present invention, the reference data corresponding to the highest frequency among the frequencies included in the digital data and the reference data corresponding to the sufficiently low frequency are recorded on the recording medium. Therefore, it is possible to realize a recording medium capable of accurately determining the logic of digital data even when the recording condition or the reproducing condition varies.

Further, according to the digital data reproducing apparatus of the present invention, the logic of the digital data is calculated from the level of the reference data corresponding to the highest frequency reproduced from the recording medium and the level of the reference data corresponding to the sufficiently low frequency. Since the threshold level for determining is determined, the logic of digital data can be accurately determined.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an arithmetic circuit 52 in the embodiment of FIG.

FIG. 2 is a block diagram illustrating a recording / reproducing principle of a partial response system.

FIG. 3 is a block diagram showing a configuration example of an encoder 1 in the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration example of a decoder 3 in the embodiment of FIG.

5 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 6 is an eye pattern diagram for explaining the operation of the embodiment of FIG.

FIG. 7 is a block diagram showing a configuration of an embodiment of a digital data recording / reproducing apparatus of the present invention.

FIG. 8 is a diagram illustrating an aperture ratio of an eye pattern.

FIG. 9 is a diagram for explaining a format of a sector of the magneto-optical disk 31 in the embodiment of FIG.

FIG. 10 is a timing chart illustrating the operation of the embodiment of FIG.

11 is a block diagram showing a configuration example of an averaging circuit 61 in the embodiment of FIG.

[Explanation of symbols]

1 encoder 2 magneto-optical disk 3 decoder 4 Multi-value discrimination circuit 11 adder 12 Delay circuit 21 Subtractor 22 Delay circuit 31 magneto-optical disk 34 Optical head 35 magnetic head 36 Drive circuit 37 Writing encoder 40 matrix amplifier 41 PLL circuit 45 Tracking error signal generation circuit 46 Servo circuit 49 MO decoder 51 Reference generator 52 Arithmetic circuit 61 to 64 averaging circuit 65,66 Subtraction circuit 67 division circuit 68,69 ROM

Claims (2)

[Claims] 1. A digital data recording apparatus for recording digital data by a partial response system, wherein: generating means for generating reference data corresponding to a maximum frequency and a sufficiently low frequency among frequencies included in the digital data; A digital data recording device, comprising: a recording unit arranged at the beginning of a predetermined data block and recording on a recording medium. 2. A digital data reproducing apparatus for reproducing digital data by a partial response system, wherein a maximum frequency and a sufficiently low frequency among frequencies included in the digital data are arranged at the beginning of each data block of a recording medium. A threshold for determining the logic of digital data from a reading means for reading the corresponding reference data, the level of the reference data corresponding to the highest frequency among the frequencies included in the digital data, and the level of the reference data corresponding to a sufficiently low frequency. A digital data reproducing apparatus comprising: a determining unit that determines a level.