JP2001028607A - Communication buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the memory capacity to store re-transmission start addresses in a communication buffer circuit. SOLUTION: A disclosed communication buffer circuit is provided with a packet boundary detection section 6 that detects the boundary of a packet read from a dual port memory 1 that designates an optional address and reads/ writes data in the unit of packet and with a packet head address storage register 7 that latches a packet head address for each detected packet boundary. The packet in the dual port memory 1 is read based on the packet head address that is latched on the occurrence of a re-transmission request and the packet is re-transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication buffer circuit capable of reducing a memory capacity for storing a retransmission start address when performing a retransmission operation in packet units.

[0002]

2. Description of the Related Art Conventionally, in a communication node for transmitting and relaying packetized data, as a procedure for retransmitting data based on a retransmission request generated on the receiving side based on a transmission error or the like, conventionally, a higher order is used. Generally, retransmission processing is performed by a layer retransmission protocol. However, when performing a retransmission operation in an upper layer, the amount of data to be retransmitted increases due to added control information and the like. Therefore, for a transmission error that can be detected in a lower layer, if the retransmission operation is performed in the lower layer where the error is detected, the amount of data to be retransmitted is small, and the time required for retransmission is reduced. Therefore, such a retransmission method is being studied because a limited transmission path band can be used more effectively.

Conventionally, a dual port memory (DPM) is generally used as a buffer memory for realizing such a retransmission operation. At the time of writing a packet to the dual port memory, by storing the memory address of the packet boundary in a register, when a retransmission request occurs, up to what number of the written packets can be read out Is completed, and the corresponding address is read from a plurality of packet boundary addresses stored in the register and loaded into the address counter, and the packet is read from the dual port memory by using this address. Thus, a retransmission operation in a lower layer can be performed.

[0004]

However, in such a conventional retransmission method, it is necessary to prepare a plurality of registers for storing a packet boundary address in order to determine a retransmission start address. Therefore, when trying to increase the capacity of the communication buffer, it is necessary to increase the register capacity for storing the packet boundary address with the increase in the buffer capacity, which causes an increase in the hardware scale. was there.

The present invention has been made in view of the above circumstances, and in a communication buffer circuit having a retransmission function in units of packets, even if the buffer capacity becomes large, a memory capacity for storing a retransmission start address is provided. It is an object of the present invention to make it possible to reduce the amount.

[0006]

According to a first aspect of the present invention, there is provided a communication buffer circuit for reading and writing data in packet units by arbitrarily specifying an address. Packet boundary detection means for detecting a boundary of a packet read from the buffer circuit; and packet head address storage means for latching a packet head address for each packet boundary detection,
When a retransmission request is input, a packet in the buffer circuit is read from the latched packet head address and retransmitted.

According to a second aspect of the present invention, there is provided the communication buffer circuit according to the first aspect, wherein the packet boundary detecting means monitors a packet read from the buffer circuit to determine a packet boundary having a predetermined pattern. It is characterized in that it is configured to generate a trigger signal when detecting information.

According to a third aspect of the present invention, there is provided the communication buffer circuit according to the second aspect, wherein the packet head address storage means reads out the buffer circuit at a timing at which a trigger signal is received from the packet boundary detection means. An address is latched as the packet start address.

According to a fourth aspect of the present invention, there is provided the communication buffer circuit according to the first aspect, wherein the buffer circuit comprises a dual port memory, and the write address counting means responds to an increment control signal from the write control means. The write clock is counted up to generate a write address, so that the input data is written to the dual port memory in accordance with the write address, and read in the read address counting means in response to the increment control signal from the read control means. By generating a read address by counting up a clock, data written in the dual port memory is read in accordance with the read address to generate output data. It is set to.

According to a fifth aspect of the present invention, there is provided the communication buffer circuit according to the fourth aspect, wherein the write control means includes information indicating that a write area from the dual port memory has become full; It is characterized in that it is configured to generate an increment control signal for the write address counting means from information indicating a valid range of data and a write clock, and to generate a write enable signal for the dual port memory. .

According to a sixth aspect of the present invention, there is provided the communication buffer circuit according to the fifth aspect, wherein the information indicating that the write area from the dual port memory is full is a packet on the dual port memory. In order to prevent loss of a packet due to overwriting of data, the packet is transferred to the data input side circuit.

According to a seventh aspect of the present invention, in the communication buffer circuit according to the fourth aspect, the read control means includes: information indicating that a read area from the dual port memory is empty; From the clock
It is configured to generate an increment control signal for the read address counting means, generate a read enable signal for the dual port memory, and generate information for inserting idle data between packets read from the dual port memory. It is characterized by having.

[0013]

According to the structure of the present invention, during the operation of reading a packet from the dual port memory, the packet boundary detecting means constantly monitors the read data, and every time a packet boundary is detected, the packet boundary address is stored in the packet head address storing means. Outputs trigger signal. The packet head address storage means latches the read address in response to the input trigger signal, and supplies the head address of the latest packet that has been read to the read address count means. When the retransmission request signal is input, the read address counting means loads the packet head address input from the packet head address storage means and performs a read operation from that address. As described above, according to the present invention, during the operation of reading a packet from the dual port memory, only the start address of one packet that is being read is always stored.
At the time of a retransmission request, the retransmission operation is performed using this head address, so that the memory capacity for storing the retransmission start address can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a block diagram showing an electrical configuration of a communication buffer circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the communication buffer circuit of the present embodiment. As shown in FIG. 1, the communication buffer circuit 10 of this example includes a dual port memory (DPM) 1, a write address counter 2, a write control unit 3, a read address counter 4, a read control unit 5, It comprises a boundary detection unit 6 and a packet head address storage register 7.

The dual port memory 1 writes input data from a Din terminal in accordance with a write address input to a WADR terminal, reads out written data in accordance with a read address input to a RADR terminal, Output data is generated at the Dout terminal,
The FF terminal outputs FF (Full Flag) information indicating that the write area is full, and the FF terminal outputs EF (Empty Flag) information indicating that the write area is empty. The FF information is transferred to the data input side circuit in order to prevent packet loss due to overwriting of the packet on the dual port memory 1. The write address counter 2 generates an address for writing input data to the dual port memory 1 according to a write clock in accordance with a control signal from the write control unit 3.

The write control unit 3 indicates whether to permit writing to the dual port memory 1 in accordance with a write clock, information on a data valid range indicating a packet part in input data, and FF information from the dual port memory 1. A write enable signal is generated and input to the WE terminal.
The write address increment control signal is output. The read address counter 4 reads a retransmission request signal from the data output side, a read clock, an increment control signal from the read control unit 5, and a packet start address currently being read from the packet start address storage register 7. , A read address for the dual port memory 1 is generated.

The read control unit 5 is based on a read clock and EF information from the dual port memory 1,
A read address increment control signal is output to the read address counter 4, and a read enable signal indicating permission of reading from the dual port memory 1 is generated and input to the RE terminal. An idle output enable signal for inserting idle data is generated,
Input to the E terminal. The packet boundary detection unit 6 monitors a packet read from the dual port memory 1 and
When detecting the boundary information of the packet ("7Eh" in the case of HDLC), it outputs a trigger signal to the packet head address storage register 7. The packet head address storage register 7 stores the read address at the timing of the trigger signal. The value is latched, and the latched value is supplied to the read address counter 4.

Next, the operation of the communication buffer circuit of this example will be described. At the time of writing, the writing control unit 3
Indicates that the FF information from dual port memory 1 is "Full"
Is not in the state, the write enable signal is output to the dual port memory 1 and the increment control signal is output to the write address counter 2 in accordance with the write clock and the information of the data valid range. The write address counter 2 outputs a write address to the dual port memory 1 in accordance with a write clock, whereby input data is written to the dual port memory 1. At the time of reading, when the EF information from the dual port memory 1 is not in the "Empty" state, the read control unit 5 outputs a read enable signal to the dual port memory 1 in accordance with the read clock, and reads the read address. Since the increment control signal is output to the counter 4, the read address counter 4
A read address is output to the dual port memory 1 in response to the read clock, whereby output data is read from the dual port memory 1 to the data output side circuit.

The packet boundary detector 6 constantly monitors packets read from the dual port memory 1, and outputs a trigger signal when detecting packet boundary information. At the timing of the signal, the read address value is latched, and the latched value is supplied to the read address counter 4 as the packet start address. When there is a retransmission request from the data output side circuit, the read address counter 4 sequentially supplies the read address from the packet top address from the dual port memory 1 according to the read clock, so that the read packet is read. The data is output to the data output side circuit as retransmission data.

Hereinafter, the retransmission operation in the communication buffer circuit of this example will be described in detail with reference to the timing chart of FIG. The write control unit 3 starts a write operation at time T1 according to data valid range information provided from the outside. The write address counter 2 starts the address increment operation from time T1 in synchronization with the write clock according to the increment control signal from the write control unit 3, and increments the address to address A2 by time T4. As a result, the packet A in the input data is sent to the dual port memory 1.
And packet B are written.
Here, packet A starts from address 0 (A1-1).
The packet B is stored from address A1 to address (A2-1). Similarly, time T
5 to time T8, from address A2 to (A3
-1) The packet C is stored up to the address, and from the time T8 to the time T13, the packet is stored from the address A3 to (A5
-1) The packet D is stored up to the address.

Next, a read operation when a retransmission request signal is input at time T10 will be described. The read control unit 5 starts a read operation from time T3. The read address counter 4 includes a read control unit 5
From time T3 to time T7 in accordance with the increment control signal from (A2-1).
Increment until: By this operation, two packets, packet A and packet B, stored from address 0 to address (A2-1) are sequentially read.

During this operation, the packet boundary detector 6
At time T6, a data string indicating a packet boundary included in the output data (a flag pattern: 7Eh when the transfer data is HDLC) is detected, and a trigger signal for latching an address value is sent to the packet head address storage register 7. (Packet boundary detection trigger) is output. The packet start address storage register 7 latches the start address A1 of the packet B in response to the trigger signal,
It is supplied to the read address counter 4. Similarly, at time T7, the packet boundary detection unit 6 detects the packet boundary, updates the contents of the packet head address storage register 7 to the address A2, and supplies it to the read address counter 4.

The read control unit 5 starts the read operation at time T9 after the completion of the writing of the packet C. When the retransmission request signal is input during the reading of the packet C, (A6 -1) Instead of the count value counted up to the address, the address value A supplied from the packet start address storage register 7 is used.
The address 2 is loaded, and the read operation of the packet C is executed again. At the time T11, when the reading of the packet C is completed and the retransmission operation of the packet is completed, at this time, the content of the packet head address storage register 7 is
It is updated to address 3. Hereinafter, similarly, after the completion of writing of the packet D, the read operation is started from time T14, and the read address becomes A by time T16.
3 → A4 → 0 → (A5-1) is incremented,
The reading of the packet D is performed.

As described above, according to the communication buffer circuit of this example, the packet read side detects the packet boundary and always stores only the start address of one packet being read out in the packet start address storage register 7. The memory capacity for storing the retransmission start address can be reduced.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. Even this is included in the present invention. For example, the data unit read and written by the communication buffer circuit of the present invention is not limited to a packet but may be a frame. The communication buffer circuit of the present invention is a communication node for packet communication, for example,
Multiplexer and optical network unit (Optical Network Unit: O
NU) and the like. The present invention provides HDLC (High-level Data Link)
Control procedures) at the retransmission technology level
Applied to reduce hardware (memory) scale. Conventionally, for this purpose, FIFO (First In First O
ut) Many memories have been used. However, in the FIFO, only the address is incremented, and a dual-port memory is required for returning the address value and retransmitting the data. However, the present invention is not limited to a dual-port memory, but can be applied to any type of storage device that achieves the same purpose.

[0026]

As described above, according to the communication buffer circuit of the present invention, a buffer boundary is detected on the buffer reading side, and only the head address of one packet in the middle of reading is always stored. I decided to leave
Even if the capacity of the communication buffer becomes large, the memory capacity for storing the retransmission start address can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a communication buffer circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the communication buffer circuit of the embodiment.

[Explanation of symbols]

1 Dual Port Memory (Buffer Circuit) 2 Write Address Counter (Write Address Counting Means) 3 Write Control Unit (Write Control Means) 4 Read Address Counter (Read Address Counting Means) 5 Read Control Unit (Read Control Means) 6 Packet Boundary Detection Section (packet boundary detecting means) 7 packet head address storage register (packet head address storage means) 10 communication buffer circuit

Claims (7)

[Claims] A buffer circuit for reading and writing data in packet units by arbitrarily designating an address; a packet boundary detecting means for detecting a boundary of a packet read from the buffer circuit; A packet head address storage unit for latching a head address, wherein when a retransmission request is input, a packet in the buffer circuit is read from the latched packet head address and retransmitted. Communication buffer circuit. 2. The apparatus according to claim 1, wherein said packet boundary detecting means monitors a packet read from said buffer circuit and generates a trigger signal when detecting packet boundary information having a predetermined pattern. The communication buffer circuit according to claim 1, wherein 3. The packet head address storage means,
3. The communication buffer circuit according to claim 2, wherein a read address of said buffer circuit is latched as said packet head address at a timing at which a trigger signal is received from said packet boundary detecting means. 4. The writing circuit according to claim 1, wherein the buffer circuit comprises a dual port memory.
The input data is written to the dual port memory according to the write address by counting up a write clock in response to an increment control signal from the write control means and generating a write address. A read address is generated by counting up a read clock in response to an increment control signal from the means, so that data written in the dual port memory is read and output data is generated in accordance with the read address. The communication buffer circuit according to claim 1, wherein the communication buffer circuit is configured. 5. The information processing apparatus according to claim 1, wherein the write control means includes: information indicating that a write area from the dual port memory is full; information indicating an effective range of the input data;
5. The communication buffer circuit according to claim 4, wherein an increment control signal for said write address counting means is generated from a write clock and a write enable signal for said dual port memory is generated. 6. Information indicating that a write area from the dual port memory is full is transferred to a data input side circuit in order to prevent packet loss due to overwriting of a packet on the dual port memory. The communication buffer circuit according to claim 5, wherein the communication buffer circuit is configured to be configured as follows. 7. The read control means for generating an increment control signal for the read address counting means from information indicating that a read area from the dual port memory has become empty and a read clock, The communication buffer circuit according to claim 4, wherein the communication buffer circuit is configured to generate a read enable signal for the dual port memory and information for inserting idle data between packets read from the dual port memory.