JP2001028521A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent breakdown of capacity due to surge voltage. SOLUTION: A p-n diode 22 is allowed to be short-circuited by a surge voltage and to be biased in the forward direction by connecting the diode 22 between the output terminal 15 side of capacity 10 and a ground line 5 with reverse polarity from the capacity 10 to the line 5, even if the surge voltage is applied to the terminal 15. Thus, the capacity 10 can be protected from the surge voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for improving a surge withstand voltage.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing a conventional semiconductor integrated circuit, in which 1 is an operational amplifier, 2 is a phase compensation circuit for preventing oscillation due to feedback of a source follower output circuit 3, and 3 is an entire circuit configuration. Are a source follower output circuit for reducing the output impedance of the power supply, a power supply line 4 and a ground line 5. In the operational amplifier 1, 6
Is a differential amplifier for differentially amplifying input signals from the input terminals 7 and 8, and 9 is a gain stage constituted by a current mirror circuit for further increasing the gain. Further, in the phase compensation circuit 2, 10 is a capacitor, 11 is an insulator sandwiched between the electrodes of the capacitor 10, and 12 is a resistor. Further, in the source follower output circuit 3, 13 is a p-channel MOS transistor, 14 is a load resistor, and 15 is an output terminal.

Next, the operation will be described. Differential amplifier 6
Differentially amplifies the input signals from the input terminals 7 and 8, and the gain stage 9 further increases the gain and outputs the amplified signal from the output terminal 15 of the source follower output circuit 3. The phase compensation circuit 2 performs phase compensation by the capacitor 10 and the resistor 12 to prevent oscillation due to feedback.

[0004]

Since the conventional semiconductor integrated circuit is constructed as described above, it is susceptible to external static electricity connected to the output terminal 15. For example, consider a case where a positive pulse is input to the output terminal 15. At this time, there is a risk that the p-channel MOS transistor 13, the load resistor 14, the capacitor 10, and the resistor 12 are destroyed by a large voltage. In particular, when the capacitor 10 is formed of a MOS capacitor, a poly-poly capacitor, or the like, the insulator 11 is interposed between the electrodes, so that the current due to the surge cannot be absorbed, and the possibility of destruction is high. Become. Furthermore, since the insulator 11 is made very thin in order to improve the capacitance value per unit area of the capacitor 10, there is a problem that the insulator 11 is easily broken when a surge voltage is applied. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a semiconductor integrated circuit capable of preventing a capacitance from being destroyed by a surge voltage.

[0006]

A semiconductor integrated circuit according to the present invention includes a pn junction element connected between the output terminal of a capacitor and the ground with a reverse polarity from the capacitor to the ground. is there.

A semiconductor integrated circuit according to the present invention includes a pn junction element connected between a capacitor output terminal and a power supply in a forward polarity from the capacitor toward the power supply.

[0008] A semiconductor integrated circuit according to the present invention comprises: a first pn junction element connected in reverse polarity from a capacitor to a ground, between a capacitor output terminal and a ground; A second pn junction element connected to the power supply in a forward polarity from the capacitor toward the power supply.

In a semiconductor integrated circuit according to the present invention, a pn junction element, a first pn junction element, and a second pn junction element are connected to one or more pn diodes connected in series, or one or more pn diodes. Multiple bases connected in series
It is composed of a collector diode or one or more base-emitter diodes connected in series.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. In the figure, 1 is an operational amplifier, 21 is a phase compensation circuit for preventing oscillation due to feedback of a source follower output circuit 3, and 3 is a circuit configuration A source follower output circuit for reducing the overall output impedance, 4 is a power supply line (power supply), and 5 is a ground line (ground). In the operational amplifier 1, reference numeral 6 denotes a differential amplifier for differentially amplifying input signals from the input terminals 7 and 8, and reference numeral 9 denotes a gain stage configured by a current mirror circuit to further increase the gain. Further, in the phase compensation circuit 21, reference numeral 10 denotes a capacitor, 12 denotes a resistor, and 22 denotes a capacitor 1
The pn diode (pn junction element) is connected between the output terminal 15 of the “0” side and the ground line 5 with the opposite polarity from the capacitor 10 toward the ground line 5. Further, in the source follower output circuit 3, 13 is a p-channel M
The OS transistor, 14 is a load resistor, and 15 is an output terminal.

Next, the operation will be described. Differential amplifier 6
Differentially amplifies the input signals from the input terminals 7 and 8, and the gain stage 9 further increases the gain and outputs the amplified signal from the output terminal 15 of the source follower output circuit 3. The phase compensation circuit 21 performs phase compensation by the capacitor 10 and the resistor 12 to prevent oscillation due to feedback. Here, when no surge voltage is applied to the output terminal 15, the pn diode 22 is reverse-biased, and no current flows through the pn diode 22. Further, since the parasitic capacitance of the pn diode 22 is generally smaller than the capacitance 10, the influence of the pn diode 22 on the circuit characteristics can be ignored. When a positive surge voltage is applied to the output terminal 15, since the surge voltage is very high, the cathode voltage of the pn diode 22 becomes higher than the breakdown voltage, and the anode and the cathode of the pn diode 22 are short-circuited. . In this way, the capacitor 10 is protected by preventing a voltage higher than the breakdown voltage of the pn diode 22 from being applied to the capacitor 10. When a negative surge voltage is applied to the output terminal 15, the pn diode 22 is biased in the forward direction, and a current flows from the ground line 5 to the output terminal 15 through the pn diode 22, and the capacitance 10 The capacitor 10 is protected by preventing a negative surge voltage from being applied to the capacitor 10.

As described above, according to the first embodiment, the pn diode 22 is connected between the output terminal 15 of the capacitor 10 and the ground line 5 with the opposite polarity from the capacitor 10 toward the ground line 5. Therefore, even when a surge voltage is applied to the output terminal 15, the pn diode 22 is short-circuited by the surge voltage, or the pn diode 22 is biased in the forward direction, so that the capacitance 10 can be protected from the surge voltage. can get. In the first embodiment, only one pn diode 22 is connected. However, depending on the surge voltage and the breakdown voltage, the pn diode 22 is connected.
A plurality of diodes 22 may be connected in series.

Embodiment 2 FIG. FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. In the figure, reference numeral 23 denotes a portion between the output terminal 15 side of the capacitor 10 and the ground line 5 from the capacitor 10 to the ground line 5. Base-collector diode (p
n junction element). Other configurations are the same as those in FIG.

Next, the operation will be described. In the first embodiment, the pn diode 22 is used. However, in the second embodiment, the base-collector diode 23 composed of an NPN transistor is used. Even in such a configuration, when the surge voltage is not applied to the output terminal 15, the influence of the base-collector diode 23 on the circuit characteristics can be ignored, and the surge voltage is not applied to the output terminal 15. In this case, the collector and the base of the base-collector diode 23 are short-circuited. In this way, the capacitor 10 is protected by preventing a voltage higher than the breakdown voltage of the base-collector diode 23 from being applied to the capacitor 10. By the way, the pn diode 22
Breakdown voltage and base-collector diode 2
Since it is different from the breakdown voltage of No. 3, an appropriate pn junction is selected according to the situation and used as a protection element.
For example, a junction between an epi layer and a substrate, a base-emitter junction of a PNP transistor, or the like can be used.

As described above, according to the second embodiment, the base-collector diode 23 is connected between the output terminal 15 of the capacitor 10 and the ground line 5 in the reverse polarity from the capacitor 10 toward the ground line 5. Is connected, even if a surge voltage is applied to the output terminal 15,
The collector diode 23 is short-circuited by the surge voltage, and the effect that the capacitor 10 can be protected from the surge voltage is obtained. In the second embodiment, two base-collector diodes 23 are connected in series. However, one or more base-collector diodes 23 are connected in series according to the surge voltage and the breakdown voltage. You may do it.

Embodiment 3 FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention. In the figure, reference numeral 24 denotes an output terminal 15 of a capacitor 10 and a power supply line 4.
And a pn diode (pn junction element) connected in a forward polarity from the capacitor 10 toward the power supply line 4.
Other configurations are the same as those in FIG.

Next, the operation will be described. In the first embodiment, the pn diode 22 is connected to the side of the ground line 5, but in the third embodiment, the pn diode 2 is connected.
4 is connected to the power supply line 4 side. Even in such a configuration, when a surge voltage is not applied to the output terminal 15, if the breakdown voltage of the pn diode 24 is equal to or higher than the voltage of the power supply line 4, it is selected.
No current flows through the pn diode 24, and the influence on the circuit characteristics can be ignored. When a surge voltage is applied to the output terminal 15, the surge voltage is applied to the voltage of the power supply line 4. When the voltage exceeds the voltage obtained by adding the ON voltage of 24, the pn diode 2
4 is biased in the forward direction, a current due to the surge voltage flows to the power supply line 4 side, and the capacitor 10 can be protected.

As described above, according to the third embodiment, between the output terminal 15 side of the capacitor 10 and the power supply line 4, pn is forward-polarized from the capacitor 10 toward the power supply line 4.
Since the diode 24 is connected, even if a surge voltage is applied to the output terminal 15, the pn diode 24 is biased in the forward direction by the surge voltage, and an effect is obtained that the capacitor 10 can be protected from the surge voltage. In addition,
In the third embodiment, only one pn diode 24 is connected. However, a plurality of pn diodes 24 may be connected in series according to the voltage of the power supply line 4 and the breakdown voltage. Embodiment 2
As shown in the above, the base-collector diode 23 is
1 according to the voltage of the power supply line 4 and the breakdown voltage
One or a plurality of them may be connected in series.

Embodiment 4 FIG. 4 is a circuit diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention. In the drawing, reference numeral 22 denotes a portion between the output terminal 15 side of the capacitor 10 and the ground line 5 from the capacitor 10 to the ground line 5. And a pn diode (first pn junction element) 24 connected in reverse polarity between the output terminal 15 side of the capacitor 10 and the power supply line 4 and connected in a forward polarity from the capacitor 10 toward the power supply line 4. Pn diode (second pn junction element)
It is. Other configurations are the same as those in FIG.

Next, the operation will be described. In the fourth embodiment, the pn diode 22 shown in the first embodiment includes:
This is a combination of the pn diode 24 shown in the third embodiment. With this configuration, the capacity 1
The voltage applied to the 0-side resistor 12 side electrode is (voltage of the ground line 5) − (on voltage of the pn diode 22)
From (voltage of power supply line 4) + (pn diode 24
On-voltage). Therefore, the output terminal 15
Even when a surge voltage is applied to the capacitor 10, the capacitor 10 is kept within the voltage range to protect the capacitor 10.

As described above, according to the fourth embodiment, the pn diode 22 is connected between the output terminal 15 of the capacitor 10 and the ground line 5 with the opposite polarity from the capacitor 10 toward the ground line 5. And the output terminal 1 of the capacitor 10
Since the pn diode 24 is connected between the capacitor 5 side and the power supply line 4 in the forward polarity from the capacitor 10 toward the power supply line 4, even if a surge voltage is applied to the output terminal 15, the pn diode 22 is not affected by the surge voltage. Shorted,
the pn diode 22 is forward biased, or
The pn diode 24 is biased in the forward direction by the surge voltage, and an effect is obtained that the capacitor 10 can be protected from the surge voltage.

Embodiment 5 FIG. 5 is a circuit diagram showing a semiconductor integrated circuit according to a fifth embodiment of the present invention. In the first to fourth embodiments, a special circuit configuration in which the source follower output circuit 3 is connected to the operational amplifier 1 is shown. However, in the fifth embodiment, a general circuit configuration in which the output circuit 31 is connected to the operational amplifier 1 is shown.
Even a general operational amplifier as shown in FIG.
The capacitor 10 and the resistor 12 of the phase compensation circuit 21 are connected to the output terminal 1
5 is connected. Therefore, the capacitance 10 can be protected by the pn diode 22. The protection element of the capacitor 10 may be a base-collector diode or a base-emitter diode as described in the first to fourth embodiments, or may be connected to the power supply line 4 side. .

Embodiment 6 FIG. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 6 of the present invention. In Embodiments 1 to 5, the circuit configuration using a CMOS circuit is shown. In Embodiment 6, An output circuit 42 is connected to an operational amplifier 41 constituted by a bipolar element.
FIG. 2 shows a circuit configuration in which. Even an operational amplifier using a bipolar element as shown in FIG.
The capacitor 10 and the resistor 12 of the phase compensation circuit 21 are connected to the output terminal 1
5 is connected. Therefore, the capacitance 10 can be protected by the pn diode 22. The protection element of the capacitor 10 may be a base-collector diode or a base-emitter diode as described in the first to fourth embodiments, or may be connected to the power supply line 4 side. .

Embodiment 7 FIG. FIG. 7 is a circuit diagram showing a semiconductor integrated circuit according to a seventh embodiment of the present invention. In the seventh embodiment, a circuit configuration in which an output circuit 52 is connected to an operational amplifier 51 whose polarity is inverted is different from that of the sixth embodiment. It is shown. Even in the case of an operational amplifier using a bipolar element as shown in FIG.
And the resistor 12 are connected to the output terminal 15. Therefore, the capacitance 10 can be protected by the pn diode 22. The protection element of the capacitor 10 may be a base-collector diode or a base-emitter diode as described in the first to fourth embodiments, or may be connected to the power supply line 4 side. .

[0025]

As described above, according to the present invention, a pn junction element is connected between the output terminal side of the capacitor and the ground so that the pn junction element is connected in reverse polarity from the capacitor to the ground. When a surge voltage is applied to the pn junction element, the pn junction element is short-circuited by the surge voltage, or the pn junction element is biased in the forward direction, so that the effect of protecting the capacitance from the surge voltage can be obtained.

According to the present invention, since the pn junction element is connected between the output terminal side of the capacitor and the power supply and has a forward polarity from the capacitor toward the power supply, a surge voltage is applied to the output terminal. Also, the effect is obtained that the pn junction element is forward biased by the surge voltage and the capacitance can be protected from the surge voltage.

According to the present invention, the first pn junction element connected in reverse polarity from the capacitor to the ground is provided between the output terminal of the capacitor and the ground, and the first pn junction element is connected between the output terminal of the capacitor and the power supply. Since the second pn junction element is connected between the capacitor and the power supply in the forward polarity, even if a surge voltage is applied to the output terminal, the first pn junction element is short-circuited by the surge voltage. Alternatively, the first pn junction element is biased in the forward direction, or the second pn junction element is biased in the forward direction by the surge voltage, and the effect of protecting the capacitance from the surge voltage is obtained.

According to the invention, one or more pn junction elements, the first pn junction element, and the second pn junction element are connected in series,
Since it is composed of one or more base-collector diodes connected in series or one or more base-emitter diodes connected in series, it can be arbitrarily designed according to the requirements of the target circuit. As a result, the effect of expanding the design range can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a semiconductor integrated circuit according to a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

4 power supply (power supply line), 5 ground line (ground), 10 capacitance, 12 resistance, 15 output terminal, 22
pn diode (pn junction element, first pn junction element), 23 base-collector diode (pn junction element), 24 pn diode (pn junction element, second pn junction element)
n-junction element).

Claims (4)

[Claims] 1. A capacitor connected to an output terminal via a resistor, and a pn junction element connected between the output terminal side of the capacitor and ground and connected in reverse polarity from the capacitor to the ground. A semiconductor integrated circuit comprising: 2. A capacitor connected to an output terminal via a resistor, and a pn junction element connected between the output terminal side of the capacitor and a power supply with a forward polarity from the capacitance toward the power supply. A semiconductor integrated circuit comprising: 3. A capacitor connected directly or via a resistor to an output terminal, and a first capacitor connected between the output terminal side of the capacitor and ground and connected in reverse polarity from the capacitor to the ground. And a second pn junction element connected between the output terminal side of the capacitor and the power supply with a forward polarity from the capacitance toward the power supply. 4. The pn junction element, the first pn junction element, and the second pn junction element are one or more pn diodes connected in series, or one or more bases connected in series. -A collector diode or
4. The semiconductor integrated circuit according to claim 1, wherein one or more base-emitter diodes are connected in series.