JP2001028196A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a flash memory in which shortening the time for programming and accurate read-out can be compatible. SOLUTION: Two dummy cells D1, D3 one of which is set to an erase-state and the other is set to a program state to read the stored data of a memory cell M4 are provided. Threshold voltage in the program state of each cell is set higher than the threshold voltage of an erase-state, and set lower than the maximum read-voltage between the control gate and source. Bit lines MBL1, MBL3 connected to each drain of the dummy cells D1, D3 are coupled mutually by an equalizing switch EQSA so that intermediate reference potential in a read-cycle is generated. The state of the memory cell M4 is sensed by comparing the potential of the bit line MBL0 connected to the drain of the memory cell 4 with a generated reference potential by a differential sense amplifier 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to an electrically erasable and programmable memory, that is, an EEPROM (Electrically).
Erasable and Programmable Read Only Memory).

[0002]

2. Description of the Related Art Conventionally, a flash EEPROM having a plurality of nonvolatile memory cells each having a control gate, a floating gate, a drain, and a source and capable of erasing stored data collectively for each predetermined block.
(Flash memory) is known.

FIG. 4 shows a distribution of a threshold voltage Vth of a memory cell in a conventional flash memory. In the erase cycle, the electrons stored in the floating gate of each memory cell are removed, so that each memory cell has a low threshold voltage. The state of the memory cell storing the data “0” in this manner is referred to as an erase state or a zero state here. In the program cycle, electrons are stored in the floating gate of only the selected memory cell by a hot electron injection mechanism. A memory cell having electrons stored in the floating gate has a high threshold voltage. The state of the memory cell storing the data “1” in this manner is referred to as a program state or a 1 state here. Read (read)
In the cycle, a predetermined low read voltage Vgs is applied between the control gate and the source while a low positive potential is applied to the drain of the memory cell to be read and the ground potential is applied to the source thereof. When the maximum value of the read voltage, that is, the maximum read voltage is set to Vgsmax, conventionally, it takes a sufficient time until all the memory cells to be changed from the 0 state to the 1 state have a threshold voltage higher than Vgsmax. The program was being run over.

A differential sense type flash memory having high-speed read performance is known. This flash memory has a structure similar to that of the memory cell and is always set to 0 in order to read storage data of one memory cell whose state is set according to FIG.
Dummy cells and one differential sense amplifier are provided. The drain of the memory cell is connected to the differential sense amplifier via a first bit line, and the drain of the dummy cell is connected to the differential sense amplifier via a second bit line. These first
And the second bit line is set to a predetermined precharge potential VPC in an initial stage of a read cycle. When the memory cell is in the 0 state, the memory cell draws a drain current from the first bit line when a read voltage Vgs is applied between its control gate and the source, thereby causing the first memory cell to drain the first bit line. Reduce the potential of the bit line. When this memory cell is in one state, the same read voltage Vgs
Is applied between the control gate and the source, the memory cell does not draw the drain current from the first bit line, and the potential of the first bit line maintains VPC. On the other hand, when the same read voltage Vgs is applied between the control gate and the source, the dummy cell draws a drain current from the second bit line, thereby lowering the potential of the second bit line. However, the channel width and / or channel length of the dummy cell is adjusted such that the drain current of the dummy cell is half of the drain current of the memory cell in the 0 state. Therefore, the reference potential Vref generated by the dummy cell on the second bit line is higher than the potential of the first bit line when the memory cell is in the 0 state, and the first potential when the memory cell is in the 1 state. It is lower than the bit line potential VPC. The differential sense amplifier can correctly sense the state of the memory cell by comparing the potentials of the first and second bit lines.

[0005]

In the above conventional flash memory, all the memory cells to be changed from the 0 state to the 1 state are higher than the maximum read voltage Vgsmax so that the stored data "1" of the memory cell can be read correctly. Since the program operation is not terminated until the threshold voltage is reached, there is a problem that the program requires a long time (see FIG. 4).

FIG. 5 shows a problem in a read cycle of the conventional differential sensing type flash memory. That is, if the read voltage Vgs unexpectedly increases due to an increase in the power supply voltage, the storage data “1” in the memory cell cannot be read correctly. FIG.
The broken line in the middle indicates that the potential of the bit line connected to the one-state memory cell having a threshold voltage higher than the read voltage maintains VPC in the read cycle. However, the threshold voltage Vth of the memory cell in one state
If the read voltage Vgs becomes higher, that is, Vgs> V
When it is th, the memory cell in the 1 state lowers the potential of the bit line by drawing a drain current from the bit line. On the other hand, the reference potential Vref generated by the dummy cell in the 0 state does not depend on the read voltage Vgs.
Therefore, as shown in FIG. 5, when Vgs> Vth, 1
The bit line potential lowered by the memory cell in the state may become lower than the reference potential Vref, and in this case, a read malfunction occurs. In order to solve the above-described problem of the programming time, the threshold voltage of the memory cell in one state is set to the maximum read voltage V
Occurs when setting lower than gsmax.

An object of the present invention is to provide a nonvolatile semiconductor memory device that can achieve both a reduction in program time and accurate reading.

[0008]

In order to achieve the above object, the present invention reduces the threshold voltage of a memory cell in a program state (1 state) and simultaneously reduces the threshold voltage of an erase state (0 state).
In this case, the reference potential in the read cycle is generated by connecting the bit line connected to the dummy cell in the state (state) and the bit line connected to the dummy cell in the program state (state 1).

More specifically, a nonvolatile semiconductor memory device according to the present invention has an erase state having a control gate, a floating gate, a drain, and a source, and each having a low threshold voltage. A program state in which more electrons than the erase state are stored in the floating gate so as to have a threshold voltage higher than the threshold voltage in the erase state; The first, second, and third memory cells are set to have a threshold voltage lower than the maximum read voltage between the control gate and the source, and the first memory cell is connected to the drain of the first memory cell. 1 bit line, a second bit line connected to the drain of the second memory cell, and a drain connected to the third memory cell. A third bit lines, the second
And means for setting the state of each of the second and third memory cells such that one of the memory cells has the erase state and the other has the program state. Means for connecting the second bit line and the third bit line in a cycle, and precharging each of the first, second and third bit lines in an initial stage of the read cycle. Means for setting to a potential, and the potential of the first bit line lowered from the precharge potential by the first memory cell drawing a drain current from the first bit line in the read cycle. And wherein the second and third memory cells draw drain currents from the connected second and third bit lines, respectively, thereby forming the pre-charge circuit. A configuration including a sense unit for sensing the state of the first memory cell by comparing the potential of the second and third bit lines lowered from the potential of the first memory cell. .

It is known that, in a flash memory, the interface characteristics of a gate oxide film are significantly deteriorated when erasing / programming of a memory cell is repeated. Therefore, in order to equalize the degree of deterioration of the first, second, and third memory cells, the number of times of erasing / programming of these memory cells may be made as uniform as possible. As a result, an optimal reference potential is always obtained.

[0011]

FIG. 1 shows a configuration example of a flash memory according to the present invention. 1 includes a top array 10, a bottom array 11, four main bit lines MBL0 to MBL3, and eight sub-bit lines SBL0.
To 7 and 8 bit line selection switches TS0 to 3, BS
0 to 3 are provided.

The top array 10 includes memory cells M0 to M3.
, Dummy cells D0 to D3, and other memory cells (not shown). These cells are nonvolatile memory cells each having a control gate, a floating gate, a drain, and a source. Each of the control gates of M0 to M3 is connected to a word line TWL, and each of the sources is connected to a source line TSWL.
L. Each of the control gates of D0 to D3 is connected to a dummy word line TDWL, and the source of each of them is connected to a dummy source line TDSL. M
The drains of 0 and D0 are connected to SBL0, and SBL0 is connected to MBL0 via TS0. Each drain of M1 and D1 is connected to SBL1, and SBL1 is connected to MBL1 via TS1. The drain of each of M2 and D2 is SBL
SBL2 is connected to MB via TS2.
L2. Each drain of M3 and D3 is connected to SBL3, which is connected to MBL3 via TS3. The signal TG0 is applied to the gates of the transistors constituting each of TS0 and TS2.
The signal TG1 is applied to the gates of the transistors constituting each of TS1 and TS3.

The bottom array 11 includes memory cells M4 to M7.
, Dummy cells D4 to D7, and other memory cells (not shown). These cells are nonvolatile memory cells each having a control gate, a floating gate, a drain, and a source. Each of the control gates of M4 to M7 is connected to a word line BWL, and each of its sources is connected to a source line BS.
L. Each of the control gates of D4 to D7 is connected to a dummy word line BDWL, and the source of each is connected to a dummy source line BDSL. M
The drain of each of D4 and D4 is connected to SBL4, which is connected to MBL0 via BS0. Each drain of M5 and D5 is connected to SBL5, which is connected to MBL1 via BS1. The drain of each of M6 and D6 is SBL
6 and the SBL6 is connected to the MB via the BS2.
L2. Each drain of M7 and D7 is connected to SBL7, which is connected to MBL3 via BS3. A signal BG0 is applied to the gates of the transistors constituting each of BS0 and BS2.
The signal BG1 is applied to the gates of the transistors constituting each of BS1 and BS3.

On each of MBLs 0-3, corresponding column gates YS0-3 are interposed. YS0
And YS2, the signal YG0 is supplied to the gate of the transistor and YS1 and YS3, the signal YG1 is supplied to the gate of the transistor. Each inner part of MBL0 and MBL1 (part below YS0 and YS1 in the figure) and MB
In order to set the inner parts of L2 and MBL3 (the parts below YS2 and YS3 in the figure) to a predetermined precharge potential VPC, respectively, a precharge circuit 12,
13 are provided. The potentials of the outer portions of MBL0 and MBL1 (the portions above YS0 and YS1 in the drawing) and the outer portions of MBL2 and MBL3 (the portions above YS2 and YS3 in the drawing) are respectively set to VPC. Precharge circuits 14, 15
Is provided. An equalizing switch EQSA for connecting these main bit lines in a read cycle is interposed between the outer portions of each of MBL1 and MBL3. An equalizing switch EQSB for connecting these main bit lines in a read cycle is interposed between the outer portions of MBL0 and MBL2. The signal EQA is supplied to the gate of the transistor constituting the EQSA, and the signal EQB is supplied to the gate of the transistor constituting the EQSB. Reference numeral 16 denotes a differential sense amplifier connected to each of the outer portions of MBL0 and MBL1, and reference numeral 17 denotes MBL2 and MBL.
L3 represents a differential sense amplifier connected to each outer portion. In addition, M0-7 and D0-7 are:
The same size,
Further, they are formed at the same pitch.

FIG. 2 shows a distribution of threshold voltages Vth of memory cells (including M0 to D7 and D0 to D7) in the flash memory of FIG. In the erase cycle of the top array 10, TWL, TDWL, TSL and TWL
By applying a required potential to each of the DSLs, M
The removal of the electrons stored in the floating gates 0-3 and D0-3 results in the individual memory cells being in a zero state having a low threshold voltage. Bottom array 1
In one erase cycle, BWL, BDWL, BSL
And BDSL are supplied with a required potential, so that each of M4 to M7 and D4 to 7 becomes a zero state having a low threshold voltage. Here, for example, when data “1” is to be programmed in M0, TWL and TSL
, And a write circuit (not shown) connected to MBL0 supplies M0 with a required potential, and closes TS0 and YS0.
A program operation is performed by applying a required potential to BL0 and SBL0. As a result, electrons are stored in the floating gate of M0 by the mechanism of hot electron injection, and M0 transitions from the 0 state to the 1 state having a threshold voltage higher than the 0 state. However, as shown in FIG. 2, the threshold voltage in this 1 state is the maximum value of the read voltage applied between the control gate and the source in the read cycle, that is, the maximum read voltage V
Set to a value lower than gsmax. The same applies to the case where data "1" is programmed in other memory cells (including dummy cells). That is, in the flash memory of FIG.
The threshold voltage of the memory cell in one state is greatly reduced as compared with the conventional example shown by a rough broken line in FIG. Therefore, the programming time is greatly reduced as compared with the conventional case.
In each cycle of erase and program, EQ
Keep SA and EQSB open.

Next, a read cycle of the flash memory shown in FIG. 1 will be described. Precharge circuits 12-15
Are MBLs 0-3 in the initial stage of each read cycle.
Are charged to the VPC. After sufficient charging, the switches constituting these precharge circuits 12 to 15 are opened. In this precharge period, for example, TS0-3, BS0-3, YS0-3, EQSA and EQSB may all be closed.

According to the configuration shown in FIG. 1, one of D0 and D2 is preset to a 0 state, and the other is preset to a 1 state. These D0 and D2 are used to generate a reference potential in the read cycles of M5 and M7.
At this time, TS0, BS1, TS2, BS3, YS0-3
And EQSB are each closed. BS0, TS1,
BS2, TS3 and EQSA are each open. Thereafter, a predetermined read voltage Vgs is applied to the control gates of the selected memory cells M5 and M7. Similarly, a dummy cell D for generating a reference potential
The read voltage Vgs is also applied to the control gates 0 and D2. The differential sense amplifier 16 determines that MBL1 to M5 pull M
After waiting until a difference between the potential of BL1 and the potentials of MBL0 and MBL2 lowered from VPC by D0 and D2 drawing the drain current from the connected MBL0 and MBL2 respectively can be detected, the amplification operation is performed to perform M5. Sense the state of. Differential sense amplifier 17
Are the potential of MBL3 lowered from VPC by MB7 from MBL3 drawing the drain current, and the potential of MBL0 and MBL2 lowered from VPC by D0 and D2 from the connected MBL0 and MBL2 respectively draw the drain current. After detecting the difference, the state of M7 is sensed by performing an amplification operation. During these amplification operations, YS0 to YS3 and E
Each QSB is opened. This allows the potential difference between MBL0 and MBL2 to be generated by both differential sense amplifiers 16 and 17.

One of D1 and D3 is set to a 0 state, and the other is set to a 1 state. These D
1 and D3 are used to generate a reference potential in the read cycles of M4 and M6. At this time, BS
0, TS1, BS2, TS3, YS0-3 and EQSA
Are closed respectively. TS0, BS1, TS2, BS
3 and EQSB are each open. Thereafter, a predetermined read voltage Vgs is applied to the control gates of the selected memory cells M4 and M6. Similarly, the read voltage Vgs is also applied to the control gates of the dummy cells D1 and D3 for generating the reference potential. The differential sense amplifier 16 detects the potential of MBL0 lowered from VPC by the MBL0 to M4 drawing the drain current, and the connected MBL1 and MBL3 to D1 and D3.
Waits until a difference between the potential of MBL1 and MBL3 lowered from VPC by drawing the drain current can be detected, and then the state of M4 is sensed by performing an amplification operation. The differential sense amplifier 17 uses the MBL2
To the potential of MBL2 lowered from VPC by M6 drawing the drain current, and the potential of MBL1 and MBL3 lowered from VPC by D1 and D3 from the connected MBL1 and MBL3 respectively drawing the drain current. , The state of M6 is sensed by performing an amplification operation. During these amplification operations, YS0 to YS3 and EQSA are respectively opened. Thereby, both differential sense amplifiers 16,
17 is allowed to generate a potential difference between MBL1 and MBL3.

One of D4 and D6 is preset to a 0 state, and the other is preset to a 1 state. These D4 and D6 are used for generating a reference potential in the read cycle of M1 and M3. At this time, BS0, TS
1, BS2, TS3, YS0-3 and EQSB are respectively closed. TS0, BS1, TS2, BS3 and E
The QSAs are each open. Thereafter, a predetermined read voltage Vgs is applied to the control gates of the selected memory cells M1 and M3. Similarly, the read voltage Vgs is applied to the control gates of the dummy cells D4 and D6 for generating the reference potential. Differential sense amplifier 1
6 is the potential of MBL1 lowered from VPC by M1 pulling the drain current from MBL1 and the potential of MBL0 and MBL2 lowered from VPC by D4 and D6 from the connected MBL0 and MBL2 respectively. After waiting until a difference from the potential can be detected, the state of M1 is sensed by performing an amplification operation. The differential sense amplifier 17 outputs the potential of MBL3 lowered from VPC by the drain current from MBL3 to M3, and the connected MBL0 and MBL2.
, D4 and D6 wait for the difference between the potential of MBL0 and MBL2 lowered from VPC by drawing the drain current, and then perform the amplification operation to sense the state of M3. During these amplification operations, YS0 to YS3 and EQSB are opened, respectively. This allows the potential difference between MBL0 and MBL2 to be generated by both differential sense amplifiers 16 and 17.

One of D5 and D7 is preset to a 0 state, and the other is preset to a 1 state. These D5 and D7 are used for generating a reference potential in the read cycles of M0 and M2. At this time, TS0, BS
1, TS2, BS3, YS0-3 and EQSA are closed respectively. BS0, TS1, BS2, TS3 and E
The QSBs are each open. Thereafter, a predetermined read voltage Vgs is applied to the control gates of the selected memory cells M0 and M2. Similarly, the read voltage Vgs is also applied to the control gates of the dummy cells D5 and D7 for generating the reference potential. Differential sense amplifier 1
6, the potential of MBL0 lowered from VPC by M0 pulling the drain current from MBL0, and the potential of MBL1 and MBL3 lowered from VPC by D5 and D7 from the connected MBL1 and MBL3 respectively pulling the drain current. After waiting until a difference from the potential can be detected, the state of M0 is sensed by performing an amplification operation. The differential sense amplifier 17 outputs the potential of MBL2 lowered from VPC by the drain current flowing from MBL2 to M2, and the connected MBL1 and MBL3.
After waiting until D5 and D7 can detect the difference between the potential of MBL1 and MBL3 lowered from VPC by drawing the drain current, the state of M2 is sensed by performing an amplification operation. During these amplification operations, YS0 to YS3 and EQSA are respectively opened. This allows the generation of the potential difference between MBL1 and MBL3 by both differential sense amplifiers 16 and 17.

FIG. 3 shows a change in bit line potential in a read cycle of the flash memory of FIG. Here, the description is given on the assumption that the memory cell to be read is, for example, M4. In the read cycle of M4,
BS0 and YS0 are closed and BWL, BSL, MBL0
And SBL4 are supplied with a required potential. As a result, a predetermined read voltage Vgs is applied between the control gate and the source of M4. As described above, the reference potential Vref for reading M4 is TS1, TS3, YS
1, YS3 and EQSA are closed, D1 and D3
Generated by Therefore, TDWL and TDSL
Are supplied with a required potential. As a result, the same read voltage Vgs as in the case of M4 is applied between the control gate and the source of each of D1 and D3.

Now, M4 is in the 0 state or the 1 state.
When M4 is in the 0 state, the M4 is at the read voltage Vgs.
Is applied between its control gate and source,
By drawing a large drain current from MBL0 through SBL4, the potential of MBL0 is greatly reduced. Even when M4 is in the 1 state, the potential of MBL0 is
Rather than maintaining the VPC as shown by the coarse dashed line in FIG. 3, it is lowered slightly. This is because a read voltage Vgs higher than the threshold voltage Vth of the memory cell in one state is applied (Vgs> Vth: see FIG. 2),
4 draws a small drain current from MBL0.

On the other hand, D1 and D3 draw drain currents from MBL1 and MBL3, respectively, when a read voltage Vgs is applied between their respective control gates and sources. Here, it is assumed that D1 is in the 0 state and D3 is in the 1 state. In this case, the current that D1 draws from MBL1 is M4 when M4 is in the 0 state.
Corresponds to the current drawn from MBL0. The current drawn by D3 from MBL3 corresponds to the current drawn by M4 from MBL0 when M4 is in the 1 state. Here, when recalling that MBL1 and MBL3 are connected to each other by EQSA, the potentials of these MBL1 and MBL3, that is, the reference potential Vref,
Instead of transitioning higher than the potential of MBL0 when M4 is in the 1 state, as shown by the fine broken line in FIG.
It can be seen that the potential changes at an intermediate level between the potential of MBL0 when M4 is in the 0 state and the potential of MBL0 when M4 is in the 1 state. Therefore, differential sense amplifier 16 can correctly sense the state of M4. Note that each of the MBLs 0 to 3 has the same load capacity,
In addition, it is preferable that each of the SBLs 0 to 7 has the same load capacity. Thereby, for example, the bit line path (MBL1 + SBL) from the differential sense amplifier 16 to D1 and D3
1 + MBL3 + SBL3) corresponds to the bit line path (MBL0 + SB) from the differential sense amplifier 16 to M4.
This is convenient because it is just twice the load capacity of L4).

As described above, according to the flash memory shown in FIG. 1, it is possible to achieve both a shortened program time and accurate reading. In addition, accurate read is guaranteed even when the read voltage Vgs unexpectedly increases due to an increase in the power supply voltage.

When the state of M4 is updated, D1 and D3 are each erased once and then set to, for example, the same state as the previous state. Thereby, M4,
The degree of deterioration of D1 and D3 is made uniform. Considering that there is a difference between the damage received by the gate oxide film during erasing and the damage received during programming, D1 and D3 are, after being erased once, respectively, when the state of M4 is updated. It is preferable to set the state opposite to the previous state. Thereby, the degree of deterioration of D1 and D3 is made uniform. The same applies to other combinations of memory cells and dummy cells. As shown in FIG.
The configuration of the flash memory, in which each of the flash memory and the bottom array 11 has a dummy cell, serves to equalize the degree of deterioration of the cell. The roles of the memory cell and the dummy cell in FIG. 1 can be exchanged as needed.

In the above example, even when the threshold voltage Vth of the memory cell in the programmed state is set higher than the maximum read voltage Vgsmax between the control gate and the source, an effect that an accurate reference potential Vref can be generated. Is obtained. As a result, even if the threshold voltage of the memory cell fluctuates due to the process condition, or the voltage applied to the memory cell fluctuates, the stored data can be read accurately.

[0027]

As described above, according to the present invention, the threshold voltage of the one-state memory cell is reduced, and the bit line connected to the zero-state dummy cell and the one-state dummy cell are connected. Since the reference potential in the read cycle is generated by connecting the read bit line to the read bit line, it is possible to achieve both shortening of the program time and accurate reading.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a flash memory according to the present invention.

FIG. 2 is a diagram showing a distribution of threshold voltages of memory cells in the flash memory of FIG. 1;

FIG. 3 is a diagram showing a change in bit line potential in a read cycle of the flash memory of FIG. 1;

FIG. 4 is a diagram showing a distribution of threshold voltages of memory cells in a conventional flash memory.

FIG. 5 is a diagram showing a change in bit line potential in a read cycle of a conventional flash memory.

[Explanation of symbols]

 Reference Signs List 10 Top array 11 Bottom array 12-15 Precharge circuit 16, 17 Differential sense amplifier BDSL Dummy source line BDWL Dummy word line BS0-3 Bit line selection switch BSL Source line BWL Word line D0-7 Dummy cell EQSA, EQSB Equalize switch M0 To 7 memory cells MBL0 to 3 Main bit line SBL0 to 7 Sub bit line TDSL Dummy source line TDWL Dummy word line TS0 to 3 Bit line selection switch TSL Source line TWL Word line Vgs Read voltage Vgsmax Maximum read voltage Vref Reference potential Vth Memory cell Threshold voltage VPC precharge potential YS0-3 column gate

Claims (19)

[Claims] An electrically erasable and programmable non-volatile semiconductor memory device, each having a control gate, a floating gate, a drain, and a source, and each having a low threshold voltage. An erase state and a program state in which more electrons are stored in the floating gate than in the erase state so as to have a threshold voltage higher than the threshold voltage in the erase state, A threshold voltage in the program state connected to first, second, and third memory cells set to be lower than a maximum read voltage between the control gate and the source; and a drain connected to the first memory cell. A first bit line, a second bit line connected to a drain of the second memory cell, and the third memory A third bit line connected to the drain of the first and second memory cells, and one of the second and third memory cells has the erase state, and the other has the program state. Means for setting the state of each of the memory cells, means for connecting the second bit line and the third bit line in a certain read cycle, and means for connecting the second bit line and the third bit line in a certain read cycle. 1st, 2nd
And a means for setting each of the third bit lines to a predetermined precharge potential; and in the read cycle, the first memory cell draws a drain current from the first bit line to thereby perform the precharge. The potential of the first bit line lowered from the potential and the precharge potential by drawing the drain current from the second and third bit lines to which the second and third memory cells are connected. A non-volatile semiconductor memory device, comprising: sensing means for sensing the state of the first memory cell by comparing the lowered potentials of the second and third bit lines. . 2. The nonvolatile semiconductor memory device according to claim 1, wherein a load capacity of the connected second and third bit lines is:
2. The nonvolatile semiconductor memory device according to claim 1, wherein the load capacity is twice the load capacity of the first bit line. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a connection between each drain of said first, second and third memory cells and said first, second and third bit lines is made. A nonvolatile semiconductor memory device, further comprising means for shutting off. 4. The non-volatile semiconductor memory device according to claim 1, wherein the second and third memory cells are erased once before the first memory cell is updated when the state of the first memory cell is updated. A non-volatile semiconductor memory device set to the same state as the above. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said second memory cell and said third memory cell are respectively erased and updated before and after the state of said first memory cell is updated. Characterized by being set in a state opposite to the state described above. 6. The nonvolatile semiconductor memory device according to claim 1, wherein a control gate, a floating gate, a drain,
An erased state having a source and having a low threshold voltage, and more electrons stored in the floating gate than the erased state so as to have a threshold voltage higher than the threshold voltage in the erased state. A fourth memory cell, wherein a threshold voltage in the program state is set lower than a maximum read voltage between the control gate and the source; A fourth bit line connected to the drain of the fourth memory cell and set to the precharge potential in an initial stage of the read cycle; and in the read cycle, the fourth memory cell is connected to the fourth bit. Potential of the fourth bit line lowered from the precharge potential by drawing a drain current from the line The second and third memory cells draw a drain current from the connected second and third bit lines, respectively, so that the potential of the second and third bit lines is lowered from the precharge potential. And means for sensing the state of the fourth memory cell by comparing 7. The nonvolatile semiconductor memory device according to claim 6, wherein a load capacitance of the connected second and third bit lines is:
A nonvolatile semiconductor memory device characterized in that the load capacity is twice as large as the load capacity of the fourth bit line. 8. The nonvolatile semiconductor memory device according to claim 6, wherein in said read cycle, said second bit line and said third bit line are sensed at the time when sensing of the states of said first and fourth memory cells is started. A non-volatile semiconductor memory device further comprising means for cutting off connection with the bit line. 9. The nonvolatile semiconductor memory device according to claim 6, wherein said nonvolatile semiconductor memory device includes first and second arrays, and said first and fourth memory cells are arranged in said first array. ,
The second and third memory cells belong to the second array, respectively, and the first array sets a reference potential used for sensing a state of the first and fourth memory cells to the second array.
And having a plurality of other memory cells for generating a reference potential used to sense the state of the other plurality of memory cells in the second array as generated by the third memory cell. A nonvolatile semiconductor memory device characterized by the above-mentioned. 10. The nonvolatile semiconductor memory device according to claim 6, wherein one of the first and fourth memory cells has the erase state and the other has the program state, respectively. Means for setting the state of each of the fourth and fourth memory cells; means for connecting the first bit line and the fourth bit line in another read cycle; and the other read cycle. In the initial stage of the first,
Means for setting each of the second, third and fourth bit lines to the precharge potential; and wherein in the another read cycle, the second memory cell draws a drain current from the second bit line. The second voltage lowered from the precharge potential by
And the first and fourth memory cells are pulled down from the precharge potential by drawing drain currents from the connected first and fourth bit lines, respectively. Means for sensing the state of the second memory cell by comparing the potential of the third bit line with the potential of the third bit line. The third current lowered from the precharge potential by drawing a drain current;
And the first and fourth memory cells are pulled down from the precharge potential by drawing drain currents from the connected first and fourth bit lines, respectively. Means for comparing the potential of the fourth bit line with the potential of the third memory cell to sense the state of the third memory cell. 11. The nonvolatile semiconductor memory device according to claim 10, wherein a load capacitance of said connected first and fourth bit lines is:
The nonvolatile semiconductor memory device according to claim 1, wherein each of the load capacitance of the second bit line and the load capacitance of the third bit line is twice as large. 12. An electrically erasable and programmable nonvolatile semiconductor memory device, each having a control gate, a floating gate, a drain, and a source, and each having a low threshold voltage. An erase state and a programmed state in which more electrons are stored in the floating gate than in the erase state so as to have a threshold voltage higher than the threshold voltage in the erase state can be taken. 1, a second and a third memory cell; a first bit line connected to a drain of the first memory cell; a second bit line connected to a drain of the second memory cell; A third bit line connected to the drain of the third memory cell, and one of the second and third memory cells is in the erased state; Means for setting the state of each of the second and third memory cells so as to have the program state, respectively; and the second bit line and the third bit line in a read cycle. Means for connecting the first and the second in an initial stage of the read cycle.
Means for setting each of the third and third bit lines to a predetermined precharge potential; and in the read cycle, at least one of the second and third memory cells is connected to the second and third memory cells. Means for sensing the state of the first memory cell using the potentials of the second and third bit lines lowered from the precharge potential by drawing a drain current from the third bit line. A nonvolatile semiconductor memory device. 13. The nonvolatile semiconductor memory device according to claim 12, wherein a load capacitance of the connected second and third bit lines is:
2. The nonvolatile semiconductor memory device according to claim 1, wherein the load capacity is twice the load capacity of the first bit line. 14. The nonvolatile semiconductor memory device according to claim 12, wherein a control gate, a floating gate, a drain,
An erased state having a source and having a low threshold voltage, and more electrons stored in the floating gate than the erased state so as to have a threshold voltage higher than the threshold voltage in the erased state. A fourth memory cell that can assume one of a programmed state and a fourth memory cell connected to a drain of the fourth memory cell and set to the precharge potential in an initial stage of the read cycle. And in the read cycle, at least one of the second and third memory cells draws a drain current from the connected second and third bit lines to lower the precharge potential. For sensing the state of the fourth memory cell using the potentials of the second and third bit lines. The nonvolatile semiconductor memory device, characterized in that it further includes a stage. 15. The nonvolatile semiconductor memory device according to claim 14, wherein a load capacity of the connected second and third bit lines is:
A nonvolatile semiconductor memory device characterized in that the load capacity is twice as large as the load capacity of the fourth bit line. 16. An erase state having a control gate, a floating gate, a drain, and a source, respectively, and each having a low threshold voltage, and a threshold voltage higher than the threshold voltage in the erase state. A first, a second, and a third memory cell that can take any one of a programmed state in which more electrons are stored in the floating gate than the erased state so as to have: A first bit line connected to the drain of the second memory cell; a second bit line connected to the drain of the second memory cell; and a third bit line connected to the drain of the third memory cell. A method of generating a reference potential in a non-volatile semiconductor memory device, comprising: a first memory cell, a second memory cell, and a second memory cell. Setting the state of each of the second and third memory cells so as to have the program state, respectively, and connecting the second bit line and the third bit line in a certain read cycle. And the first and second steps in an initial stage of the read cycle.
And setting each of the third bit lines to a predetermined precharge potential. In the read cycle, at least one of the second and third memory cells is connected to the second and third memory cells. The potential of the second and third bit lines lowered from the precharge potential by drawing a drain current from the third bit line is used as a reference potential when sensing the state of the first memory cell. A reference potential generating method characterized by the above-mentioned. 17. The reference potential generating method according to claim 16, wherein the load capacity of the connected second and third bit lines is twice as large as the load capacity of the first bit line. A method for generating a reference potential, further comprising the step of setting a load capacitance of each of the first to third bit lines. 18. An erased state having a control gate, a floating gate, a drain, and a source, each having a low threshold voltage, and a threshold voltage higher than the threshold voltage in the erased state. A first, a second, and a third memory cell that can take any one of a programmed state in which more electrons are stored in the floating gate than the erased state so as to have: A first bit line connected to the drain of the second memory cell; a second bit line connected to the drain of the second memory cell; and a third bit line connected to the drain of the third memory cell. A reference potential generation circuit in a nonvolatile semiconductor memory device comprising: one of the second and third memory cells in the erase state; Means for setting the state of each of the second and third memory cells so as to have the program state, respectively; and setting the second bit line and the third bit line in a read cycle. Means for connecting; the first and the second in an early stage of the read cycle.
And a means for setting each of the third bit lines to a predetermined precharge potential. In the read cycle, at least one of the second and third memory cells is connected to the second memory cell. The potential of the second and third bit lines lowered from the precharge potential by drawing a drain current from the third bit line is used as a reference potential when sensing the state of the first memory cell. A reference potential generation circuit, which is used. 19. The reference potential generation circuit according to claim 18, wherein a load capacitance of the connected second and third bit lines is:
A reference potential generation circuit, wherein the reference potential generation circuit is twice as large as the load capacitance of the first bit line.