JP2001024166A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent decline in coverage of an insulating film by forming recessed sections on a first insulating film and, after forming a conductive film in accordance with the shapes of the recessed sections, burying second insulating films in the recessed sections, and etching the conductive film by isotropic etching by using the second insulating films as a mask. SOLUTION: After a resist pattern is formed on a sacrificial oxide film 35 of a first insulating film, openings 36 and 37 for forming storage nodes are formed through the oxide film 35 and an SiN film 34. Then a conductive film 38 is formed on the surface of the oxide film 35 and the internal wall surfaces and bottom faces of the openings 36 and 37. Consequently, recessed sections 36a and 37a are formed of the conductive film 38 in the openings 36 and 37, respectively. In addition, NSG films 39 are buried in the recessed sections 36a and 37a as second insulating films. Moreover, the NSG films 39 are etched back by isotropic etching until the conductive film 38 is exposed so that the NSG films 39 may be buried partially in the recessed sections 36a and 37a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a dynamic RAM (DRAM).
This is suitable for application to the formation of bit lines and the formation of lower electrodes in (RAM).

[0002]

2. Description of the Related Art Conventionally, MOS field-effect transistors (M
In the formation of the diffusion layer in the OSFET), first,
After a gate electrode is formed on a silicon (Si) substrate via a gate oxide film, a sidewall spacer is formed on a side wall of the gate electrode, and impurities are added to the Si substrate using the gate electrode and the sidewall spacer as a mask. A method of forming a diffusion layer in a self-aligned manner by introducing it is used.

In general, silicon oxide (SiO ₂ ) is used as a material of a sidewall spacer serving as a mask when introducing the impurity. However, when the element isolation region is formed by using the LOCOS method, it is necessary to reduce the field oxide film and the film thickness in order to suppress a bird's beak caused by miniaturization of the element.

As described above, when the field oxide film is thinned, the field oxide film is further thinned when forming the above-described sidewall spacer.
As a result, when impurities are introduced into the Si substrate to form a diffusion layer, the impurities penetrate the field oxide film, causing a problem of deteriorating element isolation characteristics.

Therefore, as one means for solving this problem, a method has been considered in which the side wall spacer is made of polycrystalline Si. That is, since the selectivity between polycrystalline Si and the SiO ₂ film in etching is large,
By forming the sidewall spacers using polycrystalline Si, it is possible to prevent the thickness of the field oxide film from being reduced during the etch back.

By the way, the D having the MOSFET described above
In the RAM, the storage node electrode is formed as follows.

That is, as shown in FIG. 14, after forming a sacrificial oxide film 101 on a substrate (not shown), an opening 102 is formed in the sacrificial oxide film 101. Next, an amorphous Si film 103 is formed on the entire surface so as to have a shape along the inner wall and the bottom surface of the opening 102. As a result, a concave portion 103a composed of the amorphous Si film 103 is formed inside the opening 102. Next, this recess 103
An oxide film 104 is embedded in a.

Next, using the oxide film 104 as a mask, the sacrificial oxide film 10 is formed by reactive ion etching (RIE).
The portion of the exposed amorphous Si film 103 on the substrate 1 is removed by etching. In FIG. 14, the portion of the amorphous Si film 103 that has been etched away is indicated by a dotted line. Thereafter, by removing the oxide film 104 and the sacrificial oxide film 101, a so-called cylindrical storage node electrode having a U-shaped cross section is left.

[0009]

As a result of studying the above-mentioned prior art, the present inventors have found the following problems in a method of forming a sidewall spacer from polycrystalline Si in forming a MOSFET. Reached.

That is, when a method using polycrystalline Si as a material for the sidewall spacer is adopted, polycrystalline S
Since i has conductivity, if it remains, a defect due to a short circuit occurs. In order to avoid this short circuit, the sidewall spacer must be removed after forming the diffusion layer. With this, MOS
Additional steps are required in the FET manufacturing process.

Further, the present inventor has found the following problems in a method of forming a cylindrical storage node electrode.

That is, as shown in FIG. 14, when the exposed amorphous Si film 103 on the sacrificial oxide film 101 is removed by etching by RIE, the sacrificial oxide film 101 and the oxide film 104 of the amorphous Si film 103 are removed. The central portion of the upper end of the portion sandwiched between the portions is shaved to form an acute angle portion (the acute angle portion 105), which results in a so-called crab shape. If the acute angle portion 105 is present at the upper end of the storage node electrode, the electric field is concentrated on the acute angle portion 105, causing fatigue of the insulating film or lowering the coverage of the insulating film. Therefore, an additional step for rounding the acute angle portion 105 is required, and this additional step is actually employed.

Further, with the miniaturization of the device, in order to secure the capacitance C _s in a capacitor, hemispherical Si grains in the storage node electrode (Hemi-spherical Sil
It is necessary to apply a technique for increasing the surface area of the electrode, such as forming an icongrain (HSG). On the other hand, with the miniaturization of the element, the aspect ratio of the concave portion 103a in which the above-described oxide film 104 is embedded has been increasing. Therefore, as the oxide film 104, a non-doped silicate glass (NSG) film formed by a low-pressure chemical vapor deposition (CVD) method using tetraethoxysilane (TEOS) gas with good coverage is used.

Incidentally, the formation of the HSG requires the migration of Si. Therefore, it is necessary that the film quality is amorphous when the storage node electrode is left in a cylindrical shape. However, when an NSG film is used as the oxide film 104, the film forming temperature of the NSG film becomes 700
Since the temperature is as high as about ° C., the oxide film 104
Is embedded, the amorphous Si film 103 is crystallized. This is a factor that hinders HSG formation.

Accordingly, an object of the present invention is to prevent an acute angle portion from being formed when an amorphous semiconductor layer is removed by etching, and an electric field is concentrated on the acute angle portion to cause fatigue of an insulating film. It is another object of the present invention to provide a method for manufacturing a semiconductor device, which can prevent a decrease in the coverage of an insulating film.

It is another object of the present invention to provide a method of manufacturing a semiconductor device which does not require an additional step of removing a conductive sidewall.

[0017]

In order to achieve the above object, a first aspect of the present invention is a method for forming a concave portion in a first insulating film and forming a conductive film along the shape of the concave portion. A method of manufacturing a semiconductor device, comprising: a step of: embedding a second insulating film in a concave portion formed by a conductive film; and a step of etching the conductive film using the second insulating film as a mask. The conductive film is etched by an etching method.

In the first invention, typically, the semiconductor device has a capacitor, and the conductive film forms an electrode of the capacitor. In the first invention, after the conductive film is etched, the first insulating film and the second insulating film are removed to form an electrode of the capacitor having a U-shaped cross section.

In the first aspect, preferably, the second aspect
Is formed at a temperature equal to or lower than the formation temperature in forming the conductive film. Further, in the first invention, preferably, the conductive film is an amorphous semiconductor film doped with impurities, and hemispherical grains are formed on the surface of the amorphous semiconductor film.

In the first invention, typically, the isotropic etching method is a plasma etching method, but other isotropic etching methods may be used. For example, a wet etching method may be used. It is.

In the first invention, typically, the conductive film is an amorphous semiconductor film doped with impurities.
When an electrode of a capacitor is formed using the conductive film, hemispherical grains are formed on the surface of the conductive film made of an amorphous semiconductor in order to increase the capacitance of the capacitor. Then, in order to favorably form the hemispherical grains, the second insulating film is typically formed at a temperature equal to or lower than the formation temperature in forming the conductive film. In the first invention, typically, the amorphous semiconductor film is an amorphous silicon film. Then, in order to maintain the amorphous state of the amorphous silicon film and form hemispherical silicon grains on the surface thereof, the second insulating film is formed at a temperature at which the amorphous silicon does not crystallize. Is formed at a temperature of 430 ° C. or more and 530 ° C. or less.

According to a second aspect of the present invention, there is provided a method of forming a first conductive pattern on a semiconductor substrate, comprising the steps of:
Forming a first insulating film on the semiconductor substrate so as to cover the first pattern; and forming a first insulating film on the side wall surface of the first pattern.
Forming a conductive side wall with the insulating film interposed therebetween, and forming a conductive second pattern on at least the side wall so as to be connected to the side wall. Of the semiconductor device.

In the second invention, typically, the semiconductor device has a dynamic RAM (DRAM), and the semiconductor device includes the second pattern and the sidewall connected to the second pattern. Construct a bit line of a DRAM.

In the second invention, typically, the semiconductor device has a dynamic RAM, and a word line of the dynamic RAM is constituted by the first pattern.

In the second invention, typically, a resist pattern is formed on the first insulating film and the side wall after the step of forming the side wall and before the step of forming the second pattern. Then, the connection hole is formed in the first insulating film by etching the first insulating film using the resist pattern and the sidewall as a mask.

In the second aspect, typically, the sidewall is made of a polycrystalline semiconductor. Also, this second
In the invention, the sidewalls are typically made of polycrystalline silicon, preferably, polycrystalline silicon doped with impurities.

In the second aspect, typically, the sidewall is made of an amorphous semiconductor. Also, this second
In the present invention, the sidewalls are typically made of amorphous silicon, and preferably are made of amorphous silicon doped with impurities.

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention having the above-described structure, a conductive film having a shape along a recess is formed by an isotropic etching method using the second insulating film as a mask. By performing the etching, the upper end of the concave portion in the conductive film can be uniformly etched.

According to the method of manufacturing a semiconductor device according to the second aspect of the present invention, the first insulating film is formed so as to cover the first conductive pattern formed on the semiconductor substrate. A sidewall having conductivity is formed on a side wall surface of the first pattern via a first insulating film, and a second pattern having conductivity is formed on at least the sidewall so as to be connected to the sidewall. By being formed, a pattern such as a wiring can be constituted by the second pattern and the side wall, and unnecessary side walls at the time of patterning the second pattern are simultaneously formed. Can be removed.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the following embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, D according to the first embodiment of the present invention will be described.
A method for manufacturing a semiconductor device having a RAM will be described. 1 to 12 show a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

In the first embodiment, first, as shown in FIG. 1A, a predetermined portion of the Si
Element isolation is performed by selectively performing thermal oxidation by the OCOS method to form an element isolation region 2 made of a field oxide film. Here, the film thickness of the element isolation region 2 is set to a necessary minimum film thickness so that impurities implanted in a later step do not penetrate into the Si substrate 1.
50 nm. Thereafter, a gate oxide film 3 made of a SiO ₂ film is formed on the surface of the active region surrounded by the element isolation region 2 by, for example, a thermal oxidation method.

Next, as shown in FIG. 1B, an amorphous Si film is formed on the entire surface by doping n-type impurity phosphorus (P) by, for example, a CVD method, thereby forming phosphorus-doped amorphous Si (P Doped). Amorphas Silicon, PD
AS) The film 4 is formed. Next, a WSi ₂ film 5 is formed on the entire surface by, for example, a sputtering method. here,
The thickness of each of the PDAS film 4 and the WSi ₂ film 5 is, for example, 100 nm. Then, the WSi ₂ film 5 and the PD
By patterning the AS film 4 into a predetermined shape,
A gate electrode 6 is formed in the logic circuit portion, word lines 7 and 8 used for the illustrated memory cells, and word lines 9 and 10 used for other memory cells are formed in the memory cell portion. Thereafter, a predetermined impurity is ion-implanted into the Si substrate 1 using the gate electrode 6 of the logic circuit portion as a mask, so that the diffusion layer 11 is self-aligned with the gate electrode 6.
a and the word lines 7 and 8 in the memory cell portion.
By using a mask as a mask, a predetermined impurity is ion-implanted into the Si substrate 1 to form the diffusion layer 12 in a self-aligned manner with respect to the word lines 7 and 8.

Next, as shown in FIG. 2A, for example, TEO
An NSG film 1 is formed on the entire surface by a reduced pressure CVD method using S gas.
Form 3 The thickness of the NSG film 13 is, for example, 50 n.
m. Then, in an oxygen (O ₂ ) gas atmosphere,
For example, a thermal oxidation process is performed by heating to 850 ° C., and the end of the gate is oxidized by about 5 nm.

Next, as shown in FIG. 2B, a PDAS film is formed by forming an amorphous Si film on the entire surface by doping P with, for example, a CVD method. This PD
The impurity concentration of the AS film is, for example, 2 × 10 ²⁰ cm ⁻² ,
The film thickness is, for example, 100 nm. Thereafter, for example, electron cyclotron resonance (ECR)
The PSG film is etched back using a plasma etching apparatus, so that the NSG film 13 is formed on the side walls of the gate electrode 6 and the word lines 7, 8, 9, and 10, respectively.
Through the sidewall spacer 1 made of PDAS
4, 15, 16, 17, and 18 are formed. Here, as an example of the etching conditions, a mixed gas of chlorine (Cl ₂ ) gas and hydrogen bromide (HBr) gas is used as an etching gas, the flow rates thereof are respectively 40 sccm and 100 sccm, the pressure is 1 Pa, and RF power to 70
W.

Next, in the logic circuit portion, a predetermined impurity is selectively ion-implanted using the gate electrode 6 and the side wall spacer 14 as a mask, thereby forming the diffusion layer 11 having a higher concentration than the impurity concentration in the diffusion layer 11a. Form. Thus, an LDD structure is formed in the logic circuit portion.

Next, as shown in FIG. 3, a resist pattern 19 having an opening 19a in a bit contact formation region is formed on the entire surface of the Si substrate 1. Next, using the resist pattern 19 as a mask, for example, using a magnetron plasma etching apparatus,
6, the NSG film 13 and the gate oxide film 3 are sequentially etched until the surface of the diffusion layer 12 is exposed. Thereby, the connection hole 20 is formed. At this time, even if the misalignment of the opening 19a of the resist pattern 19 occurs, the side wall spacer 1
Since the masks 5 and 16 serve as etching masks, it is possible to prevent a bit contact to be formed later and the word lines 7 and 8 from causing insulation failure. Here, as an example of the etching conditions, a mixed gas of tetracarbon octafluoride (C ₄ F ₈ ) gas, carbon monoxide (CO) gas, and argon (Ar) gas is used as an etching gas. The flow rates are 10 sccm, 300 sccm, and 400 sccm, respectively, the pressure is 5.3 Pa, and the RF power is 1700 W. After that, the resist pattern 19 is removed.

Next, as shown in FIG. 4A, the exposed surfaces of the side wall spacers 16 and 17 on the side walls of the connection hole 20 and the S surface are formed using 1% diluted hydrofluoric acid (100: 1, DHF).
The natural oxide film on the exposed surface of the i-substrate 1 is removed. Next, the PDA film 21 and the W
An Si ₂ film 22 is sequentially formed. The PDAS film 21 and the WSi ₂ film 22 have a thickness of 50 nm and 10 nm, respectively.
0 nm.

Next, as shown in FIG. 4B, after forming a bit line-shaped resist pattern (not shown) on the WSi ₂ film, the resist pattern is used as a mask to form a resist pattern using, for example, an ECR plasma etching apparatus. The bit line 23 is formed by performing stepwise etching. In this three-stage etching, first, a WSi ₂ film is etched as a first etching, and a PSi is etched as a second etching.
Sidewall spacers 1 other than the side wall spacers 15 and 16 which become a part of the DAS film 21 and the bit line 23
4 to 18 are etched until the surface of the NSG film 13 starts to be exposed, and as a third etching, etching is performed so that the PDAS material does not remain. Thereby, W
The Si ₂ film 22 and the PDAS film 21 are sequentially etched, and the side wall spacers 1 other than the side wall spacers 15 and 16 that become a part of the bit line 23 are formed.
4 to 18 are removed by etching. Note that the etching conditions in the three-stage etching are the side wall spacers 14 other than the side wall spacers 15 and 16.
To 18 and the PDAS film 21 are almost completely removed.
The condition is selected so that the SG film 13 is not etched. This is to prevent the gate electrode and the diffusion layer formed in the lower layer from being exposed and being etched. Here, a specific example of the etching conditions in the three-stage etching will be described below. That is, the first
The etching conditions for the etching are a mixed gas of Cl ₂ gas and O ₂ gas as an etching gas, the flow rates thereof are respectively 80 sccm and 12 sccm, the pressure is 0.4 Pa, and the RF power is 70 W. The etching conditions in the second etching were as follows: a mixed gas of Cl ₂ gas and O ₂ gas was used as an etching gas, and the flow rates thereof were 80 sccm and 12 sc, respectively.
cm, pressure 0.4 Pa, and RF power 40 W. The etching conditions in the third etching were such that a mixed gas of HBr gas and O ₂ gas was used as an etching gas, and the flow rates thereof were each 100 sccm.
, 10 sccm, the pressure is 0.4 Pa, and the RF power is 40 W.

Next, as shown in FIG. 5, an interlayer insulating film 24 made of, for example, an SiO ₂ film that can be planarized is formed so as to cover the entire surface by, for example, a plasma CVD method.

Next, as shown in FIG. 6, a resist pattern (not shown) having an opening at a portion where a storage node contact is formed is formed on interlayer insulating film 24 by a lithography process, and this resist pattern is used as a mask. For example, the interlayer insulating film 24 is etched using a magnetron plasma etching apparatus. Thus, openings 25 and 26 are formed in the interlayer insulating film 24 on both sides of the bit line. Here, as an example of etching conditions in forming the opening, a mixed gas of methane trifluoride (CHF ₃ ) gas, O ₂ gas and Ar gas is used as an etching gas, and the flow rates thereof are respectively 40 sccm.
5 sccm and 50 sccm, pressure 5.3P
a, RF power is 1600 W. After that, the resist pattern is removed.

Next, an NSG film 27 is formed on the entire surface by, for example, a low pressure CVD method using TEOS gas. The thickness of the NSG film 27 is, for example, 50 nm. And
The NSG film 27 covers the bottom surfaces and inner walls of the openings 25 and 26.

Next, as shown in FIG. 7, a PDOS film is formed on the entire surface by, for example, a plasma CVD method. This PD
The thickness of the AS film is, for example, 100 nm. Thereafter, the PDAS film is etched back by using, for example, an ECR plasma etching apparatus, whereby sidewalls 28 and 29 made of PDAS are formed on the inner walls of the openings 25 and 26 via the NSG film 27, respectively. Here, as an example of the etch-back conditions, a mixed gas of Cl ₂ gas and He gas is used as an etching gas, the flow rates thereof are respectively 200 sccm and 100 sccm, the pressure is 1 Pa, and the RF power is 80 W. Subsequently, the NSG film 27 on the interlayer insulating film 24 is etched using, for example, a magnetron plasma etching apparatus, and the NSG film 27 on the bottom surfaces of the openings 25 and 26 is formed using the respective sidewalls 28 and 29 as masks. Etch. As a result, connection holes 30 and 31 are formed inside the openings 25 and 26, respectively. Here, as an example of the etching conditions in forming the connection holes 30 and 31, a mixed gas of CHF ₃ gas, CO gas and O ₂ gas is used as an etching gas, and the flow rates thereof are 20 sccm and 180 sc, respectively.
cm and 2 sccm, the pressure is 4 Pa, and the RF power is 1500 W.

Next, 1% diluted hydrofluoric acid (100: 1, DH
Using F), the native oxide film (not shown) on the exposed surface is removed.

Next, as shown in FIG. 8, a PDAS film is formed on the entire surface by, for example, a CVD method so as to be embedded in the connection holes 30 and 31. The thickness of this PDAS film is, for example, 300 nm. After that, the PDAS film is etched back using, for example, an ECR plasma etching apparatus, so that the inside of the connection holes 30 and 31 is formed.
Contact plugs 32 and 33 each made of PDAS
Leave. Here, as an example of etching conditions for forming the contact plugs 32 and 33, a mixed gas of Cl ₂ gas and sulfur hexafluoride (SF ₆ ) gas is used as an etching gas, and the flow rates thereof are each set to 105 s.
ccm and 15 sccm, pressure 0.4 Pa, RF power 35 W.

Next, the upper surfaces of the interlayer insulating film 24 and the contact plugs 32 and 33 are polished by, for example, a CMP method using potassium hydroxide (KOH) and silica, so that the surface is planarized. Next, a silicon nitride (SiN) film 34 as an etching stopper film is formed on the planarized interlayer insulating film 24 and the contact plugs 32 and 33. The thickness of the SiN film 34 is, for example, 50 nm.

Next, as shown in FIG. 9, O ₃ gas and TE
A sacrificial oxide film 35 made of, for example, a SiO ₂ film is formed on the entire surface of the SiN film 34 by a CVD method using an OS gas. The thickness of the sacrificial oxide film 35 is, for example, 600 nm.

Next, as shown in FIG. 10, a resist pattern (not shown) having an opening at a portion where a storage node is formed is formed on the sacrificial oxide film 35 by a lithography process, and this resist pattern is masked. By performing two-stage etching using, for example, a magnetron plasma etching apparatus, the sacrificial oxide film 35 and S
Openings 36 and 37 for forming storage nodes are formed in the iN film 34. In this two-stage etching, first, as the first etching, the sacrificial oxide film 35 is etched using the SiN film 34 as an etching stopper, and as the second etching, the SiN film is etched until the upper surfaces of the contact plugs 32 and 33 are exposed. The film 34 is etched. Here, a specific example of the etching conditions in the two-stage etching will be described below. That is, the etching conditions in the first etching are as follows: a mixed gas of tetracarbon octafluoride (C ₄ F ₈ ) gas, CO gas, Ar gas and O ₂ gas is used as the etching gas, and their flow rates are each 8 scc
m, 150 sccm, 200 sccm and 3 sccm
And the pressure is 5.3 Pa and the RF power is 1700 W. The etching conditions for the second etching were as follows: a mixed gas of CHF ₃ gas, CO gas and O ₂ gas was used as an etching gas, the flow rates thereof were 40 sccm, 160 sccm and 14 sccm, the pressure was 5.3 Pa, and the RF power was Is set to 1000 W. After that, the resist pattern is removed.

Next, after the natural oxide film formed on the surface is removed, the entire surface of the substrate is subjected to PDAS, for example, by a plasma CVD method.
A film 38 is formed. The PTAS film 38 has a thickness of, for example, 100 nm, and is formed along the surface of the sacrificial oxide film 35 and the inner walls and bottom surfaces of the openings 36 and 37. Then, the PDAS film 38 is provided inside the openings 36 and 37, respectively.
Are formed.

Next, an NSG film 39 is formed on the entire surface so as to be buried in the recesses 36a and 37a by, for example, a plasma CVD method using an O ₃ gas and a TEOS gas. Here, the thickness of the NSG film 39 is
It is determined by the size of the opening width of another pattern such as an alignment mark not shown above. In the first embodiment, the maximum value of the opening width in another pattern on the Si substrate 1 is, for example, 1 μm. Therefore, the film thickness is selected to be, for example, 500 nm.

Subsequently, NS is performed by using, for example, a parallel plate type plasma etching apparatus until the PDAS film 38 is exposed.
By etching back the G film 39, the concave portions 36a,
A part of the NSG film 39 is embedded in the inside of 37a. Here, as an example of the etching conditions of the NSG film 39, a mixed gas of CF ₄ gas and Ar gas is used as an etching gas, and the flow rate thereof is 40 sccm, respectively.
800 sccm, the pressure is 240 Pa, and the RF power is 1400 W.

Next, using an NSG film 38 buried in the recesses 36a and 37a as a mask, a sacrificial process is performed using an isotropic etching method such as a parallel plate type isotropic plasma etching device. Oxide film 35
The PDA film 38 exposed above is removed by isotropic etching. As an example of the etching conditions in the isotropic etching of the PDAS film 38, the temperature of the lower electrode in the parallel plate type isotropic plasma etching apparatus is set to 120 ° C., and a mixture of CF ₄ gas and O ₂ gas as etching gas Gases are used, the flow rates thereof are 210 sccm and 90 sccm, respectively, the pressure is 70 Pa, and the power is 700 W.

Next, as shown in FIG.
By a wet etching method using hydrofluoric acid (10: 1, HF) with a concentration, the sacrificial oxide film 35 is etched away using the SiN film 34 as an etching stopper, and the NSG film 39 inside the concave portions 36a and 37a is etched away. . Thus, storage nodes 40 and 41 having a U-shaped cross section, that is, a so-called cylindrical shape are left.

By performing isotropic etching on the PDES film 38 exposed on the sacrificial oxide film 35 in this manner, a crab-shaped claw is formed on the upper ends of the storage nodes 40 and 41 by conventional etching. The formation of sharp corners can be prevented, and favorable electrode shapes can be obtained as the storage nodes 40 and 41.

Thereafter, as shown in FIG. 12, capacitor insulating film 42 made of a laminated film of a nitride film and an oxide film or a laminated film in which the nitride film is sandwiched between oxide films so as to cover the exposed surface. To form Next, the capacitor insulating film 42
The so as to cover, by sequentially forming a polycrystalline Si film and the WSi _x film on the capacitor insulating film 42, a conductive film of polycide structure. Thereafter, the conductive film is patterned into a predetermined shape together with the underlying capacitor insulating film 42 and SiN film 34 to form a plate electrode 43 having a polycide structure.

Next, an interlayer insulating film 44 made of, for example, a SiO ₂ film is formed on the entire surface. Thereafter, the interlayer insulating film 44 is polished by, for example, a CMP method to planarize the surface.

Next, in the logic circuit portion, a predetermined portion of the interlayer insulating film 44 and the interlayer insulating film 24 are selectively etched to form a contact hole 45. Next, a contact plug 47 is buried inside the contact hole 45 using the adhesion layer 46 as a base film.

Next, after an adhesion layer 48 made of, for example, a TiN / Ti film, an Al alloy film 49 and a TiN film 50 are sequentially formed on the interlayer insulating film 44 by, for example, a sputtering method, the TiN film 50 is formed by, for example, an RIE method. , Al alloy film 49 and adhesion layer 48 are sequentially etched until the surface of interlayer insulating film 44 is exposed. Thus, a wiring 51 having a laminated structure is formed on the interlayer insulating film 44.

Thereafter, a semiconductor device is manufactured by sequentially forming an interlayer insulating film, a connection hole and a connection hole plug by a conventionally known method.

As described above, according to the method for fabricating the semiconductor device according to the first embodiment, after forming the sidewall spacers 14 to 18 made of PDA having conductivity and removing the resist pattern 19, the resist is removed. By forming the connection hole 20 using the pattern 19 and the sidewall spacers 15 and 16 as a mask, a contact with a large margin for alignment can be formed. In addition, the side wall spacers 15 and 16 of the side wall spacers 14 to 18 are configured as a part of the bit line, and the unnecessary side wall spacers 14 to 18 are formed simultaneously with the patterning of the PDAS film 21 formed thereon. By removing 18, it is not necessary to perform the step of removing the sidewall spacers 14 to 18 in a separate step. Further, since the PDA film is used as the sidewall spacer, the element isolation region 2 can be removed when the sidewall spacers 14 to 18 are removed.
Can be prevented from being etched, so that impurities can be prevented from passing through the element isolation region 2 during ion implantation, and deterioration of element isolation characteristics can be prevented. After the openings 36 and 37 are formed in the sacrificial oxide film 35, a PTAS film 38 is formed on the entire surface so as to cover the bottom and side walls of the openings 36 and 37.
After the NSG film 39 is formed so as to be buried in the recesses 36a and 37a formed by the AS film 38, the exposed portion of the PDAS film 38 is etched and stored by using an isotropic etching method. By forming the nodes 40 and 41, it is possible to prevent an acute angle portion from being generated at the tips of the storage nodes 40 and 41, so that it is not necessary to add a step of rounding the tips. And
Concentration of an electric field at the tips of the storage nodes 40 and 41 can be prevented, and fatigue of the insulating film for a capacitor formed after the formation of the storage nodes 40 and 41 can be prevented. Therefore, a highly reliable semiconductor device having a memory cell such as a DRAM can be obtained.

Next, D according to the second embodiment of the present invention will be described.
A method for manufacturing a semiconductor device having a RAM will be described.

In the second embodiment, similarly to the first embodiment, the formation of the PDOS film 38 (FIG. 1)
0), an NSG film is formed on the entire surface of the PDA film 38 by, for example, a plasma CVD method using a mixed gas of O ₃ gas and TEOS gas. Form 39. This NSG
The thickness of the film 39 is, for example, 500 nm. Also, this N
The deposition temperature for forming the SG film 39 is at least PDA
Selected from a temperature range in which the amorphous state of the S film 38 is maintained;
Specifically, it is selected from 430 to 530 ° C. This enables formation of HSG, which will be described later.

Thereafter, as in the first embodiment, N
The SG film 39 is etched back.
Using the NSG film 39 buried in 7a as a mask, the exposed PRAS film 38 is removed by isotropic etching. Then, by wet etching,
Sacrificial oxide film 35 using iN film 34 as an etching stopper
And the NSG film 39 inside the recesses 36a and 37a is etched away. Thereby, the storage node 4 having a U-shaped cross section and a cylindrical shape is formed.
0 and 41 are left.

Next, HS is applied to the surfaces of the storage nodes 40 and 41.
G is formed. That is, first, the Si substrate 1 is loaded into a reaction chamber (not shown), and then, for example, a SiH ₄ gas is supplied into the reaction chamber, thereby the PDAS
A nucleus of Si grains (not shown) is formed on the exposed surfaces of the storage nodes 40 and 41 composed of the film 38. Here, as an example of conditions for forming the nuclei of the Si grains, the heating temperature is 560 ° C., and the pressure is 1 × 10 ⁻³ Torr.

Next, when the nuclei of the Si grains are formed, the supply of the SiH ₄ gas into the reaction chamber is stopped.
For example, in a high vacuum of about 1 × 10 ⁻⁸ Torr,
The substrate 1 is heated. Thereby, the storage nodes 40 and 41
HSG40 centered on the Si grain nucleus
a, 41a are formed. These HSGs 40a, 41
In forming a, the heating temperature is 560 ° C. The surface area of the storage nodes 40 and 41 is HSG 40a,
It increases about 2-2.6 times before and after the formation of 41a.

Thereafter, in the same manner as in the first embodiment, a capacitor insulating film, an interlayer insulating film, and wiring are formed, and a semiconductor device having a desired DRAM is manufactured.

As described above, according to the method of manufacturing the semiconductor device according to the second embodiment, the processes up to the formation of the storage nodes 40 and 41 made of the PDAS film 38 are performed in the same manner as in the first embodiment. Accordingly, the same effect as in the first embodiment can be obtained. At the same time, since the NSG film 39 is formed within a temperature range of 430 to 530 ° C., the amorphous state of the PTAS film 38 can be maintained at least until the HSG is formed. HSGs 40a, 40g,
1a can be formed favorably. Also, HSG
40a, 41a can be formed to increase the surface area of the storage nodes 40, 41 by about 2-2.6 times,
The height of the storage nodes 40 and 41 in the capacitor electrode can be reduced as compared with the case where the HSG is not formed. Thereby, the step of the interlayer insulating film formed thereover, such as the interlayer insulating film 44 in the first embodiment, can be reduced, so that the surface of the interlayer insulating film can be easily flattened.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, the numerical values given in the above embodiments are merely examples, and different numerical values may be used as needed.

In the first embodiment, for example, the PDA is used as the side wall spacers 14-18.
Although an S film is used, as a sidewall spacer,
It is also possible to use a polycrystalline Si film, a polycrystalline Si film doped with impurities, or a non-doped amorphous Si film.

In the first embodiment, for example, after the plate electrode 43 and the interlayer insulating film 44 are sequentially formed, the surface of the interlayer insulating film 44 is planarized by the CMP method, and the wiring is formed on the upper layer. After the plate electrode 43 and the interlayer insulating film 44 are sequentially formed,
After polishing is performed by using the surface of the plate electrode 43 as a polishing stopper by a method, a new interlayer insulating film is formed on the upper surfaces of the plate electrode 43 and the interlayer insulating film 44, and the interlayer insulating film is planarized. A wiring may be formed on the upper layer.

[0072] Also, for example, in the first embodiment described above, although using the WSi _x as the material of the plate electrode 43, a polycrystalline Si film and W as a plate electrode 43
Si _x film is also possible to sequentially form the polycide structure, it is also possible to use a film including a Ti film and TiN film or W film.

[0073]

As described above, according to the first aspect of the present invention, a concave portion is formed in the first insulating film, and a conductive film is formed along the shape of the concave portion. When the conductive film is etched using the second insulating film as a mask and the conductive film is etched using the second insulating film as a mask, the conductive film is etched by the isotropic etching method. Since it is possible to prevent the formation of a crab-shaped acute angle portion, fatigue of the insulating film formed on the upper layer and junction leakage can be prevented. Therefore, when this conductive film is used as a lower electrode of a DRAM capacitor, a highly reliable semiconductor device having a DRAM can be obtained.

Further, according to the second aspect of the present invention, the first insulating film is formed so as to cover the conductive first pattern formed on the semiconductor substrate. A sidewall having conductivity is formed on a side wall surface of the first insulating film via a first insulating film, and a second pattern having conductivity is formed on at least the sidewall so as to be connected to the sidewall. Accordingly, a pattern such as a wiring can be formed by the second pattern and the side wall, and the alignment margin when the second pattern is brought into contact with a lower conductive layer or the like can be improved. . Further, unnecessary sidewalls can be removed at the same time as patterning of the second pattern, so that the number of steps for removing the conductive sidewalls can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 10 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 12 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view for explaining a problem according to the related art.

[Explanation of symbols]

2 ・ ・ ・ Element isolation region, 4, 21, 38 ・ ・ ・ PDAS
Film, 6 ... gate electrode, 7, 8, 9, 10 ... word line, 13, 27, 39 ... NSG film, 14, 15,
16, 17, 18 ... sidewall spacers, 23
... Bit line, 35 ... Sacrificial oxide film, 36,37
..Openings, 36a, 37a ... concave portions, 40, 41
.Storage nodes, 40a, 41a... HSG

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoshihisa Matoba 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5F004 AA11 BA13 BA14 CA01 DA00 DA01 DA04 DA16 DA18 DA22 DA23 DA26 DA30 DB00 DB02 DB03 DB12 DB17 DB28 DB30 EA10 EA12 EA23 EA28 EA33 EB01 EB02 EB03 EB08 FA02 5F083 AD24 GA06 GA21 JA04 JA32 JA33 JA35 KA05 MA06 MA17 NA02 PR03 PR05 PR07 PR12 PR21 PR36 PR39 PR40

Claims (19)

[Claims] A step of forming a recess in the first insulating film; a step of forming a conductive film along the shape of the recess; and a step of embedding a second insulating film in the recess formed by the conductive film. And a step of etching the conductive film using the second insulating film as a mask, wherein the etching of the conductive film is performed by an isotropic etching method. Manufacturing method of a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor device has a capacitor, and said conductive film forms an electrode of said capacitor. 3. After performing the etching of the conductive film, the first insulating film and the second insulating film are removed to form the electrode having a U-shaped cross section. 3. The method for manufacturing a semiconductor device according to claim 2, wherein: 4. The method according to claim 1, wherein said isotropic etching method is a plasma etching method. 5. The method according to claim 1, wherein said second insulating film is formed at a temperature equal to or lower than a temperature at which said conductive film is formed. 6. The method according to claim 1, wherein the conductive film is an amorphous semiconductor film doped with an impurity. 7. The method according to claim 6, wherein hemispherical grains are formed on the surface of the amorphous semiconductor film. 8. The method of manufacturing a semiconductor device according to claim 6, wherein said second insulating film is formed at a temperature not higher than a temperature at which said conductive film is formed. 9. The semiconductor device according to claim 6, wherein said amorphous semiconductor film is an amorphous silicon film, and said second insulating film is formed at a temperature of 430 ° C. or more and 530 ° C. or less.
The manufacturing method of the semiconductor device described in the above. 10. A step of forming a first pattern having conductivity on a semiconductor substrate; a step of forming a first insulating film on the semiconductor substrate so as to cover the first pattern; Forming a sidewall having conductivity on the side wall surface of the first pattern via the first insulating film; and having conductivity on at least the sidewall so as to be connected to the sidewall. Forming a second pattern. 11. The semiconductor device according to claim 1, wherein the semiconductor device is a dynamic RAM.
11. The semiconductor device according to claim 10, wherein a bit line of said dynamic RAM is constituted by said second pattern and said sidewall connected to said second pattern. Manufacturing method. 12. The semiconductor device according to claim 1, wherein the semiconductor device is a dynamic RAM.
Wherein the first pattern is the dynamic RAM
11. The word line according to claim 10, wherein
The manufacturing method of the semiconductor device described in the above. 13. A resist pattern is formed on the first insulating film and the sidewall after the step of forming the sidewall and before the step of forming the second pattern. 11. The method according to claim 10, further comprising a step of forming a connection hole in the first insulating film by etching at least the first insulating film using the sidewall as a mask.
The manufacturing method of the semiconductor device described in the above. 14. The method according to claim 10, wherein said sidewall is made of a polycrystalline semiconductor. 15. The method according to claim 10, wherein the sidewall is made of polycrystalline silicon. 16. The method according to claim 10, wherein said sidewall is made of polycrystalline silicon doped with an impurity. 17. The method according to claim 10, wherein said sidewall is made of an amorphous semiconductor. 18. The method according to claim 10, wherein said sidewall is made of amorphous silicon. 19. The method of manufacturing a semiconductor device according to claim 10, wherein said sidewall is made of amorphous silicon doped with an impurity.