JP2001024146A - Semiconductor device and mounting method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify wiring while extremely decreasing nonconformity due to wiring constitution when a plurality of semiconductor devices are mounted. SOLUTION: Electrodes 14a-14d to be connected in common are formed to a side section to a reference semiconductor chip 11 as an object. Common connecting electrodes 15a-15d are formed to a side section in a semiconductor chip 12 formed in mirror symmetric relationship to the semiconductor chip 11. The semiconductor chips are arranged and mounted so as to be oppositely faced onto a printed board 13, holding a center line S. Electrically balanced connection can be obtained by connecting the semiconductor chips in common with wiring patterns 16a-16d.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a common connection electrode electrically connected to two or more of the plurality of electrodes with respect to a reference semiconductor device having a plurality of electrodes. The present invention relates to a method for mounting a semiconductor device.

[0002]

In general, a semiconductor device has a structure provided with a plurality of electrodes.
In the case of a circuit configuration in which a plurality of the same semiconductor devices are mounted,
Due to the wiring, the following problem may occur. For example, bare chip mounting 2 shown in FIG.
A description will be given of the semiconductor chips 1 and 2. Each of the semiconductor chips 1 and 2 has four electrodes 1a to 1d and 2a to 2d, respectively.
Is formed.

The electrodes 1a to 1d, 2a to 2d
Are wiring patterns 3a to 3a on the mounting board 3 so as to be connected between them as 1a and 2a and 1b and 2b, respectively.
3d is formed. At this time, two semiconductor chips 1
2 has the same arrangement state of the electrodes 1a to 1d and 2a to 2d. Therefore, when the electrodes 1a to 1d and 2a to 2d are arranged side by side, wirings 3a to 3g between the electrodes need to be provided with a complicated pattern as shown in the figure. Come.

Accordingly, control signals and sense signals of the two semiconductor chips 1 and 2 are individually routed on the mounting board 3 and then connected to a common line. When the density is increased or the module is incorporated as a module, the size of the module becomes larger. This leads to an increase in cost.

In a product having a high driving frequency of the semiconductor chips 1 and 2, the circuit elements of the semiconductor chips 1 and 2 operating in parallel should be arranged with equal impedance when viewed from equal length wiring or power supply lines. However, in such a conventional device, the wirings 3a to 3g of the mounting substrate 3 are complicated, so that a difference occurs in the signal delay time between the semiconductor chips 1 and 2 or a malfunction occurs. In some cases, this may cause a problem in operation.

[0008] This also causes a similar problem when semiconductor chips 1 and 2 are used side by side, as shown in FIG. 8. That is, in a configuration in which the semiconductor chips 1 and 2 are arranged in parallel on the mounting substrate 4 and connected by the wirings 4a to 4g, the electrodes 1a and 2a are commonly connected by the wiring 4a and the other electrodes 1b to 1d, In this case, 2b to 2d are connected by wirings 4b to 4g, respectively. Also in this case, since the wirings 4a to 4g between the semiconductor chips 1 and 2 may not have the same condition when viewed from the wiring side, a difference in delay time may occur or a malfunction may be caused.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to simplify the wiring configuration and minimize the problems caused by the wiring configuration when mounting a plurality of semiconductor devices. It is an object of the present invention to provide a semiconductor device capable of performing the above.

[0008]

According to the first aspect of the present invention, two of the plurality of electrodes provided on the reference semiconductor device are provided.
A structure in which a common connection electrode electrically connected to these electrodes is provided for at least two or more electrodes, and these common connection electrodes are formed in a mirror image symmetrical arrangement with the corresponding one of the reference semiconductor device. Therefore, in the case of mounting with a reference semiconductor device, if mounting is performed so as to be arranged at a symmetrical position using the mirror image symmetry, wiring connected between them is connected through an intermediate portion. In addition, the wiring can be performed under the same conditions, so that the wiring can be provided in a simple state and the wiring can be performed with the electrical characteristics being the same.

Similarly, according to the second aspect of the present invention, since the common connection electrode is provided on the semiconductor chip mounted on the bare chip, the wiring between the chip and the semiconductor chip of the reference semiconductor device must be close to each other. Wiring to both can be performed so as to be electrically equivalent while arranging, so that mounting density can be increased, and a difference in the degree of signal delay due to wiring can be prevented as much as possible to achieve a well-balanced operation. Can be performed.

According to the third aspect of the present invention, since the common connection electrode is a lead terminal provided on the package, even when mounted on a printed circuit board or the like, the common connection electrode can be shared with the reference semiconductor device in the same manner as described above. Wiring to the connection electrodes can be efficiently performed, and a configuration having well-balanced electrical characteristics can be achieved.

According to the fifth aspect of the present invention, the semiconductor chip is arranged and formed such that the semiconductor element circuit to be formed therein has a mirror image relationship with the corresponding semiconductor element circuit portion of the reference semiconductor device. Since the semiconductor device circuit configuration is geometrically symmetrical with the device, when wiring is made to the common connection electrode, the internal semiconductor device circuit configuration can be set to the same condition, so that a well-balanced electrical operation is achieved. And wiring of the lead terminals can be easily performed in a mirror image symmetry even in a surface mount package or the like.

According to the invention of claim 6, the semiconductor device is
It is mounted side by side on the same mounting surface as the mounting surface of the reference semiconductor device, and at this time, the common connection electrode is mounted so that it is in a mirror image position with the corresponding electrode of the reference semiconductor device. With such wiring, electrically equivalent wiring can be provided for both the semiconductor device and the reference semiconductor device. At this time, since the semiconductor device and the reference semiconductor device are arranged on the same plane, the relationship in which the semiconductor device is opposed to the reference semiconductor device can also be provided in the direction orthogonal to the reference semiconductor device. It becomes possible to adopt a configuration in which wiring is performed.

According to the seventh aspect of the present invention, the reference semiconductor device and the semiconductor device are arranged on the front and back surfaces of the double-sided mounting substrate such that the common connection electrode is in a mirror-image position with the corresponding electrode of the reference semiconductor device. Since they are mounted in a state, they can be wired in a completely symmetrical state with the mounting substrate interposed therebetween, whereby the electrical wiring conditions can be balanced and the length of the wiring can be reduced to one semiconductor device. It can be performed in exactly the same state as the one. Also, in this case, the semiconductor device and the reference semiconductor device are arranged on the front and back of the double-sided mounting board, so that by adopting the mounting configuration combined with the above-described invention of claim 6, up to eight wirings are equally provided. Configuration.

[0014]

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a case where two semiconductor chips, a reference semiconductor chip 11 as a reference semiconductor device and a semiconductor chip 12 as a semiconductor device of the present invention, are opposed to each other on a mounting substrate 13.

The reference semiconductor chip 11 and the semiconductor chip 12 have semiconductor elements corresponding to, for example, a plurality of IGBTs incorporated as IGBT modules, a plurality of DRAMs incorporated as DRAM modules, or a plurality of MPUs incorporated as multi-MPU modules. , Which is a target for performing a parallel operation. In this embodiment, the reference semiconductor chip 11 and the semiconductor chip 12 are formed such that the arrangement state of the circuit pattern formed inside and the pattern of the electrode portion for connection to the outside is mirror-image symmetric. Have been. Therefore, they have exactly the same function electrically, and only the electrode pads electrically connected externally are arranged so as to be mirror-symmetric.

On a printed board 13 as a mounting board, a predetermined wiring pattern is formed, and the reference semiconductor chip 11 and the semiconductor chip 12 are connected to the respective side portions 11a,
12a are mounted so as to face each other with a dashed line indicated by S in the figure (hereinafter referred to as a center line S). Reference semiconductor chip 11 and semiconductor chip 12
Have, for example, four common connection electrodes 14a to 14a on the surface corresponding to the sides 11a and 12a facing each other.
d and 15a to 15d are arranged and formed so as to correspond one-to-one.

In this case, as described above, each of the common connection electrodes 14a to 14d of the reference semiconductor chip 11 is formed so as to face a position symmetrical to the common connection electrodes 15a to 15d of the semiconductor chip 12. These are connected in common between the opposing portions by wiring patterns 16a to 16d formed in advance on the printed circuit board 13, and then pulled out to a predetermined portion to be electrically connected to other portions. ing.

According to this configuration, the reference semiconductor chip 11
And the semiconductor chip 12 are connected to the common connection electrodes 14a to 14d.
And 15a to 15d are arranged so as to be mirror-symmetrical, and wiring is performed completely symmetrically by the wiring patterns 16a to 16d. Therefore, an equi-impedance arrangement can be obtained. The operation characteristics of the parallel operation can be performed in a stable state without causing a problem due to a difference in delay time or a difference in impedance.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
This embodiment is different from the first embodiment in that the sides 11a and 12a of the reference semiconductor chip 11 and the semiconductor chip 12 are arranged on a printed circuit board 17 so as to be located on a straight line. It has just been arranged and implemented. In this case, the side portions 11a,
Although 12a is not at the facing position, the common connection electrodes 14a to 14d and the common connection electrodes 15a to 15d are arranged symmetrically with respect to the center line S.

On the printed board 17, for example, wiring patterns 18a to 18g are formed. Wiring pattern 1
8d is formed so as to be led out in a state where the common connection electrodes 14d and 15d are connected in common, and the other common connection electrodes 14a to 14c and 15a to 15c are connected to the respective wiring patterns 18a to 18c and 18e to 18g. It is connected to the.

According to such a configuration, the common connection electrodes 14d of the reference semiconductor chip 11 and the semiconductor chip 12
Since 15d is connected in exactly the same symmetrical manner by the wiring pattern 18d, the wiring pattern can be made simple and short without multi-layering, and an equi-impedance arrangement can be obtained electrically. A stable operation can be performed.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
This is an embodiment in which the structures of the first and second embodiments are combined and electrodes provided on each of three sides 19a, 19b, and 19c of the reference semiconductor chip 19 are shown. In contrast, the electrodes of the three sides 20a, 20b, and 20c of the semiconductor chip 20 are arranged so as to be mirror-image-symmetric.

That is, in the reference semiconductor chip 19, each of the side portions 19a, 19b, 19c has a common connection electrode 2
1a to 21m are formed on the semiconductor chip 20, and the common connection electrodes 22a to 22m are formed on the sides 20a, 20b, and 20c of the semiconductor chip 20 at mirror image positions with respect to the center line S.
Are formed. The sides 19b and 20b have the relationship of the first embodiment, and the sides 19a and 19c and the sides 20a and 20c have the relationship of the second embodiment.
Similarly, connection can be made in a mirror-image relationship.

According to such a configuration, it is possible to provide a configuration in which a plurality of common connection electrodes extending over three sides are connected in a mirror image arrangement so as to increase the degree of freedom in design. Even in the case where the reference semiconductor chip 19 provided with an integrated circuit having a complicated configuration is used, the use of the semiconductor chip 20 makes it possible to bring out excellent electrical characteristics in the same manner as described above.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
This embodiment is different from the first embodiment in that two reference semiconductor chips 23 are used, and two semiconductor chips 24 are provided in correspondence with the two. , 24 are arranged in two rows.

The reference semiconductor chip 23 includes common connection electrodes 25a to 25a formed on two orthogonal sides 23a and 23b.
5i are formed. Correspondingly, the semiconductor chip 24 has common connection electrodes 26a to 26i formed at mirror-symmetric positions on two orthogonal sides 24a and 24b.

The reference semiconductor chip 23 and the semiconductor chip 24 are arranged so as to face each other with respect to two orthogonal center lines S1 and S2. At this time, the common connection electrodes are arranged so that the sides where the common connection electrodes are arranged face the center lines S1 and S2. Therefore, even with such a configuration, the same operation and effect as described above can be obtained even when four semiconductor chips 23 and 24 are used.

(Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.
This embodiment is different from the first embodiment in that a reference semiconductor chip 27 in which solder bumps are formed as common connection electrodes so that a bare chip is mounted face down is used. Then, a semiconductor chip 28 in which common connection electrodes are formed by solder bumps so as to be mirror-symmetrical to the entire surface on which the solder bumps are formed is mounted on both sides of a printed board 29.

That is, FIG. 5 shows a cross section in a mounted state. For example, all of the electrodes 30a to 30g formed on the reference semiconductor chip 27 can be used as common connection electrodes. 28 electrodes 3
1a to 31g are formed at mirror image symmetric positions.

The printed board 29 is, for example, a multilayer printed board formed by laminating four insulating plates 29a to 29d. The reference semiconductor chip 27 and the semiconductor chip are formed by wiring patterns provided on the front and back surfaces and between the insulating plates 29a to 29d. 28 electrodes.

According to such a configuration, since the reference semiconductor chip 27 and the semiconductor chip 28 are mounted so as to face each other completely, the semiconductor chip 28 can be used in a state where the matching of the electrical characteristics is further enhanced. Become like Except for mounting on both surfaces, the wiring pattern can be formed to the same extent as when one reference semiconductor chip 27 is mounted, so that the wiring efficiency is high.

(Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
In this embodiment, the electrodes of the reference semiconductor chip 27 and the semiconductor chip 28 in the sixth embodiment are changed so that the opposing side portions become the common connection electrodes as in the fourth embodiment. The printed circuit board 29 has eight components mounted on the front and back sides. By adopting such a configuration, a maximum of eight components can be used in a good mounting state that is electrically balanced, and the mounting efficiency is improved and the electrical characteristics are also in a good efficiency state. Will be able to do it.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. The case where the semiconductor chip of the present invention corresponding to the reference semiconductor chip is exactly the same and has a mirror-image symmetry has been described, but a portion corresponding to a part of the circuit portion of the reference semiconductor chip is mirror-image-symmetric. The present invention can be applied to a case where semiconductor chips arranged and formed are used.

Therefore, it is not always necessary to make the same size as the reference semiconductor chip, and the present invention can be applied to all semiconductor chips formed such that the common connection electrode portion is mirror-image symmetric.

The present invention is not limited to the case of mounting on a bare chip, but can be applied to a semiconductor element mounted on a package. In this case, the pins provided on the package are provided at positions where the pins are mirror-image-symmetric.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

FIG. 3 is a view corresponding to FIG. 1, showing a third embodiment of the present invention;

FIG. 4 is a view corresponding to FIG. 1, showing a fourth embodiment of the present invention;

FIG. 5 is a longitudinal sectional side view showing a fifth embodiment of the present invention.

FIG. 6 is an external perspective view showing a cross section of a part showing a sixth embodiment of the present invention.

FIG. 7 is a diagram corresponding to FIG. 1 showing a conventional example.

FIG. 8 is a diagram corresponding to FIG. 2, showing a different conventional example.

[Explanation of symbols]

11, 19, 23 and 27 are reference semiconductor chips (reference semiconductor devices), 12, 20, 24 and 28 are semiconductor chips (semiconductor devices), 13, 17, and 29 are printed circuit boards, 14a
~ 14d, 15a ~ 15d, 21a ~ 21m, 22a ~
22m, 25a-25i, 26a-26i, 30a-3
0g, 31a-31g are common connection electrodes, 16a-16
d, 18a to 18g are wiring patterns.

Claims (7)

[Claims] 1. A semiconductor device having a common connection electrode electrically connected to two or more of the plurality of electrodes with respect to a reference semiconductor device having a plurality of electrodes, wherein each of the common connection electrodes is A plurality of electrodes of the reference semiconductor device, which are arranged to be opposed to the reference semiconductor device, are formed in a state of being mirror-image-symmetric with respect to an electrode electrically connected to the electrodes, with the facing surface interposed therebetween. A semiconductor device characterized in that: 2. The semiconductor device according to claim 1, comprising a semiconductor chip mounted on a bare chip, wherein said common connection electrode is an electrode for external connection formed on a surface of said semiconductor chip. Semiconductor device. 3. The semiconductor device according to claim 1, wherein a semiconductor chip is sealed in a surface mounting package, wherein the common connection electrode is a lead terminal provided on the package. Semiconductor device. 4. The semiconductor device according to claim 3, wherein the package is a CSP (Chip Scale Package) type or a BGA (Ball Grid Array) type package. 5. The semiconductor device according to claim 2, wherein the semiconductor chip has a semiconductor element circuit formed inside the semiconductor chip mirror-symmetric with a corresponding semiconductor element circuit portion of the reference semiconductor device. A semiconductor device, wherein the semiconductor device is arranged and formed. 6. The method of mounting the semiconductor device according to claim 1 together with the reference semiconductor device, wherein the semiconductor device is arranged side by side on the same mounting surface as the mounting surface of the reference semiconductor device, and the common connection is provided. A method of mounting a semiconductor device, wherein the mounting is performed so that the electrodes are arranged so as to be mirror-symmetrical to the corresponding electrodes of the reference semiconductor device. 7. A method for mounting the semiconductor device according to claim 1 together with the reference semiconductor device, wherein the reference semiconductor device and the semiconductor device are arranged on both sides of a double-sided mounting substrate and the common connection is provided. A method for mounting a semiconductor device, wherein the electrodes are mounted in a state where the electrodes are arranged so as to be mirror-symmetrical to the corresponding electrodes of the reference semiconductor device.