JP2001015684A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time required for evaluation by conducting a simple function test for evaluating a cross-point voltage of a differential output of a differential output circuit. SOLUTION: A differential output circuit 10 which outputs a forward output of the same phase with an input pulse and an inversion signal of an inverse phase; a first detection circuit 11 which outputs a first detection pulse DPX corresponding to a time band which crosses first reference voltage Vref1/second reference voltage Vref2, when the logical level of the forward output of the differential output circuit 10 changes; a second detection circuit 12 which outputs a second detection pulse DPX corresponding to the time band which crosses second reference voltage/first reference voltage, when the logical level of the inverse output of the differential output circuit 10 changes; and a circuit 14 which outputs a judgement signal wherein, with two detection pulses inputted, the logical level changes if both agree each other for time while the logical level does not change if both do not agree each other for time; are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to a differential output (normal / inverted output) of a differential output circuit.
The present invention relates to a circuit for measuring an intersection voltage of a waveform.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a differential output (normal / inverted output) waveform of a differential output circuit built in a semiconductor integrated circuit.

When the voltage at the intersection of the output waveform is specified by specifications or the like, it is necessary to measure the intersection voltage, but it is impossible or impossible to measure with a conventional digital tester. In addition, the output waveform must be sampled, and the time required for the measurement becomes longer.

[0004]

As described above, the conventional semiconductor integrated circuit has a problem that it is impossible to measure the crossing point voltage of the differential output of the differential output circuit or the time required for the measurement is long. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention is provided with a test circuit for evaluating a cross-point voltage of a differential output of a differential output circuit and performing a simple function test to obtain a cross-over point. It is possible to evaluate the voltage,
An object of the present invention is to provide a semiconductor integrated circuit that can significantly reduce the time required for evaluation.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a differential output circuit for outputting a non-inverted signal having the same phase as an input pulse signal and an inverted signal having a negative phase; Output a first detection pulse signal having a pulse width corresponding to a time width crossing the different first reference voltage and the different second reference voltage when the logic level changes.
And a second circuit having a pulse width corresponding to a time width crossing the second reference voltage and the first reference voltage when the logic level of the inverted output of the differential output circuit changes.
A second detection circuit that outputs the detection pulse signal of the first detection circuit, a first detection pulse signal output from the first detection circuit, and a second detection pulse signal output from the second detection circuit. When a temporal match occurs, a determination circuit for outputting a determination signal whose logic level changes in accordance with a change in the logic level of the input pulse signal is provided.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a differential output circuit mounted on a semiconductor integrated circuit according to a first embodiment of the present invention and a test circuit for evaluating an intersection voltage of the differential output.

In FIG. 1, reference numeral 10 denotes a differential output circuit;
It comprises a first buffer circuit BF1 and a second buffer circuit BF2 to which the input pulse signal IN is commonly input. The first
The buffer circuit BF1 outputs a non-inverted signal having a waveform in phase with the input pulse signal IN to the first output node DP, and the second buffer circuit BF2 has a waveform opposite in phase to the input pulse signal IN An inverter circuit for outputting an inverted signal to the second output node DM.

Reference numeral 11 denotes a first detection circuit, which includes an output signal of the first buffer circuit BF1 and two different reference voltages (a first reference voltage Vref1 and a second reference voltage Vref).
2) to which two voltage comparison circuits (first voltage comparison circuit 111 and second voltage comparison circuit 112) are input, and one voltage matching circuit to which the output of each of the voltage comparison circuits 111 and 112 is input. A mismatch detection circuit (for example, an exclusive OR circuit 113);
When the output signal of the first buffer circuit BF1 is inverted, a first detection pulse signal DPX having a pulse width corresponding to a time width crossing the two reference voltages Vref1 and Vref2 is output.

The output signal Z of the first buffer circuit BF1 is input to the (+) input terminal of the first voltage comparison circuit 111 and the (+) input terminal of the second voltage comparison circuit 112, respectively. The (−) input terminal of the first voltage comparison circuit 111 and the (−) input terminal of the second voltage comparison circuit 112 correspond to the selected output voltage of the first multiplexer 131 of the reference voltage selection circuit 13 described later. Y and the selected output voltage X of the second multiplexer 132 are input.

Reference numeral 12 denotes a second detection circuit, which includes an output signal of the second buffer circuit BF2 and the two reference voltages Vr.
Two voltage comparison circuits (third voltage comparison circuit 121 and fourth voltage comparison circuit 122) to which ef1 and Vref2 are input, and one second input to which the output of each of the voltage comparison circuits 121 and 122 is input. A mismatch detection circuit (exclusive OR circuit) 123;
And outputs a second detection pulse signal DMX having a pulse width corresponding to a time width crossing each of the two reference voltages Vref1 and Vref2 when the output signal of the buffer circuit BF2 is inverted.

Here, the output signal of the second buffer circuit BF2 is input to the (+) input terminal of the third voltage comparison circuit 121 and the (+) input terminal of the fourth voltage comparison circuit 122, respectively. The (−) input terminal of the third voltage comparison circuit 121 and the (−) input terminal of the fourth voltage comparison circuit 122 correspond to the selected output voltage Y of the first multiplexer 131 of the reference voltage selection circuit 13 and The selected output voltage X of the second multiplexer 132 is input.

Reference numeral 13 denotes a reference voltage selection circuit which is controlled by the input pulse signal IN and has two reference voltages Vref1 and Vref1.
It has two multiplexers (first multiplexer 131 and second multiplexer 132) for selecting different ones of Vref2, and has two multiplexers 131 and 132.
The two reference voltages Vref1 and Vref2 selected separately are supplied to the two voltage comparison circuits 111 and 112 of the first detection circuit 11 and the two voltage comparison circuits 121 and 122 of the second detection circuit 12, respectively. Things.

In this case, the first multiplexer 131
The first reference voltage Vref1 / the second reference voltage Vref2 is selected according to the logic level “H” / “L” of the input pulse signal IN and output Y, and the second multiplexer 132 outputs the input pulse signal IN The second according to the logic level “H” / “L”
The reference voltage Vref2 / first reference voltage Vref1 is selected as an output X.

That is, the two multiplexers 131 and 132
The reference voltages selected from the two reference voltages Vref1 and Vref2 are reversed according to the logic level of the input pulse signal IN. As a result, the two voltage comparison circuits in the first detection circuit 11
111, 112 and two reference voltages Vref1, Vre supplied thereto
The relationship between the two voltage comparison circuits 121 and 122 in the second detection circuit 12 and the supply
The correspondence between the two reference voltages Vref1 and Vref2 is reversed.

Reference numeral 14 denotes an intersection voltage determination circuit,
The first detection pulse signal DPX output from the detection circuit 11 and the second detection pulse signal DMX output from the second detection circuit 12 are input, and have a pulse width corresponding to a period in which both temporally match. It outputs a determination pulse signal.

In this case, the first detection pulse signal DPX and the second detection pulse signal DMX are input to a two-input AND circuit 141, and the output signal of the AND circuit 141 is supplied to a D-type flip-flop (FF) circuit 142. The input pulse signal IN is input to the clock input terminal CK, the input pulse signal IN is input to the data input terminal D of the FF circuit 142, and the output signal of the output terminal Q of the FF circuit 142 is output to the determination output terminal CRS via the buffer circuit 143. Output.

FIG. 2 is a timing chart showing an operation example of the circuit of FIG.

Next, assuming that the voltage range at the intersection of the waveforms of the non-inverted output and the inverted output of the circuit of FIG. 1 is defined as 1.3 V to 2.0 V, an operation example of measuring the intersection voltage is shown in FIG. This will be described with reference to FIG.

The lower limit 1.3 V of the intersection voltage range is given as the first reference voltage Vref1, and the upper limit 2.0V of the intersection voltage range is given as the second reference voltage Vref2. When the input pulse signal IN is at “H” level, the first multiplexer 13
1 selects the first reference voltage Vref1 (= 1.3V), and the second multiplexer 132 selects the second reference voltage Vref2 (= 1.3V).
2.0V).

As a result, in the first detection circuit 11,
The first reference voltage Vref1 (= 1.3 V) is applied to the (−) input terminal of the first voltage comparison circuit 111, and the second reference voltage Vref2 is applied to the (−) input terminal of the second voltage comparison circuit 112. (= 2.
0V) is applied. Further, in the second detection circuit 12, the first reference voltage Vref1 (= 1.3 V) is applied to the (−) input terminal of the third voltage comparison circuit 121, and the (−) of the fourth voltage comparison circuit 122 is ) Input terminal to the second reference voltage Vref2 (=
2.0 V) is applied.

When the input pulse signal IN changes from "H" level to "L" level, the first buffer circuit BF
The 1 output signal Z (the signal of the first output node DP) changes from “H” level to “L” level in response to the level change of the input pulse signal IN.

At this time, when the input pulse signal IN becomes 2.0 V or less, the output S2 of the second voltage comparison circuit 112 changes from "L" level to "H" level. Further, when the input pulse signal IN becomes 1.3 V or less, the output S1 of the first voltage comparison circuit 111 changes from "L" level to "H" level.

Thus, in the first detection circuit 11,
The first mismatch detection circuit 113 has a first pulse width corresponding to a period in which the logic levels of S2 and S1 do not match (the time width crossing the two reference voltages Vref2 and Vref1).
Output the detection pulse signal DPX.

On the other hand, as described above, the input pulse signal IN
Changes from the “H” level to the “L” level, the output signal of the second buffer circuit BF2 (the signal at the second output node DM) changes to “L” in response to the level change of the input pulse signal IN. The level changes from “H” level to “H” level.

At this time, when the input pulse signal IN exceeds 1.3 V, the output S1 'of the third voltage comparison circuit 121 changes from "L" level to "H" level. Further, when the input pulse signal IN exceeds 2.0 V, the output S2 'of the fourth voltage comparison circuit 122 changes from "L" level to "H" level.

Thus, in the second detection circuit 12,
The second mismatch detection circuit 123 generates a second detection pulse signal DMX having a pulse width corresponding to a period (the time width crossing the two reference voltages Vref1 and Vref2) in which the logic levels of S1 'and S2' do not match. Output.

Thus, the two-input AND circuit 141 in the intersection voltage determination circuit 14 has a pulse width corresponding to a period in which the first detection pulse signal DPX and the second detection pulse signal DMX coincide with each other in time. Outputs the judgment pulse signal CS. The D-type FF circuit 142 to which the determination pulse signal CS is input to the clock input terminal CK receives the input pulse signal IN at the data input terminal D. The level (in this example, the input pulse signal IN is at the “L” level) is taken in, and the output signal at the output terminal Q becomes “L”. This D type F
The output signal “L” of the output terminal Q of the F circuit 142 is
Output to the judgment output terminal CRS via 43.

As described above, the input pulse signal IN
Is changed from “H” level to “L” level.
Multiplexer 131 has a second reference voltage Vref2 (= 2.
0V), and the second multiplexer 132 selects the first reference voltage Vref1 (= 1.3V). This allows
In the first detection circuit 11, the second reference voltage Vref2 (= 2.0 V) is applied to the (-) input terminal of the first voltage comparison circuit 111, and the (-) input of the second voltage comparison circuit 112 is applied. A first reference voltage Vref1 (= 1.3 V) is applied to the end. In the second detection circuit 12, the third voltage comparison circuit 12
The second reference voltage Vref2 (= 2.0
V) is applied, and a first reference voltage Vref1 (= 1.3 V) is applied to the (−) input terminal of the fourth voltage comparison circuit 122.

Contrary to the above operation, the input pulse signal I
When N changes from “L” level to “H” level, the first
Output signal Z of the buffer circuit BF1 (first output node DP
Changes from “L” level to “H” level in response to the level change of the input pulse signal IN.

At this time, when the input pulse signal IN exceeds 1.3 V, the output S2 of the second voltage comparison circuit 112 becomes "L".
The level changes from “H” level to “H” level. Further, when the input pulse signal IN exceeds 2.0 V, the output S1 of the first voltage comparison circuit 111 changes from "L" level to "H" level.

As a result, in the first detection circuit 11,
The first mismatch detection circuit 113 has a first pulse width corresponding to a period in which the logic levels of S2 and S1 do not match (a time width crossing the two reference voltages Vref1 and Vref2, respectively).
Output the detection pulse signal DPX.

On the other hand, as described above, the input pulse signal IN
Changes from the “L” level to the “H” level, the output signal of the second buffer circuit BF2 (the signal at the second output node DM) changes to “H” in response to the level change of the input pulse signal IN. The level changes from “L” level to “L” level. At this time, when the input pulse signal IN becomes 2.0 V or less, the output S2 'of the fourth voltage comparison circuit 122 changes from "L" level to "H" level. Further, when the input pulse signal IN is 1.3
When the voltage becomes equal to or less than V, the output S1 ′ of the third voltage comparison circuit 121
Changes from the “L” level to the “H” level.

Thus, in the second detection circuit 12,
The second mismatch detection circuit 123 generates a second detection pulse signal DMX having a pulse width corresponding to a period in which the logic levels of S2 'and S1' do not match (the time widths crossing the two reference voltages Vref2 and Vref1). Is output.

Thus, the two-input AND circuit 141 in the intersection voltage determination circuit 14 has a pulse width corresponding to a period in which the first detection pulse signal DPX and the second detection pulse signal DMX coincide with each other in time. Outputs the judgment pulse signal CS. The D-type FF circuit 142 to which the determination pulse signal CS is input to the clock input terminal CK receives the input pulse signal IN at the data input terminal D, and the logic of the input pulse signal IN at the trailing edge of the determination pulse signal CS. The level (in this example, the input pulse signal IN is at “H” level) is fetched, and the output signal at the output terminal Q becomes “H”. This D type F
The output signal “H” of the output terminal Q of the F circuit 142 is
Output to the judgment output terminal CRS via 43.

As described above, the input pulse signal IN
Is changed from the “L” level to the “H” level.
Of the first reference voltage Vref1 (= 1.
3V), and the second multiplexer 132 selects the second reference voltage Vref2 (= 2.0 V). This allows
In the first detection circuit 11, the first reference voltage Vref1 (= 1.3 V) is applied to the (-) input terminal of the first voltage comparison circuit 111, and the (-) input of the second voltage comparison circuit 112 is applied. A second reference voltage Vref2 (= 2.0 V) is applied to the end. In the second detection circuit 12, the third voltage comparison circuit 12
The first reference voltage Vref1 (= 1.3)
V), and the second reference voltage Vref2 (= 2.0 V) is applied to the (−) input terminal of the fourth voltage comparison circuit 122.

Therefore, the intersection of the waveforms of the normal output and the inverted output of the circuit shown in FIG. 1 corresponds to the specified voltage range (1.3 V to 1.3 V).
2.0 V), the determination pulse signal CS goes to the “H” level, the D-type FF circuit 142 captures the data at the data input terminal D (input pulse signal IN), and the determination output terminal CRS
Outputs data corresponding to the level change of the input pulse signal IN.

On the other hand, the intersection of the normal output and inverted output waveforms of the circuit of FIG.
2.0 V), the determination pulse signal CS remains at the “L” level, the D-type FF circuit 142 stops taking in the data at the data input terminal D (input pulse signal IN), and the determination output terminal CRS Does not output data corresponding to the level change of the input pulse signal IN, and keeps the previous data.

That is, according to the semiconductor integrated circuit of the above embodiment, the test circuit shown in FIG. 1 is easily incorporated into an existing differential output circuit, so that the differential output circuit specified by the specifications and the like can be used. Two reference voltages Vref1 and Vre corresponding to the upper and lower limits of the intersection voltage range of the output waveform of the differential output
Whether the specification is satisfied by monitoring the output waveform of the judgment output terminal CRS by a simple function test in which the logic level of the input pulse signal IN is changed while f2 is supplied from the outside (or generated internally) It is possible to determine whether or not.

If the regulation is not satisfied, the intersection voltage range is newly defined, the two reference voltages Vref1a and Vref2a corresponding thereto are set and the function test is performed again. This makes it possible to measure the voltage range at the intersection of the output waveforms of the differential output of the differential output circuit.

With such a simple function test, the evaluation time can be greatly reduced as compared with the conventional method of sampling the output waveform.

[0043]

As described above, according to the semiconductor integrated circuit of the present invention, a test circuit for evaluating the cross-point voltage of the differential output of the differential output circuit is mounted, and a simple function test is performed to obtain the cross-point. It is possible to evaluate the voltage,
The time required for evaluation can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a differential output circuit mounted on a semiconductor integrated circuit according to a first embodiment of the present invention and a test circuit for evaluating an intersection voltage of the differential output.

FIG. 2 is a timing chart illustrating an operation example of the circuit in FIG. 1;

FIG. 3 is a diagram showing an example of a differential output (normal / inverted output) waveform of a differential output circuit built in a semiconductor integrated circuit.

[Explanation of symbols]

10: differential output circuit, BF1: first buffer circuit, BF2: second buffer circuit, Z: output signal of first buffer circuit BF1, DP: first output node, DM: second output node 11, a first detection circuit, 111, a first voltage comparison circuit, 112, a second voltage comparison circuit, 113, a first match / mismatch detection circuit (for example, an exclusive OR circuit), DPX, a first Detection pulse signal, 12: second detection circuit, 121: third voltage comparison circuit, 122: fourth voltage comparison circuit, 123: second mismatch detection circuit (exclusive OR circuit), DMX: second Detection pulse signal, 13 ... reference voltage selection circuit, Vref1 ... first reference voltage, Vref2 ... second reference voltage, 131 ... first multiplexer, Y ... selection output voltage of first multiplexer, 132 ... second A multiplexer, X: a selected output voltage of the second multiplexer, 14: an intersection voltage determination circuit, 141: Two-input AND circuit, 142: D-type FF circuit, 143: Buffer circuit, CRS: Judgment output terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Atsushi Sakurada 1-Family Toshiba Microelectronics Center, Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture F-term (reference) 5F038 DF01 DT08

Claims (3)

[Claims] 1. A differential output circuit for outputting a non-inverted output having the same phase as an input pulse signal and an inverted signal having a negative phase, and a first output circuit which is different when a logical level of the non-inverted output of the differential output circuit changes. A first detection circuit that outputs a first detection pulse signal having a pulse width corresponding to a time width crossing the reference voltage and the second reference voltage, and a logic level of an inverted output of the differential output circuit changes A second detection circuit that outputs a second detection pulse signal having a pulse width corresponding to a time width that crosses the second reference voltage and the first reference voltage, and outputs the second detection pulse signal from the first detection circuit. The first detection pulse signal and the second detection pulse signal output from the second detection circuit are input, and when both coincide with each other in time, the logic level changes according to the change in the logic level of the input pulse signal. Changing decisions A semiconductor integrated circuit, comprising: a determination circuit that outputs a signal. 2. The first detection circuit includes: a first voltage comparison circuit to which a non-inverting output of the differential output circuit and a first reference voltage are input; a first non-inverting output of the differential output circuit; A second voltage comparison circuit to which a second reference voltage is input, and respective outputs of the first voltage comparison circuit and the second voltage comparison circuit are input, and the first voltage comparison circuit is input based on both inputs.
And a first coincidence / mismatch detection circuit for generating a detection pulse signal, wherein the second detection circuit compares an inverted output of the differential output circuit and a first reference voltage with each other. Circuit and
A fourth voltage comparison circuit to which the inverted output of the differential output circuit and the second reference voltage are input, and respective outputs of the third voltage comparison circuit and the fourth voltage comparison circuit are input. 2. The semiconductor integrated circuit according to claim 1, further comprising a second coincidence / mismatch detection circuit that generates the second detection pulse signal based on the signal. 3. A first reference voltage / second reference voltage is selected according to a logic level of the input pulse signal, and the selected reference voltage is supplied to the first voltage comparison circuit and the third voltage comparison circuit. A first multiplexer that supplies a common signal to the first and a second multiplexer that supplies the first multiplexer according to a logic level of the input pulse signal.
The second reference voltage / first reference voltage is complementarily selected by the multiplexer, and the selected reference voltage is commonly supplied to the second voltage comparison circuit and the fourth voltage comparison circuit. 3. The semiconductor integrated circuit according to claim 2, comprising two multiplexers.