JP2001015527A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of a monolithic microwave integrated circuit reduced in chip size. SOLUTION: A gate electrode 32, a source electrode 33 and a drain electrode 34 are arranged on a semi-insulating substrate 31 to form a transistor cell 35. A multiplicity of such cells 35 are arranged and commonly connected by common source electrodes 36, 37, common drain electrodes 38,39, and common gate electrodes 40, 41. The cell connected to the common gate and drain electrodes 40 and 38 is formed as a first transistor 6, while the cell connected to the common gate and drain electrodes 41 and 39 are formed as a second transistor 7. A channel region 52 having gate electrode 32 brought in a Schottky- contact therewith is not separated by the transistors 6 and 7 and formed as a common continuous region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used particularly for high frequency switching, and more particularly to a monolithic microwave integrated circuit containing a plurality of transistors for switching.

[0002]

2. Description of the Related Art In mobile communication devices such as cellular phones, G
In many cases, a microwave in the Hz band is used, and a switching element for switching these high-frequency signals is often used in a switching circuit of a filter circuit or the like (for example, Japanese Patent Application Laid-Open No. 9-181624). . Gallium arsenide (Ga)
In many cases, a field effect transistor (FET) using As) is used, and accordingly, a monolithic microwave integrated circuit (MMIC) in which the switch circuit itself is integrated.
Is being developed.

FIG. 4A is a sectional view of a GaAs field effect transistor. An N-type channel region 2 is formed by doping an N-type impurity on a surface portion of a non-doped GaAs substrate 1, a gate electrode 3 in Schottky contact with the GaAs surface is arranged, and GaAs is provided on both sides of the gate electrode 3.
a source / drain electrode 4 in ohmic contact with the s surface,
5 are arranged. In this transistor, a depletion layer is formed in the channel region 2 immediately below by the potential of the gate electrode 3, thereby controlling a channel current between the source electrode 4 and the drain electrode 5.

FIG. 4B shows an example of a switch circuit using a GaAs field effect transistor. The sources (or drains) of the first and second transistors 6, 7 are connected to a common input terminal IN, and the transistors 6, 7
Is connected to first and second control terminals Ctr1 and Ctr2 via resistors R1 and R2, and the drain (or source) of each transistor is connected to the first and second output terminals O
These are connected to UT1 and OUT2. First and second
The signals applied to the control terminals Ctr1 and Ctr2 are capture signals, and the transistor to which the H-level signal is applied is turned on, and the signal applied to the input terminal IN is transmitted to one of the output terminals. It has become. Resistance R
Reference numerals 1 and R2 are provided for the purpose of preventing a high-frequency signal from leaking through the gate electrode with respect to the DC potential of the control terminals Ctr1 and Ctr2, which are AC grounded.

FIG. 5 shows an example of a semiconductor device in which such a switch circuit is integrated. A transistor cell 8 is formed by providing two channel regions 2 on the surface of a semi-insulating substrate 11 and arranging a gate electrode 3, a source electrode 4 and a drain electrode 5 in parallel on the surface thereof. A large number of transistor cells 8 are arranged such that 5 and 5 are alternately arranged. Some transistor cells 8
Collectively form first and second transistors 6 and 7. Each source electrode 4 and drain electrode 5 are commonly connected to common source electrodes 9 and 10 and common drain electrodes 11 and 12. Similarly, the gate electrode 3 is a common gate electrode 13,
14. The common source electrodes 9 and 10 are connected to an electrode pad 15, the common drain electrodes 11 and 12 are connected to electrode pads 16 and 17, respectively, and the common gate electrode 13 is connected to a pad 18 via a resistor R1. Connected to pad 19 via resistance element R2.

[0006]

SUMMARY OF THE INVENTION The above GaAs FET
Has a drawback that the transistor cell 8 is arranged in a rectangular area, and the pad 19 and the resistor R1 are arranged in this area.

Further, since the channel regions 2 for the first and second transistors 6 and 7 are separately arranged, there is a disadvantage that the chip size is also increased.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has one conductivity type channel region formed on the surface of a semi-insulating substrate and a Schottky contact with the surface of the channel region. A gate electrode, a source / drain electrode in ohmic contact with the surface of the channel region next to the gate electrode, the gate electrode and the source / drain electrode.
Forming a transistor cell by extending the drain region,
A plurality of the transistor cells are juxtaposed and the transistor cells are connected in parallel to form first and second transistors, and the first and second transistor cells are juxtaposed in the common channel region. Is what you do.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing a semiconductor device of the present invention. A gate electrode 32, a source electrode 33, and a drain electrode 34 are arranged in parallel on the surface of a semi-insulating substrate 31 to form a transistor cell 35, and a large number of transistors are arranged so that the source electrode 33 and the drain electrode 34 are alternately arranged. Two transistor cells 35 are arranged.

Each source electrode 33 and drain electrode 34
Common source electrodes 36 and 37 and common drain electrodes 38 and 3
9 in common. Similarly, the gate electrode 32 is connected to the common gate electrodes 40 and 41. Common source electrode 3
6, 37 and the common drain electrodes 38, 39 are formed in a comb-like shape so as to face each other. Further, the common source electrodes 36 and 37 and the common drain electrodes 38 and 39
Has an extended portion on the surface of the substrate 31 and permits formation of an electrode pad described later. And the common source electrode 3
6, 37 are provided on the electrode pad 42, the common drain electrode 38,
39 is connected to the electrode pads 43 and 44, respectively. The common gate electrode 40 is connected to the resistance element R1, and the resistance element R1 is connected to the electrode pad 45. Similarly, common gate electrode 41 is connected to resistance element R2, and resistance element R2 is connected to electrode pad 46. In addition, the same electrode material as each common electrode is exposed below the electrode pads 42 to 46. This structure can be obtained by covering the upper part of each electrode on the substrate surface with an insulating film (not shown) and partially opening the insulating film to expose the lower electrode material.

The transistor cell 35 shown in FIG.
Transistor cell 35 involving common drain electrode 38
(The cell on the left half of the drawing) are assembled into a first transistor 6
And the transistor cell 35 (the cell in the right half of the drawing) involving the common drain electrode 39 is assembled to form the second transistor 7. Each of the resistance elements R1 and R2 has a resistance value of several KΩ, and is formed of a diffusion region in which impurities are selectively diffused on the surface of the substrate 31 with a constant line width. 4B, the electrode pad 42 is the input terminal IN, the electrode pad 43 is the output terminal OUT1, the electrode pad 44 is the output terminal OUT2, and the electrode pad 45. Is the first control terminal Ctr
1. The electrode pad 46 becomes the control terminal Ctr2. The electrode pad 42 is arranged near the center of the substrate 31 and at the end thereof so as to be commonly connected to the two transistors 6 and 7. The pads 43 to 46 are arranged at four corners of the substrate 31.

FIG. 2 is a plan view for explaining each region on the substrate 31. In order to simplify the drawing, the gate electrode 33 and other displays are omitted. The first region 50 of the substrate 31 is located below the electrode pad 42 arranged near the center of the substrate 31, and the electrode pads 43, 4 arranged at the corners of the substrate 31
5 and between the electrode pads 44 and 46
Is located. The second region 51 has a size reduced in length by the size of the electrode pads 43 and 44 with respect to the first region 50. That is, one end 50a of the first region 50
Is the other end 5 of the first region 50 adjacent to the electrode pad 42.
0b is adjacent to the end of the substrate 31. One end 51 a of the second region 51 is adjacent to the electrode pad 45 and the other end 51 b
Is adjacent to the electrode pad 43. And the other end 51
c is adjacent to the end of the substrate 31.

In the first region 50, the transistor cells 35 are arranged with a first length and a substantially equal length. In this case, the cell length refers to the length of a portion where a channel region for forming a channel exists below the gate electrode 33. The cell has a length of 500 to 800 μ. On the other hand, in the second region 51, the length of the cell has a second length shorter than the first length, and the length is 200 to 400 μ. First area 50 and second area
In the region between the region 51 and the cell 35, the cell 35
Is formed at an intermediate length. That is, the first area 5
The length is gradually reduced from 0 toward the second region 51. The number of cells 35 is arbitrary.

The resistance element R1 is arranged using a region between the second region 51 and the electrode pad 45 and a region between the electrode pads 42 and 45. Similarly, the resistance element R2 is arranged using a region between the second region 51 and the electrode pad 46 and a region between the electrode pads 42 and 46 (see FIGS. 1 and 2). In this case, the pattern of the diffusion region may meander.

FIG. 3 is a diagram showing a sectional structure of the transistor cell 35. As shown in FIG. Semi-insulating non-doped GaAs substrate 5
A region selectively doped with an N-type impurity is formed on the surface of the substrate 1, and is used as a channel region 52. The gate electrode 32 makes Schottky contact with the surface of the channel region 52, and
The drain electrodes 33 and 34 make ohmic contact with the surface of the channel region 52. The gate, source and drain electrodes 32, 33 and 34 located outside the channel region 52
Since no ET element is formed, the channel length of the transistor is equal to the length of the gate electrode 32 extending above the channel region 52. The channel region 51 forms a single, continuous, common region for all the transistor cells 35 (see FIG. 1 or 2). That is, the first and second
Transistors 6 and 7 have channel region 52 as a common region. One of the source electrodes 33a is formed at a substantially central portion of the channel region 52 as a common electrode for the first and second transistors 6, 7, and the group of transistor cells 35 has the source electrode 33a as a central axis. It consists of a symmetrical pattern.

FIG. 3 shows the arrangement of the electrodes most clearly. That is, the source electrode 33a is arranged at the center,
A gate electrode 32 is disposed next to the gate electrode 32, and a drain electrode 34 is disposed.
3, the source electrode 33 and the drain electrode 34 are alternately arranged. All the source electrodes 33 are connected in common and connected to the input terminal IN, and the gate electrode 32 and the drain electrode 34 arranged on the left side of FIG.
The gate electrode 32 and the drain electrode 34 disposed on the right side are connected to the control terminal Ctr2 and the output terminal OUT2, respectively, to tr1 and the output terminal OUT1.

Complementary control signals are applied to the control terminal Ctr1 and the control terminal Ctr2. For example, when a control signal of 0 V is applied to the control terminal Ctr 1 and a control signal of +3 V is applied to the control terminal Ctr 2, the channel region 52 is affected by the gate potential of the transistor 7. That is, the channel region 5
2 is a forward potential difference of the Schottky barrier diode formed by the gate electrode 32 from the control potential 3 V (about 0.3 V).
V) and is fixed at a potential (2.7 V) lowered by the amount of V).
As a result, a depletion layer 53 is generated below the gate electrode 32 of the first transistor 6 according to the potential difference between the two, and cuts off between the source and the drain. No depletion layer is formed below the gate electrode 32 of the second transistor 7. That is, the second transistor 7 is turned on to transmit a signal from the input terminal IN to the output terminal OUT2, and the first transistor 6
It becomes FF state. Further, the depletion layer 53 prevents the channel current 54 of the second transistor 7 from flowing to the first transistor. When the potential relationship of the control signals applied to the control terminals Ctr1 and Ctr2 is reversed,
A depletion layer is generated below the gate electrode 32 of the second transistor 7, enabling the same operation as described above.

As described above, according to the semiconductor device of the present invention,
By changing the length of the cell 35 depending on the location, for example, by arranging it also in the blank portion (second region 51) between the electrode pads 43 and 45, the entire length of the cell (channel length) is maintained. The size of the semiconductor chip can be reduced.

Further, since the channel region 52 is not separated by the first and second transistors 6 and 7 but is formed as a continuous region, each electrode can be continuously arranged close to each other. Thereby, the chip size of the semiconductor chip can be further reduced. It goes without saying that the source and drain of the first and second transistors 6 and 7 may be replaced with the drain and source.

[0021]

As described above, according to the present invention, by forming the channel region 52 as a continuous region without being separated, the first and second transistors 6, 7 having a reduced chip size can be manufactured. This has the advantage that an integrated monolithic microwave integrated circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the present invention.

4A is a cross-sectional view for explaining a conventional example, and FIG.
It is a circuit diagram.

FIG. 5 is a plan view for explaining a conventional example.

Claims (4)

[Claims] 1. A semiconductor device, wherein first and second transistors having one of a source and a drain connected in common are arranged on a common channel region. 2. A channel region of one conductivity type formed on a surface of a semi-insulating substrate, a gate electrode in Schottky contact with the surface of the channel region, and an ohmic contact with a surface of the channel region next to the gate electrode. A source / drain electrode, and a gate electrode and a source / drain region extending to form a transistor cell. A plurality of the transistor cells are juxtaposed and the transistor cells are connected in parallel to form a first and a second transistor. Wherein the first and second transistor cells are arranged in a common channel region. 3. The semiconductor device according to claim 2, wherein one of said source / drain electrodes is used as a common electrode, and said transistor cells are arranged symmetrically with respect to said common electrode. 4. The semiconductor device according to claim 2, wherein an inverted signal is applied to each of the gates of said first and second transistors.