JP2001015455A - Method and apparatus for producing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus for producing a semiconductor device in which generation of defective chips can be suppressed even if the position of the claw of a fabricating apparatus enters the effective area border line on a wafer. SOLUTION: In the method for producing a semiconductor device, an imaginary effective area border line 11 is set on the surface of a waver 7 after it is placed in a production apparatus and a plurality of imaginary danger areas 12-15 having a predetermined width are set on the inside of the border line 11. The danger areas are weighted, an effective chip forming region 20 is set on the surface of the wafer 7, the number of effective chips 22 is calculated, danger areas superposed on the effective chips 22 are detected, the sum of the weight of danger areas is calculated and then the position of the wafer 7 is altered such that the sum of the weight is minimized for each chip and the number of effective chips is maximized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method and an apparatus for manufacturing a semiconductor device capable of imposing a wafer while suppressing generation of defective chips.

[0002]

2. Description of the Related Art FIGS. 4 and 5 are plan views for explaining a conventional method of manufacturing a semiconductor device.

Hereinafter, a specific method of imposing a wafer will be described with reference to the drawings.

[0004] Imposition refers to determining the chip arrangement on a wafer, which is performed by photolithography.

First, as shown in FIG. 4, a virtual effective area boundary line 11 where an effective chip can be formed on the surface of the wafer 7 is assumed. The effective area boundary line 11 is usually located inside the portion where the wafer 7 is fixed by the claws 1 to 4 and is arranged about 2 mm inside the outer periphery of the wafer 7. The inside of the effective area boundary line 11 on the surface of the wafer 7 is the boundary of the area where chips can be formed.

Next, a chip forming area map 16 in which a plurality of chips 21 are arranged on a plane is superimposed on the surface of the wafer 7. Thereafter, the chips arranged within the effective area boundary line 11 in the map 16 are regarded as valid chips, and the valid chip formation region 20 is determined. Next, the number of valid chips 22 in the valid chip formation region 20 is calculated.

Then, the position of the chip formation map 16 is offset a plurality of times on the surface of the wafer 7, an effective chip formation area is determined for each arbitrary offset, and the number of effective chips is calculated. Then, any one of the map offset values that maximizes the number of effective chips is adopted. FIG.
Is an example in which the number of effective chips is the largest, and the number of effective chips is five more than the map offset shown in FIG. Thus, the wafer 7
Perform imposition.

[0008]

As described above, in the conventional method for manufacturing a semiconductor device, any one of the map offset values that maximizes the number of effective chips is adopted. For this reason, the effective chip 22 in the effective chip formation region 20
Among them, the effective chip formation region 20 is arranged without considering the distance to the effective area boundary line 11 of the chip closest to the effective area boundary line 11. Therefore,
For example, each effective chip 22 located at a corner in the effective chip formation region 20 shown in FIG.
May not be constant, and one of the corner chips 22 may be particularly close to the effective area boundary 11 and the other chips may be relatively far from the boundary 11. It is thought that there are many.

On the other hand, in the conventional wafer imposition, when the wafer 7 is fixed in the manufacturing apparatus by the claws 1 to 4, the claws may hit the effective area boundary line 11. When such an abnormality in fixing the wafer occurs, even if the chip is formed in a region closer to the boundary 11 even inside the boundary 11 of the effective area, a chip formed in a region farther than the boundary 11 is formed. The probability of defective products is high. In other words, a chip may become a non-defective product or a defective product due to a difference in imposition position of several tens of μm. For this reason, it is desirable to arrange the effective chip forming region 20 on the wafer 7 so that the distance between each of the effective chips 21 to 24 at the four corners and the effective area boundary line 11 is constant to some extent.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to fix the position of a claw within an effective area boundary on a wafer when the wafer is fixed by a claw in a manufacturing apparatus. It is an object of the present invention to provide a method and an apparatus for manufacturing a semiconductor device which can suppress the generation of a defective chip even if it enters.

[0011]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device by imposing a wafer which determines the arrangement of chips on the wafer. After placing the wafer in the manufacturing apparatus, assuming a virtual effective area boundary line that can form an effective chip on the surface of the wafer, a plurality of dangerous areas having a certain width inside the effective area boundary line are defined. Assuming, weighting the dangerous area, increasing the weight closer to the effective area boundary line, and disposing an effective chip forming area that actually forms a plurality of chips on the surface of the wafer, The number of valid chips formed in the valid chip forming region is calculated, and at least a part of the valid chips is formed so as to overlap the dangerous area. And for each of the selected chips, detecting a dangerous area formed by overlapping, calculating the sum of the weights of the dangerous areas, the sum of the weights for each of the chips is minimized, and Imposition is performed on the wafer by changing the position of the wafer so that the number of effective chips is maximized.

In the above-described method of manufacturing a semiconductor device, the wafers are imposed so that the sum of the weights of the dangerous areas for each chip is minimized and the number of effective chips is maximized. The effective chip formation region can be arranged on the wafer such that the distance between each of the chips and the boundary of the effective area becomes constant to some extent. For this reason, when the wafer is fixed with the claw in the manufacturing apparatus, even if an abnormality such as the position of the claw enters the boundary of the effective area on the wafer, the occurrence of defective chips can be suppressed.

A semiconductor device manufacturing apparatus according to the present invention performs wafer imposition for determining the arrangement of chips on a wafer,
A manufacturing apparatus for manufacturing a semiconductor device, wherein after setting a wafer in the manufacturing apparatus, a boundary estimating means for estimating a virtual effective area boundary capable of forming an effective chip on a surface of the wafer; Dangerous area assumption means for assuming a plurality of dangerous areas having a certain width inside the boundary line, weighting means for weighting the dangerous area, weighting means for increasing the weight closer to the effective area boundary line,
An arranging means for arranging an effective chip forming area for actually forming a plurality of chips on the surface of the wafer, and a first calculating means for calculating the number of the plurality of effective chips formed in the effective chip forming area Selecting means for selecting a chip at least a part of which is to be formed so as to overlap with the dangerous area, among the plurality of valid chips, and for each chip selected by the selecting means, Detecting means for detecting a dangerous area to be detected, second calculating means for calculating the sum of the weights of the dangerous areas detected by the detecting means for each of the chips, and each chip calculated by the second calculating means. The position of the wafer is changed such that the sum of the weights of the first and the second means is minimized and the number of effective chips calculated by the first calculation means is maximized. Characterized by comprising a means.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are plan views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a diagram showing a procedure for manufacturing the semiconductor device according to the embodiment of the present invention.

A specific method of imposing a wafer will be described with reference to the drawings.

[0017] Imposition refers to determining the chip arrangement on a wafer, which is performed by photolithography.

First, the surface of the wafer 7 is photographed by photographing means (not shown) to obtain image data of the surface of the wafer 7. Next, as shown in FIG. 2, a virtual effective area boundary line 11 where an effective chip can be formed is assumed in the image data of the surface of the wafer 7 (ST1 shown in FIG. 3). This estimation of the effective area boundary is performed by boundary estimation means (not shown). Note that the effective area boundary line 11 is usually located inside a portion where the wafer 7 is fixed by the claws 1 to 4, and is arranged, for example, about 2 mm inside from the outer periphery of the wafer 7. The inside of the effective area boundary line 11 on the surface of the wafer 7 is the boundary of the area where chips can be formed.

Thereafter, in the image data, first to fourth dangerous areas 12 to 15 having a fixed width (for example, 0.5 mm) are virtually arranged inside the effective area boundary line 11 (see FIG. 3). ST2). The arrangement of the dangerous area is performed by a dangerous area estimating means (not shown).
The first dangerous area 12 is inscribed in the effective area boundary 11, and the second dangerous area 13 is the first dangerous area 12.
Inscribed in The third dangerous area 14 is inscribed in the second dangerous area 13, and the fourth dangerous area 15 is the third dangerous area 15.
In danger area 14.

Next, a weight is assigned to each of the dangerous areas 12 to 15 (ST3 shown in FIG. 3). The weight increases as it approaches the effective area boundary line 11. This weighting is performed by weighting means (not shown). Therefore, for example, the weight of the first dangerous area 12 is 4, the weight of the second dangerous area 13 is 3, the weight of the third dangerous area 14 is 2, and the weight of the fourth dangerous area 15 is 1 And

Thereafter, a chip forming area map 16 in which a plurality of chips 21 are arranged on a plane is superimposed on the surface of the wafer 7. Next, the chips arranged within the effective area boundary line 11 in this map 16 are regarded as effective chips,
Determine the effective chip formation region 20 (ST shown in FIG. 3)
4). The arrangement of the effective chip formation region is performed by an arrangement means (not shown). Next, the number of valid chips 22 in the valid chip formation region 20 is calculated. The calculation of the number of effective chips is performed by first calculating means (not shown).

Thereafter, the position of the chip formation map 16 is offset a plurality of times on the surface of the wafer 7, an effective chip formation area is determined for each arbitrary offset, and the number of effective chips is calculated. Then, a map offset that maximizes the number of effective chips is adopted. The map offset shown in FIG. 1 is one of the ones in which the number of effective chips is the largest, and the map offset shown in FIG.
The number is increasing.

Next, the following processing is performed for each of the map offsets in which the number of adopted effective chips is maximized. A plurality of effective chips 22 arranged in the effective chip forming area 20
At least a part of the first to fourth dangerous areas 12
A chip to be formed so as to overlap with １５15 is selected (ST5 shown in FIG. 3). The selection of the chip is performed by selection means (not shown).

For each of the selected valid chips, overlapping dangerous areas 12 to 15 are detected (ST6). The detection of the dangerous area is performed by detection means (not shown). In this case, for example, for the chip 22a shown in FIG.
15 is detected, and the third and fourth chips 22b are detected.
Dangerous areas 14 and 15 are detected.

Next, the sum of the weights of the dangerous areas is calculated for each chip (ST7). The calculation of the sum of the weights is performed by a second calculating unit (not shown). In this case, the sum of the weights is 10 for the chip 22a, and 3 for the chip 22b.

Thereafter, the sum of the weights calculated for each chip is compared for each map offset (ST8). The comparison of the sum of the weights is performed by comparing means (not shown). Then, the position of the wafer 7 is changed by using a map offset that minimizes the sum of the weights for each chip (ST9). This change of the wafer position is performed by a position changing means (not shown).

That is, the position of the effective chip formation region 20 is offset a plurality of times on the surface of the wafer 7 and a map offset that maximizes the number of effective chips is adopted. Calculate the sum of the weights. Then, a map offset value that minimizes the sum of the weights of the chips is adopted. The imposition on the wafer 7 is performed in this manner.

According to the above embodiment, the wafer 7 is imposed so that the sum of the weights of the respective chips in the dangerous area is minimized and the number of effective chips is maximized. Thereby, the distance of the outermost effective chip to the effective area boundary line 11 can be equalized, and the distance between the effective chip formation region 20 and the effective area boundary line 11 can be equalized. For this reason, even if an abnormality such that the positions of the claws 1 to 4 of the manufacturing apparatus enter the inside of the effective area boundary line 11 occurs,
The occurrence of defective chips can be suppressed. Therefore, the yield can be stabilized.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
In the above embodiment, the first to fourth dangerous areas 12 to 1
5, the weights are set to 4, 3, 2, and 1, however, other weights can be used.

[0030]

As described above, according to the present invention, the wafers are imposed such that the sum of the weights of the dangerous areas for each chip is minimized and the number of effective chips is maximized. Therefore, it is possible to provide a method and an apparatus for manufacturing a semiconductor device which can suppress generation of defective chips even when the position of the claw is within the boundary of the effective area on the wafer when the wafer is fixed by the claw in the manufacturing apparatus. it can.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, in which a distance to an effective area boundary of an outermost effective chip is equalized.

FIG. 2 is a plan view for explaining the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing procedure of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a plan view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 5 is a plan view for explaining a conventional method for manufacturing a semiconductor device, and shows an example of a map offset at which the number of effective chips is maximized.

[Description of Signs] 1-4 claw 7 wafer 11 effective area boundary line 12-15 first
To the fourth dangerous area 16 Chip forming area map 20 Effective chip forming area 21 Chip 22 Effective chip

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device by imposing a wafer which determines the arrangement of chips on the wafer, wherein an effective chip can be formed on a surface of the wafer after the wafer is installed in a manufacturing apparatus. Assuming a virtual effective area boundary line, assuming a plurality of dangerous areas having a certain width inside the effective area boundary line, weighting the dangerous area, the closer the weight is to the effective area boundary line, Increasing the effective chip forming area that actually forms a plurality of chips on the surface of the wafer; calculating the number of the plurality of effective chips formed in the effective chip forming area; Among the chips, at least a part is selected to be formed so as to overlap with the dangerous area, and each of the selected chips is formed so as to overlap. Detecting a rugged area, calculating the sum of the weights of the dangerous areas, and changing the position of the wafer so that the sum of the weights for each chip is minimized and the number of effective chips is maximized A method for manufacturing a semiconductor device, comprising imposing the wafer. 2. A manufacturing apparatus for manufacturing a semiconductor device by imposing a wafer for arranging chips on the wafer, and forming an effective chip on a surface of the wafer after installing the wafer in the manufacturing apparatus. Boundary line assumption means for assuming a possible virtual effective area boundary line, Danger area assumption means for assuming a plurality of danger areas having a certain width inside the effective area boundary line, and weighting the danger area, Weighting means for increasing the weight as the weight is closer to the effective area boundary line; arranging means for arranging an effective chip forming area where a plurality of chips are actually formed on the surface of the wafer; and the effective chip forming area. First calculating means for calculating the number of a plurality of effective chips formed in the plurality of effective chips, and at least a part of the plurality of effective chips overlaps the dangerous area. Selecting means for selecting a chip to be formed; and for each chip selected by the selecting means,
Detecting means for detecting a dangerous area formed by overlapping; second calculating means for calculating the sum of the weights of the dangerous areas detected by the detecting means for each of the chips; calculating by the second calculating means Means for changing the position of the wafer such that the sum of the weights for each of the chips thus obtained is minimized and the number of effective chips calculated by the first calculation means is maximized. Characteristic semiconductor device manufacturing equipment.